CN111399905A - Computing method, device and related products - Google Patents

Abstract

The disclosure relates to an operation method, an operation device and a related product. The machine learning device comprises one or more instruction processing devices, is used for acquiring data to be operated and control information from other processing devices, executes specified machine learning operation and transmits the execution result to other processing devices through an I/O interface; when the machine learning arithmetic device includes a plurality of instruction processing devices, the plurality of instruction processing devices can be connected to each other by a specific configuration to transfer data. The command processing devices are interconnected through a Peripheral Component Interface Express (PCIE) bus and transmit data; the plurality of instruction processing devices share the same control system or own control system and share the memory or own memory; the interconnection mode of the plurality of instruction processing apparatuses is an arbitrary interconnection topology. The operation method, the operation device and the related products provided by the embodiment of the disclosure have the advantages of wide application range, high instruction processing efficiency and high instruction processing speed.

Description

Computing method, device and related products

technical field

The present disclosure relates to the field of computer technology, and in particular, to a vector search instruction processing method, device and related products.

Background technique

With the continuous development of science and technology, the use of machine learning, especially neural network algorithms, is becoming more and more extensive. It has been well used in image recognition, speech recognition, natural language processing and other fields. However, due to the increasing complexity of neural network algorithms, the types and quantities of data operations involved continue to increase. In the related art, the search operation on vector data has low efficiency and slow speed.

SUMMARY OF THE INVENTION

In view of this, the present disclosure proposes a vector search instruction processing method, device and related products, so as to improve the efficiency and speed of the vector search operation.

According to a first aspect of the present disclosure, there is provided a vector lookup instruction processing device, the device comprising:

The control module is configured to parse the received vector search instruction, obtain the operation code and operation field of the vector search instruction, and determine the waiting period required to execute the vector search instruction according to the operation code and the operation field. lookup vector, lookup condition and target address;

an arithmetic module, configured to sequentially determine whether a plurality of to-be-checked numbers representing the to-be-searched vector satisfy the search condition, determine the to-be-checked number that satisfies the search condition as a target number, and determine the storage address of the target number into the target address as the search result,

The operation code is used to indicate that the operation performed by the vector search instruction on the vector data is a search operation, and the operation field includes the address of the vector to be searched and the target address.

According to a second aspect of the present disclosure, there is provided a machine learning computing device, the device comprising:

One or more vector search instruction processing devices described in the first aspect above are used to obtain data to be operated and control information from other processing devices, perform specified machine learning operations, and transmit the execution results to the I/O interface. other processing devices;

When the machine learning computing device includes a plurality of the vector search instruction processing devices, the plurality of the vector search instruction processing devices can be connected through a specific structure and data can be transmitted;

Wherein, a plurality of the vector search instruction processing devices are interconnected and transmit data through the fast peripheral device interconnection bus PCIE bus to support larger-scale machine learning operations; a plurality of the vector search instruction processing devices share the same control system Or have their own control systems; a plurality of the vector search instruction processing devices share memory or have their own memory; the interconnection mode of the multiple vector search instruction processing devices is any interconnection topology.

According to a third aspect of the present disclosure, there is provided a combined processing device, the device comprising:

The machine learning computing device, universal interconnection interface, and other processing devices described in the second aspect above;

The machine learning computing device interacts with the other processing devices to jointly complete the computing operation specified by the user.

According to a fourth aspect of the present disclosure, there is provided a machine learning chip, where the machine learning chip includes the machine learning network computing device described in the second aspect or the combined processing device described in the third aspect.

According to a fifth aspect of the present disclosure, a machine learning chip packaging structure is provided, and the machine learning chip packaging structure includes the machine learning chip described in the fourth aspect.

According to a sixth aspect of the present disclosure, there is provided a board card including the machine learning chip packaging structure described in the fifth aspect.

According to a seventh aspect of the present disclosure, an electronic device is provided, and the electronic device includes the machine learning chip described in the fourth aspect or the board card described in the sixth aspect.

According to an eighth aspect of the present disclosure, there is provided a vector lookup instruction processing method, the method is applied to a vector lookup instruction processing apparatus, and the method includes:

Analyze the received vector search instruction, obtain the operation code and operation field of the vector search instruction, and determine the vector to be searched and search conditions required to execute the vector search instruction according to the operation code and the operation field and destination address;

Determine in turn whether a plurality of to-be-checked numbers representing the to-be-searched vector satisfy the search condition, determine the to-be-checked number that satisfies the search condition as the target number, and store the storage address of the target number as the search result in the the target address,

The operation code is used to indicate that the operation performed by the vector search instruction on the vector data is a search operation, and the operation field includes the address of the vector to be searched and the target address.

In some embodiments, the electronic device includes a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, Cameras, projectors, watches, headphones, mobile storage, wearables, vehicles, home appliances, and/or medical equipment.

In some embodiments, the vehicles include airplanes, ships and/or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; the medical Equipment includes MRI machines, ultrasound machines and/or electrocardiographs.

The vector search instruction processing method, device, and related products provided by the embodiments of the present disclosure include a control module and an operation module. The control module is used to parse the received vector search instruction, obtain the operation code and operation domain of the vector search instruction, and determine the to-be-searched vector, search condition and target address required to execute the vector search instruction according to the opcode and operation domain. The operation module is used to sequentially determine whether a plurality of to-be-checked numbers representing the to-be-searched vector satisfy the search condition, determine the to-be-checked number satisfying the search condition as the target number, and store the storage address of the target number as the search result in the target address. The vector search instruction processing method, device and related products provided by the embodiments of the present disclosure have a wide range of applications, and have high processing efficiency and high processing speed for the vector search instruction.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure, and together with the description, serve to explain the principles of the disclosure.

FIG. 1 shows a block diagram of a vector lookup instruction processing apparatus according to an embodiment of the present disclosure.

FIG. 2 shows a block diagram of a vector search instruction processing apparatus according to an embodiment of the present disclosure.

3a-3c are schematic diagrams illustrating application scenarios of a vector search instruction processing apparatus according to an embodiment of the present disclosure.

4a and 4b illustrate block diagrams of a combined processing apparatus according to an embodiment of the present disclosure.

FIG. 5 shows a schematic structural diagram of a board according to an embodiment of the present disclosure.

FIG. 6 shows a flowchart of a method for processing a vector search instruction according to an embodiment of the present disclosure.

Detailed ways

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numbers in the figures denote elements that have the same or similar functions. While various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following detailed description. It will be understood by those skilled in the art that the present disclosure may be practiced without certain specific details. In some instances, methods, means, components and circuits well known to those skilled in the art have not been described in detail so as not to obscure the subject matter of the present disclosure.

FIG. 1 shows a block diagram of a vector lookup instruction processing apparatus according to an embodiment of the present disclosure. As shown in FIG. 1 , the device includes a control module 11 and an arithmetic module 12 .

The control module 11 is used to parse the received vector search instruction, obtain the operation code and operation domain of the vector search instruction, and determine the vector to be searched, the search condition and the target required to execute the vector search instruction according to the operation code and the operation domain address. The operation code is used to indicate that the operation performed by the vector search instruction on the vector data is a search operation, and the operation domain includes the address of the vector to be searched and the target address.

The arithmetic module 12 is used to sequentially determine whether a plurality of to-be-searched numbers representing the to-be-searched vector satisfy the search condition, determine the to-be-searched number that satisfies the search condition as the target number, and store the storage address of the target number as the search result in the target address .

In this embodiment, the vector to be searched may be composed of multiple numbers to be searched. For example, the decimal representation of the to-be-searched vector m is (5, 6, 4), then the multiple to-be-searched numbers of the to-be-searched vector m are "5", "6" and "4". The vector to be searched can also be represented by a string in binary, hexadecimal, or the like. For example, the binary representation of the vector m to be searched is "101110100", where "101", "110" and "100" are multiple numbers to be searched for the vector m to be searched, respectively when the vector m to be searched is converted to decimal The corresponding numbers are 5, 6, and 4. The control module can obtain the vector to be searched from the address of the vector to be searched. The address of the vector to be searched may be the first address where the vector to be searched is stored, or the like. The control module can obtain the vector search instruction and the vector to be searched through the data input and output unit, and the data input and output unit can be one or more data I/O interfaces or I/O pins.

In this embodiment, the operation code may be the part of the instruction or field (usually represented by code) specified in the computer program to perform the operation, and the instruction sequence number, which is used to inform the device that executes the instruction which instruction needs to be executed. . The operation domain can be the source of all data required to execute the corresponding instruction. All data required to execute the corresponding instruction includes parameter data, the vector to be searched, the corresponding operation method, or the storage parameter data, the vector to be searched, the corresponding operation the address of the method, etc. For a vector search instruction, it must include an operation code and an operation field, wherein the operation field at least includes the address of the vector to be searched and the target address.

It should be understood that those skilled in the art can set the instruction format of the vector search instruction and the included operation codes and operation fields as required, which is not limited in the present disclosure.

In this embodiment, the device may include one or more control modules and one or more operation modules, and the number of control modules and operation modules may be set according to actual needs, which is not limited in the present disclosure.

The vector search instruction processing device provided by the embodiment of the present disclosure includes a control module and an operation module. The control module is used to parse the received vector search instruction, obtain the operation code and operation domain of the vector search instruction, and determine the to-be-searched vector, search condition and target address required to execute the vector search instruction according to the opcode and operation domain. The operation module is used to sequentially determine whether a plurality of to-be-checked numbers representing the to-be-searched vector satisfy the search condition, determine the to-be-checked number satisfying the search condition as the target number, and store the storage address of the target number as the search result in the target address. The vector search instruction processing device provided by the embodiment of the present disclosure has a wide range of applications, and has high processing efficiency and high processing speed for the vector search instruction.

In a possible implementation manner, the number to be checked that satisfies the search condition may include at least one of the following:

The value is the specified multiple of the specified value, and the order is the number to be checked in the specified order;

The number to be checked whose value is in the specified value range;

Numeric is the number to look up in the specified multiple of the specified value.

The specified ordering may include at least one of the following: the ordering of the numbers to be checked is the nth number of the numbers to be checked whose numerical value is a specified multiple of the specified value, where n is a positive integer greater than or equal to 1; the ordering of the numbers to be checked is The value is the m-th penultimate of the number to be checked that is a specified multiple of the specified value, where m is a positive integer greater than or equal to 1. Among them, m and n are less than or equal to the number of numbers to be searched in the vector to be searched.

In this implementation, it is possible to sort the number to be checked as the nth number to be checked whose value is a specified multiple of the specified value, and the order of the number to be checked as the number to be checked whose value is a specified multiple of the specified value. The m-th from the bottom in the number lookup sets different expressions, etc., to distinguish the specified order of the reciprocal and positive numbers. In the specified sorting, the expression of "the number to be checked is the nth number to be searched whose value is a specified multiple of the specified value" can be set as "0n" in the vector search instruction, and the expression of "to be searched" in the specified sorting can be set. The order of the number to be searched is the last mth in the number to be searched whose value is a specified multiple of the specified value. The expression in the vector search instruction is "m0". Those skilled in the art can set the expression manner of the specified sorting according to actual needs, which is not limited in the present disclosure.

In a possible implementation, the specified value may be a numerical value such as 0, 1, 2, and 3. The specified multiple can be 1 times (that is, the value is the same as the specified value), 2 times, 3 times and other multiples.

For example, the target number found by the vector search instruction may be the first 1, the last 1, the first 2 to be checked three times the number to be checked, and the last 2 of the multiple to-be-checked numbers of the vector to be searched. 3 times the number to be checked, the number to be checked less than 5, the number to be checked greater than 9, etc.

In a possible implementation, the operation field may also include the input length. The control module 11 is further configured to obtain the vector to be searched from the address of the vector to be searched according to the input length.

In this implementation manner, the length of the vector to be searched obtained from the address of the vector to be searched according to the input length needs to be equal to the input length, or needs to be smaller than the input length.

In a possible implementation manner, when the input length is not included in the operation field, the vector to be searched may be obtained according to a preset default input length. All data in the address of the vector to be searched can also be obtained as the vector to be searched.

In a possible implementation manner, the operation field may further include the width of the number to be checked. The operation module 12 is further configured to determine a plurality of numbers to be searched from the vector to be searched according to the width of the number to be searched.

In this implementation manner, the width of the number to be searched may represent the width corresponding to each number to be searched in the character string of the vector to be searched. When the operation field includes the width of the number to be searched, a plurality of sets of character strings with the width of the number to be searched may be determined from the character string representing the vector to be searched, and each set of strings corresponds to a number to be searched. For example, if the width of the number to be searched is 3, the vector m to be searched (expressed as (5,6,4) when converted to decimal) is "101110100", and the multiple numbers to be searched of the vector m to be searched are "101" and "110" " and "100", the multiple numbers to be searched "101", "110" and "100" are the corresponding numbers 5, 6, and 4 when the vector m to be searched is converted to decimal. If the width of the number to be searched is 1, the multiple numbers to be searched of the vector m to be searched are "1", "0", "1", "1", "1", "0", "1", "0" and "0", or when the width of the number to be searched is 2, 4 and other widths other than 3, the obtained multiple to-be-searched numbers of the to-be-searched vector m are only numbers composed of strings and converted to the to-be-searched vector m The corresponding numbers 5, 6, and 4 in decimal have nothing to do with each other.

In a possible implementation manner, the operation domain may further include search conditions. The control module 11 is further configured to determine the search condition according to the operation domain.

In this implementation manner, when a search condition is included in the operation domain, the search condition in the operation domain can be directly obtained.

In a possible implementation manner, the control module 11 is further configured to determine the search condition according to the operation code. Wherein, the opcode is also used to indicate the search condition of the vector search instruction.

In this implementation, different operation codes can be set to represent different search conditions. The width of the number to be checked can also be determined according to the opcode or the default width.

For example, you can set the opcode "Find_vfirst" to be the first 1 in the multiple to-be-searched numbers of the vector to be searched (the width of the to-be-searched number is greater than 1, and the to-be-searched number that satisfies the search condition is: the value is the specified value The 1st number to be checked in the double of the number to be checked). The opcode "Find_vlast" is to find the last 1 of the multiple numbers to be searched for the vector to be searched (the width of the number to be searched is greater than 1, and the number to be searched that satisfies the search condition is: the number to be searched whose value is twice the specified value) the penultimate number to be checked). When the opcode is "Find_vfirst" and "Find_vlast", the width of the number to be searched can be further determined according to the opcode, or the default width can be determined as the width of the number to be searched, and then a plurality of numbers to be searched with the width of the number to be searched of the vector to be searched can be obtained. .

FIG. 2 shows a block diagram of a vector search instruction processing apparatus according to an embodiment of the present disclosure. In a possible implementation manner, as shown in FIG. 2 , the operation module 12 may include at least one comparator 121 for comparing multiple numbers to be checked with search conditions to obtain a comparison result, so as to facilitate determination according to the comparison result Whether the number to be checked satisfies the search conditions.

For example, what the vector search instruction is looking for is: the first one of the number to be searched whose value is 1 (that is, the value is twice the specified value of 1). The value of the number to be checked is compared with the specified value "1", and then it can be determined whether the value of the number to be checked is equal to the specified value "1", and the value is equal to the specified value "1" and sorted to be equal to the specified value "1" The first number to be searched in the number to be searched is determined as the target number, and the storage address of the target number is stored in the target address as the search result. The number of comparators may be set according to the size of the amount of data to be compared, the processing speed and efficiency of the comparison, and other requirements, which are not limited in the present disclosure.

In a possible implementation manner, as shown in FIG. 2 , the apparatus may further include a storage module 13 . The storage module 13 is used for storing the vector to be searched.

In this implementation, the storage module may include one or more of a memory, a cache, and a register, and the cache may include a temporary cache. The vector to be searched may be stored in the memory, cache and/or register in the storage module as required, which is not limited in the present disclosure.

In a possible implementation manner, the apparatus may further include a direct memory access module for reading or storing data from the storage module.

In a possible implementation manner, as shown in FIG. 2 , the control module 11 may include an instruction storage sub-module 111 , an instruction processing sub-module 112 and a queue storage sub-module 113 .

The instruction storage sub-module 111 is used for storing vector search instructions.

The instruction processing sub-module 112 is used to parse the vector search instruction to obtain the operation code and operation domain of the vector search instruction.

The queue storage sub-module 113 is used to store an instruction queue, and the instruction queue includes a plurality of instructions to be executed sequentially arranged in an execution order, and the multiple instructions to be executed may include a vector search instruction. The plurality of instructions to be executed may include other computational instructions that may also include vector lookup instructions.

In this implementation manner, the execution order of the plurality of to-be-executed commands can be arranged according to the receiving time and priority level of the to-be-executed commands to obtain the command queue, so as to execute the plurality of to-be-executed commands in sequence according to the command queue.

In a possible implementation manner, as shown in FIG. 2 , the control module 11 may further include a dependency relationship processing sub-module 114 .

The dependency relationship processing sub-module 114 is configured to cache the first to-be-executed instruction in the In the storage sub-module 112 , after the execution of the zeroth to-be-executed instruction is completed, the first to-be-executed instruction is extracted from the instruction storage sub-module 112 and sent to the operation module 12 . Wherein, the first to-be-executed instruction and the zeroth to-be-executed instruction are instructions in a plurality of to-be-executed instructions.

Wherein, the relationship between the first instruction to be executed and the zeroth instruction to be executed before the first instruction to be executed includes: a first storage address range for storing data required by the first instruction to be executed and data required for storing the zeroth instruction to be executed The zeroth memory address range of has overlapping regions. Conversely, if there is no association between the first instruction to be executed and the zeroth instruction to be executed, it may be that the first storage address interval and the zeroth storage address interval have no overlapping area.

In this way, according to the dependencies between the instructions to be executed, after the execution of the previous instruction to be executed is completed, the subsequent instruction to be executed is executed to ensure the accuracy of the operation result.

In a possible implementation manner, the instruction format of the vector search instruction may be as shown in Table 1 below, and the operation code and the position of the operation code may be set. And in Table 2, the conventional vector lookup instruction (Find) is given, and the conventional vector lookup instruction can be used to find any number in the vector to be looked up; And in Table 2, the example of the vector lookup instruction is given, and defines Two special types of vector search instructions (Find_vfirst, Find_vlast) need to include opcodes and operation fields. Using a special type of vector search instruction to search the vector to be searched can simplify the instruction processing process and save the search time.

Table 1 Instruction format

Wherein, when the search condition only includes the specified numerical range, the number to be searched that satisfies the search condition refers to the number to be searched whose numerical value is a specified multiple of the specified value.

When the search condition includes the specified value and the specified sort, the number to be searched that satisfies the search condition refers to the number to be searched that the numerical value is equal to the specified value and the sorting is the specified sort.

When the search condition includes the specified value and the specified multiple, the number to be searched that satisfies the search condition refers to the number to be searched whose value is the specified multiple of the specified value.

When the search condition includes the specified value, the specified multiple, and the specified order, the number to be searched that satisfies the search condition refers to the number to be searched that the numerical value is the specified multiple of the specified value and the order is the specified order.

Table 2 Examples of vector lookup instructions

Among them, for the vector search instruction whose opcode is "Find_vfirst", the number to be searched that satisfies the search condition is: the numerical value is twice the specified value 1 (that is, the numerical value is equal to the specified value 1), and the sorted numerical value is Specifies the 1st of the number to be checked that is double the value of 1. The width of the number to be checked is greater than 1.

For the vector search instruction whose opcode is "Find_vlast", the number to be searched that satisfies the search condition is: the value is twice the specified value 1 (that is, the value is equal to the specified value 1), and the sorted value is the specified value 1 The penultimate one of the double of the number to be checked. The width of the number to be checked is greater than 1.

It should be understood that those skilled in the art can set the operation code of the vector search instruction, the operation code in the instruction format, and the position of the operation field, which is not limited in the present disclosure.

In a possible implementation manner, the apparatus may be provided in a graphics processing unit (Graphics Processing Unit, GPU for short), a central processing unit (Central Processing Unit, CPU for short), and an embedded neural-network processing unit (Neural-network Processing Unit, abbreviated as NPU) among one or more of them.

It should be noted that although the above embodiments are used as examples to describe the vector search instruction processing apparatus as above, those skilled in the art can understand that the present disclosure should not be limited thereto. In fact, the user can flexibly set each module according to personal preferences and/or actual application scenarios, as long as it conforms to the technical solutions of the present disclosure.

Application example

In the following, an application example according to an embodiment of the present disclosure is given in conjunction with "using a vector search instruction processing apparatus to search for a vector to be searched" as an exemplary application scenario, so as to facilitate understanding of the flow of the vector search instruction processing apparatus. Those skilled in the art should understand that the following application examples are only for the purpose of facilitating the understanding of the embodiments of the present disclosure, and should not be regarded as limitations of the embodiments of the present disclosure.

3a-3c are schematic diagrams illustrating application scenarios of a vector search instruction processing apparatus according to an embodiment of the present disclosure. As shown in Fig. 3a-Fig. 3c, the process of processing the vector search instruction by the vector search instruction processing device is as follows.

First, assume that the vector a to be searched is "0101 1011 0001 0101 1100 0001 1001". Moreover, every four binary numbers represent a number of the vector a to be searched in decimal, that is, the vector a to be searched is (5, 11, 1, 5, 12, 1, 9) in decimal. For the convenience of distinguishing different vector search instructions, it is assumed that the storage addresses of the vector a to be searched are different in different vector search instructions.

The vector lookup instructions that the device needs to process include:

Vector Find Instruction 1: @Find#100#28#200#4#1#01

Vector Find Instruction 2: @Find_vfirst#101#28#201#4

Vector Find Instruction 3: @Find_vlast#102#28#202#4

Example 1

As shown in FIG. 3a, when receiving the vector search instruction 1, the control module 11 parses the vector search instruction 1, obtains the operation code of the vector search instruction 1 as Find, and determines the vector search instruction 1 according to the operation domain, to be searched The vector address is "100", the input length is "28", the target address is "200", and the specified sorting is "The sorting of the number to be searched is equal to the specified value (because the specified multiple position in vector search instruction 1 is empty, the multiple is specified by default. It is the first one in the number to be checked which is doubled)", the specified value is "1", and the width of the number to be checked is "4". Further, the control module 11 obtains the above-mentioned vector a "0101 1011 0001 0101 1100 0001 1001" with an input length of 28 from the address 200 of the vector to be searched.

The arithmetic module 12 obtains a plurality of to-be-checked numbers in turn from the to-be-searched vector a according to the width of the number to be checked as "4", and sequentially determines whether the values of the multiple to-be-checked numbers are equal to the specified value "1", and sets the numerical value equal to the specified value "1". The number to be searched which has a value of "1" and is sorted to be equal to the specified value of "1" is determined as the target number, and the storage address of the target number is stored in the target address 200 as the search result.

In this example, the operation module 12 first obtains the first to-be-checked number "0101" with a width of 4 from the to-be-searched vector a, and determines whether the value of the to-be-checked number "0101" is equal to the specified value "1". Since the value of the number to be searched "0101" is not 1, the operation module 12 continues to obtain the next number to be searched "1011" from the vector a to be searched, and determines whether the value of the number to be searched "1011" is equal to the specified value "1" . Since the value of the to-be-checked number "1011" is not 1, the operation module 12 continues to obtain the next to-be-checked number "0001" from the to-be-searched vector a, and determines whether the value of the to-be-checked number "0001" is equal to the specified value "1" . Since the value of the number to be checked "0001" is equal to 1, and its order is the specified order (that is, the order of the number to be checked is the first of the number to be checked equal to the specified value), the number to be checked "0001" is determined as For the target number, the storage address 500 of the number to be checked "0001" is stored in the target address 200 as the search result.

Example 2

As shown in Figure 3b, when receiving the vector search instruction 2, the control module 11 parses the vector search instruction 2, obtains the operation code of the vector search instruction 2 as Find_vfirst, and determines the vector to be searched for the vector search instruction 2 according to the operation domain The address is "101", the input length is "28", the destination address is "201", and the width of the number to be checked is "4". And, according to the opcode Find_vfirst, it is determined that the specified value of the vector search instruction 2 is "1", and the specified order is "the order of the number to be searched is the first of the number to be searched equal to the specified value". Further, the control module 11 obtains the above-mentioned vector a "0101 1011 0001 0101 1100 0001 1001" whose input length is 28 from the address 201 of the vector to be searched.

The arithmetic module 12 obtains a plurality of to-be-checked numbers in turn from the to-be-searched vector a according to the width of the number to be checked as "4", and sequentially determines whether the values of the multiple to-be-checked numbers are equal to the specified value "1", and sets the numerical value equal to the specified value "1". The number to be searched that has a value of "1" and is sorted to be equal to the first one of the numbers to be searched with the specified value of "1" is determined as the target number, and the storage address of the target number is stored in the target address 201 as the search result.

In this example, the operation module 12 first obtains the first to-be-checked number "0101" with a width of 4 from the to-be-searched vector a, and determines whether the value of the to-be-checked number "0101" is equal to the specified value "1". Since the value of the number to be searched "0101" is not 1, the operation module 12 continues to obtain the next number to be searched "1011" from the vector a to be searched, and determines whether the value of the number to be searched "1011" is equal to the specified value "1" . Since the value of the to-be-checked number "1011" is not 1, the operation module 12 continues to obtain the next to-be-checked number "0001" from the to-be-searched vector a, and determines whether the value of the to-be-checked number "0001" is equal to the specified value "1" . Since the value of the number to be checked "0001" is equal to 1, and its order is the specified order (that is, the order of the number to be checked is the first of the number to be checked equal to the specified value), the number to be checked "0001" is determined as For the target number, the storage address 501 of the number to be checked "0001" is stored in the target address 201 as the search result.

Example 3

As shown in Figure 3c, when the control module 11 receives the vector search instruction 3, it parses the vector search instruction 3, obtains the operation code of the vector search instruction 3 as Find_vlast, and determines the vector to be searched for the vector search instruction 3 according to the operation domain. The address is "102", the input length is "28", the destination address is "202", and the width of the number to be checked is "4". And, according to the opcode Find_vlast, it is determined that the specified value of the vector search instruction 3 is "1", and the specified order is "the order of the number to be searched is the last one in the number to be searched equal to the specified value". Further, the control module 11 obtains the above-mentioned vector a "0101 1011 0001 0101 1100 0001 1001" whose input length is 28 from the address 202 of the vector to be searched.

The arithmetic module 12 obtains a plurality of to-be-checked numbers in turn from the to-be-searched vector a according to the width of the number to be checked as "4", and sequentially determines whether the values of the multiple to-be-checked numbers are equal to the specified value "1", and sets the numerical value equal to the specified value "1". The number to be searched that has a value of "1" and is sorted to be equal to the specified value of "1" is determined as the target number, and the storage address of the target number is stored in the target address 202 as the search result.

In this example, the operation module 12 first obtains the penultimate number "1001" with a width of 4 from the vector a to be searched, and determines whether the value of the number "1001" to be searched is equal to the specified value "1". Since the value of the to-be-checked number "1001" is not 1, the operation module 12 continues to obtain the next to-be-checked number "0001" from the to-be-searched vector a, and judges whether the value of the to-be-checked number "0001" is equal to the specified value "1" . Since the value of the number to be checked "0001" is equal to 1, and its order is the specified order (that is, the order of the number to be checked is the last one in the number to be checked equal to the specified value), the number to be checked "0001" is determined. As the target number, the storage address 502 of the number to be searched "0001" is stored in the target address 202 as the search result.

In this way, the vector search instruction processing apparatus can process the vector search instructions quickly and efficiently.

The present disclosure provides a machine learning computing device, the machine learning computing device may include one or more of the above vector search instruction processing devices, used to obtain data to be operated and control information from other processing devices, and perform specified machine learning operations. The machine learning computing device can obtain vector search instructions from other machine learning computing devices or non-machine learning computing devices, and transmit the execution results to peripheral devices (also called other processing devices) through the I/O interface. Peripherals such as camera, monitor, mouse, keyboard, network card, wifi interface, server. When more than one vector search instruction processing device is included, the vector search instruction processing devices can be linked and transmitted through a specific structure, for example, interconnected and transmitted through the PCIE bus to support larger-scale neural network operations. At this time, the same control system can be shared, or there can be independent control systems; memory can be shared, or each accelerator can have its own memory. In addition, the interconnection method can be any interconnection topology.

The machine learning computing device has high compatibility and can be connected with various types of servers through the PCIE interface.

FIG. 4a shows a block diagram of a combined processing apparatus according to an embodiment of the present disclosure. As shown in Fig. 4a, the combined processing device includes the above-mentioned machine learning computing device, a general interconnection interface and other processing devices. The machine learning computing device interacts with other processing devices to jointly complete the operation specified by the user.

Other processing devices include one or more processor types among general-purpose/special-purpose processors such as a central processing unit (CPU), a graphics processing unit (GPU), and a neural network processor. The number of processors included in other processing devices is not limited. Other processing devices serve as the interface between the machine learning computing device and external data and control, including data handling, to complete basic controls such as starting and stopping the machine learning computing device; other processing devices can also cooperate with the machine learning computing device to complete computing tasks.

A universal interconnect interface for transferring data and control instructions between machine learning computing devices and other processing devices. The machine learning computing device obtains the required input data from other processing devices, and writes it into the storage device on the machine learning computing device chip; it can obtain control instructions from other processing devices and write it into the control cache on the machine learning computing device chip; The data in the storage module of the machine learning computing device can be read and transmitted to other processing devices.

FIG. 4b shows a block diagram of a combined processing apparatus according to an embodiment of the present disclosure. In a possible implementation manner, as shown in FIG. 4b, the combined processing device may further include a storage device, and the storage device is respectively connected to the machine learning computing device and other processing devices. The storage device is used to save data in the machine learning computing device and other processing devices, and is especially suitable for data that cannot be fully stored in the internal storage of the machine learning computing device or other processing devices.

The combined processing device can be used as an SOC system for mobile phones, robots, drones, video surveillance equipment and other equipment, effectively reducing the core area of the control part, improving the processing speed and reducing the overall power consumption. In this case, the general interconnection interface of the combined processing device is connected to certain components of the apparatus. Some components such as camera, monitor, mouse, keyboard, network card, wifi interface.

The present disclosure provides a machine learning chip, which includes the above-mentioned machine learning computing device or combined processing device.

The present disclosure provides a machine learning chip packaging structure, and the machine learning chip packaging structure includes the above-mentioned machine learning chip.

The present disclosure provides a board, and FIG. 5 shows a schematic structural diagram of the board according to an embodiment of the present disclosure. As shown in FIG. 5 , the board includes the above-mentioned machine learning chip packaging structure or the above-mentioned machine learning chip. In addition to the machine learning chip 389 , the board may also include other supporting components, including but not limited to: a storage device 390 , an interface device 391 and a control device 392 .

The storage device 390 is connected to the machine learning chip 389 (or the machine learning chip in the machine learning chip package structure) through a bus for storing data. The memory device 390 may include groups of memory cells 393 . Each group of storage units 393 is connected to the machine learning chip 389 through a bus. It can be understood that each group of storage units 393 may be DDR SDRAM (English: Double Data Rate SDRAM, double-rate synchronous dynamic random access memory).

DDR does not need to increase the clock frequency to double the speed of SDRAM. DDR allows data to be read out on both the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM.

In one embodiment, the memory device 390 may include four sets of memory cells 393 . Each set of memory cells 393 may include a plurality of DDR4 particles (chips). In one embodiment, the machine learning chip 389 may include four 72-bit DDR4 controllers inside, where 64 bits of the 72-bit DDR4 controllers are used for data transmission and 8 bits are used for ECC verification. It can be understood that when DDR4-3200 particles are used in each group of storage units 393, the theoretical bandwidth of data transmission can reach 25600MB/s.

In one embodiment, each set of memory cells 393 includes a plurality of double-rate synchronous dynamic random access memories arranged in parallel. DDR can transfer data twice in one clock cycle. A controller for controlling the DDR is provided in the machine learning chip 389 for controlling data transmission and data storage of each storage unit 393 .

The interface device 391 is electrically connected to the machine learning chip 389 (or the machine learning chip within the machine learning chip package structure). The interface device 391 is used to realize data transmission between the machine learning chip 389 and an external device (such as a server or a computer). For example, in one embodiment, the interface device 391 may be a standard PCIE interface. For example, the data to be processed is transmitted by the server to the machine learning chip 289 through a standard PCIE interface to realize data transfer. Preferably, when the PCIE 3.0X 16 interface is used for transmission, the theoretical bandwidth can reach 16000MB/s. In another embodiment, the interface device 391 may also be other interfaces, and the present disclosure does not limit the specific expression forms of the other interfaces, as long as the interface device can realize the switching function. In addition, the calculation result of the machine learning chip is still transmitted back to the external device (such as a server) by the interface device.

The control device 392 is electrically connected to the machine learning chip 389 . The control device 392 is used to monitor the state of the machine learning chip 389 . Specifically, the machine learning chip 389 and the control device 392 may be electrically connected through an SPI interface. The control device 392 may include a Micro Controller Unit (MCU). For example, the machine learning chip 389 may include multiple processing chips, multiple processing cores or multiple processing circuits, and may drive multiple loads. Therefore, the machine learning chip 389 can be in different working states such as multi-load and light-load. The control device can realize the regulation of the working states of multiple processing chips, multiple processing and/or multiple processing circuits in the machine learning chip.

The present disclosure provides an electronic device including the above-mentioned machine learning chip or board.

Electronic equipment may include data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, mobile phones, driving recorders, navigators, sensors, cameras, servers, cloud servers, cameras, video cameras, projectors, watches, Headphones, mobile storage, wearables, vehicles, home appliances, and/or medical equipment.

Vehicles may include aircraft, ships and/or vehicles. Household appliances may include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods. Medical equipment may include MRI machines, ultrasound machines and/or electrocardiographs.

FIG. 6 shows a flowchart of a method for processing a vector search instruction according to an embodiment of the present disclosure. As shown in FIG. 6, the method is applied to the above-mentioned vector search instruction processing apparatus, and the method includes step S51 and step S52.

In step S51, parse the received vector search instruction, obtain the operation code and operation field of the vector search instruction, and determine the vector to be searched, search conditions and target address required to execute the vector search instruction according to the operation code and operation field . The operation code is used to indicate that the operation performed by the vector search instruction on the vector data is a search operation, and the operation domain includes the address of the vector to be searched and the target address.

In step S52, it is sequentially determined whether a plurality of to-be-searched numbers representing the to-be-searched vector satisfy the search condition, and the to-be-searched number satisfying the search condition is determined as the target number, and the storage address of the target number is stored in the target address as the search result.

In a possible implementation, the operation field may also include the input length. Wherein, determining the vector to be searched, the search condition and the target address required for executing the vector search instruction according to the operation code and the operation domain may include: obtaining the vector to be searched from the address of the vector to be searched according to the input length.

In a possible implementation manner, the operation field may further include the width of the number to be checked. The method may further include: determining a plurality of numbers to be searched from the vector to be searched according to the width of the number to be searched.

In a possible implementation manner, the operation domain may further include search conditions. Wherein, determining the vector to be searched, the search condition and the target address required for executing the vector search instruction according to the operation code and the operation domain may include: determining the search condition according to the operation domain.

In a possible implementation manner, determining the vector to be searched, the search condition and the target address required for executing the vector search instruction according to the operation code and the operation domain may include:

According to the opcode, the search condition is determined, and the opcode is also used to indicate the search condition of the vector search instruction.

In a possible implementation manner, determining sequentially whether multiple numbers to be searched representing the vector to be searched satisfy the search condition may include:

At least one comparator is used to compare a plurality of numbers to be checked with a search condition to obtain a comparison result, so as to determine whether the number to be checked satisfies the search condition according to the comparison result.

In a possible implementation manner, the number to be checked that satisfies the search condition may include at least one of the following:

The value is the specified multiple of the specified value, and the order is the number to be checked in the specified order;

The number to be checked whose value is in the specified value range;

Numeric is the number to look up in the specified multiple of the specified value.

The specified ordering may include at least one of the following: the ordering of the numbers to be checked is the nth number of the numbers to be checked whose numerical value is a specified multiple of the specified value, where n is a positive integer greater than or equal to 1; the ordering of the numbers to be checked is The value is the m-th penultimate of the number to be checked that is a specified multiple of the specified value, where m is a positive integer greater than or equal to 1. Among them, m and n are less than or equal to the number of numbers to be searched in the vector to be searched.

In a possible implementation manner, the method may further include: storing the vector to be searched for.

In a possible implementation manner, the received vector search instruction is parsed to obtain the operation code and operation domain of the vector search instruction, which may include:

Store vector lookup instructions;

Analyze the vector search instruction to obtain the opcode and operation domain of the vector search instruction;

An instruction queue is stored, and the instruction queue includes multiple instructions to be executed sequentially arranged in an execution order, and the multiple instructions to be executed may include vector search instructions.

In a possible implementation, the method may further include:

When it is determined that the first to-be-executed instruction in the plurality of to-be-executed instructions has an associated relationship with the zeroth to-be-executed instruction before the first to-be-executed instruction, the first to-be-executed instruction is cached, and after it is determined that the zeroth to-be-executed instruction is executed , control the execution of the first instruction to be executed,

Wherein, the relationship between the first instruction to be executed and the zeroth instruction to be executed before the first instruction to be executed includes:

The first storage address interval storing the data required by the first instruction to be executed and the zeroth storage address interval storing the data required by the zeroth instruction to be executed have an overlapping area.

It should be noted that although the above embodiments are used as examples to introduce the vector search instruction processing method as above, those skilled in the art can understand that the present disclosure should not be limited thereto. In fact, the user can flexibly set each step according to personal preference and/or actual application scenarios, as long as it conforms to the technical solutions of the present disclosure.

The vector search instruction processing method provided by the embodiment of the present disclosure has a wide range of applications, and has high processing efficiency and high processing speed for the vector search instruction.

It should be noted that, for the sake of simple description, the foregoing method embodiments are all expressed as a series of action combinations, but those skilled in the art should know that the present application is not limited by the described action sequence. Because in accordance with the present application, certain steps may be performed in other orders or concurrently. Secondly, those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present disclosure.

In the above-mentioned embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

In the embodiments provided in the present disclosure, it should be understood that the disclosed systems and devices may be implemented in other manners. For example, the above-described system and device embodiments are only illustrative, for example, the division of devices, devices, and modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules may be combined. Or it may be integrated into another system or device, or some features may be omitted, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices, devices or modules, which may be in electrical or other forms.

Modules described as separate components may or may not be physically separated, and components shown as modules may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional module in each embodiment of the present disclosure may be integrated into one processing unit, or each module may exist physically alone, or two or more modules may be integrated into one module. The above-mentioned integrated modules can be implemented in the form of hardware, or can be implemented in the form of software program modules.

The integrated modules, if implemented in the form of software program modules and sold or used as stand-alone products, may be stored in a computer-readable memory. Based on such understanding, the technical solutions of the present disclosure essentially or the parts that contribute to the prior art or all or part of the technical solutions can be embodied in the form of software products, and the computer software products are stored in a memory, Several instructions are included to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present disclosure. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable memory, and the memory can include: a flash disk , Read-only memory (English: Read-Only Memory, referred to as: ROM), random access device (English: Random Access Memory, referred to as: RAM), magnetic disk or optical disk, etc.

The embodiments of the present application have been introduced in detail above, and the principles and implementations of the present application are described in this paper by using specific examples. The descriptions of the above embodiments are only used to help understand the methods and core ideas of the present application; at the same time, for Persons of ordinary skill in the art, based on the idea of the present application, will have changes in the specific implementation manner and application scope. In summary, the contents of this specification should not be construed as limitations on the present application.

Claims (21)

1. A vector search instruction processing device, wherein the device comprises: The control module is configured to parse the received vector search instruction, obtain the operation code and operation field of the vector search instruction, and determine the waiting period required to execute the vector search instruction according to the operation code and the operation field. lookup vector, lookup condition and target address; an arithmetic module, configured to sequentially determine whether a plurality of to-be-checked numbers representing the to-be-searched vector satisfy the search condition, determine the to-be-checked number that satisfies the search condition as a target number, and determine the storage address of the target number into the target address as the search result, The operation code is used to indicate that the operation performed by the vector search instruction on the vector data is a search operation, and the operation field includes the address of the vector to be searched and the target address. 2. The apparatus according to claim 1, wherein the operation field further comprises an input length, The control module is further configured to obtain the vector to be searched from the address of the vector to be searched according to the input length. 3. The device according to claim 1, wherein the operation field further comprises the width of the number to be checked, The operation module is further configured to determine the plurality of numbers to be checked from the vector to be searched according to the width of the number to be checked. 4. The apparatus according to claim 1, wherein the operation field further comprises a search condition, The control module is further configured to determine the search condition according to the operation domain. 5. The device of claim 1, wherein The control module is further configured to determine the search condition according to the operation code, wherein the operation code is further used to indicate the search condition of the vector search instruction. 6. The device according to claim 1, wherein the operation module comprises: at least one comparator, configured to compare the plurality of numbers to be checked with the search condition to obtain a comparison result, so as to determine whether the number to be checked satisfies the search condition according to the comparison result. 7. The device according to any one of claims 1-6, wherein the number to be checked that satisfies the search condition comprises at least one of the following: The value is the specified multiple of the specified value, and the order is the number to be checked in the specified order; The number to be checked whose value is in the specified value range; The value is the number to be checked in the specified multiple of the specified value, Wherein, the specified ordering includes at least one of the following: The order of the number to be checked is the nth number in the number to be checked whose numerical value is a specified multiple of the specified value, and the n is a positive integer greater than or equal to 1; The order of the number to be searched is the m-th penultimate in the number to be searched whose numerical value is a specified multiple of the specified value, and the m is a positive integer greater than or equal to 1, Wherein, m and n are less than or equal to the number of numbers to be searched in the vector to be searched. 8. The device of claim 1, wherein The device further includes: a storage module for storing the to-be-searched vector, Wherein, the control module includes: an instruction storage submodule for storing the vector search instruction; an instruction processing submodule, configured to parse the vector search instruction to obtain an opcode and an operation domain of the vector search instruction; a queue storage sub-module, used for storing an instruction queue, the instruction queue includes a plurality of instructions to be executed sequentially arranged in an execution order, and the multiple instructions to be executed include the vector search instruction, Wherein, the control module also includes: The dependency relationship processing submodule is configured to, when it is determined that the first to-be-executed instruction in the plurality of to-be-executed instructions has an associated relationship with the zeroth to-be-executed instruction before the first to-be-executed instruction, to process the first to-be-executed instruction The execution instruction is cached in the instruction storage sub-module, and after the execution of the zeroth instruction to be executed is completed, the first instruction to be executed is extracted from the instruction storage sub-module and sent to the operation module, Wherein, the relationship between the first instruction to be executed and the zeroth instruction to be executed before the first instruction to be executed includes: The first storage address interval storing the data required by the first instruction to be executed and the zeroth storage address interval storing the data required by the zeroth instruction to be executed have an overlapping area. 9. A machine learning computing device, wherein the device comprises: One or more vector search instruction processing devices as described in any one of claims 1-8, for obtaining the data to be calculated and control information from other processing devices, and executing the specified machine learning operation, the execution result is passed through I The /O interface is passed to other processing devices; When the machine learning computing device includes a plurality of the vector search instruction processing devices, the plurality of the vector search instruction processing devices can be connected through a specific structure and data can be transmitted; Wherein, a plurality of the vector search instruction processing devices are interconnected and transmit data through the fast peripheral device interconnection bus PCIE bus to support larger-scale machine learning operations; a plurality of the vector search instruction processing devices share the same control system Or have their own control systems; a plurality of the vector search instruction processing devices share memory or have their own memory; the interconnection mode of the multiple vector search instruction processing devices is any interconnection topology. 10. A combined processing device, characterized in that the combined processing device comprises: The machine learning computing device, universal interconnection interface and other processing devices as claimed in claim 9; The machine learning computing device interacts with the other processing devices to jointly complete the computing operation specified by the user, Wherein, the combined processing device further includes: a storage device, the storage device is respectively connected to the machine learning computing device and the other processing device, and is used for saving the data of the machine learning computing device and the other processing device. 11. A machine learning chip, wherein the machine learning chip comprises: The machine learning computing device as claimed in claim 9 or the combined processing device as claimed in claim 10 . 12. An electronic device, characterized in that the electronic device comprises: The machine learning chip of claim 11 . 13. A board, characterized in that the board comprises: a storage device, an interface device, a control device, and a machine learning chip as claimed in claim 11; Wherein, the machine learning chip is connected to the storage device, the control device and the interface device respectively; the storage device for storing data; The interface device is used to realize data transmission between the machine learning chip and an external device; The control device is used for monitoring the state of the machine learning chip. 14. A vector search instruction processing method, wherein the method is applied to a vector search instruction processing device, and the method comprises: Analyze the received vector search instruction, obtain the operation code and operation field of the vector search instruction, and determine the vector to be searched and search conditions required to execute the vector search instruction according to the operation code and the operation field and destination address; Determine in turn whether a plurality of to-be-checked numbers representing the to-be-searched vector satisfy the search condition, determine the to-be-checked number that satisfies the search condition as the target number, and store the storage address of the target number as the search result in the the target address, The operation code is used to indicate that the operation performed by the vector search instruction on the vector data is a search operation, and the operation field includes the address of the vector to be searched and the target address. 15. The method of claim 14, wherein the operation field further comprises an input length, Wherein, determining the vector to be searched, the search condition and the target address required to execute the vector search instruction according to the operation code and the operation domain, including: According to the input length, the to-be-searched vector is acquired from the to-be-searched vector address. 16. The method according to claim 14, wherein the operation field further comprises the width of the number to be checked, and the method further comprises: According to the width of the number to be looked up, the plurality of numbers to be looked up are determined from the vector to be looked up. 17. The method according to claim 14, wherein the operation field further comprises a search condition, Wherein, determining the vector to be searched, the search condition and the target address required to execute the vector search instruction according to the operation code and the operation domain, including: According to the operation domain, the search condition is determined. 18. The method according to claim 14, wherein determining the vector to be searched, the search condition and the target address required for executing the vector search instruction according to the operation code and the operation domain, comprising: The search condition is determined according to the operation code, and the operation code is further used to indicate the search condition of the vector search instruction. 19. The method according to claim 14, wherein determining sequentially whether multiple numbers to be searched representing the vector to be searched satisfy the search condition, comprising: At least one comparator is used to compare the plurality of numbers to be checked with the search condition to obtain a comparison result, so as to determine whether the number to be checked satisfies the search condition according to the comparison result. 20. The method according to any one of claims 14-19, wherein the number to be checked that satisfies the search condition comprises at least one of the following: The value is the specified multiple of the specified value, and the order is the number to be checked in the specified order; The number to be checked whose value is in the specified value range; The value is the number to be checked in the specified multiple of the specified value, Wherein, the specified ordering includes at least one of the following: The order of the number to be checked is the nth number in the number to be checked whose numerical value is a specified multiple of the specified value, and the n is a positive integer greater than or equal to 1; The order of the number to be searched is the m-th penultimate in the number to be searched whose numerical value is a specified multiple of the specified value, and the m is a positive integer greater than or equal to 1, Wherein, m and n are less than or equal to the number of numbers to be searched in the vector to be searched. 21. The method of claim 14, wherein The method further includes: storing the to-be-searched vector, Wherein, the received vector search instruction is parsed to obtain the operation code and operation domain of the vector search instruction, including: storing the vector lookup instruction; Parsing the vector search instruction to obtain an opcode and an operation domain of the vector search instruction; an instruction queue is stored, the instruction queue includes a plurality of instructions to be executed sequentially arranged in an execution order, and the multiple instructions to be executed include the vector search instruction, Wherein, the method also includes: When it is determined that the first to-be-executed instruction in the plurality of to-be-executed instructions has an associated relationship with the zeroth to-be-executed instruction before the first to-be-executed instruction, the first to-be-executed instruction is cached, and the first to-be-executed instruction is determined when the After the execution of the zeroth instruction to be executed is completed, the execution of the first instruction to be executed is controlled to be executed, Wherein, the relationship between the first instruction to be executed and the zeroth instruction to be executed before the first instruction to be executed includes: The first storage address interval storing the data required by the first instruction to be executed and the zeroth storage address interval storing the data required by the zeroth instruction to be executed have an overlapping area.

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