CN111355549B - Data protection method and device - Google Patents

Abstract

This paper discloses a data protection method and device. The data protection method includes: the source-end single board adds a time stamp to the original data packet, and sends the time-stamped data packet to the sink-end single board in parallel through two channels; data packet, determine the data packet written into the buffer queue of each channel according to the time stamp carried by the data packet, and write the data packet into the buffer queue of each channel respectively; The data packets are read in parallel in the buffer queue, and the data packets read by the two channels are aligned according to the timestamps carried by the data packets; The data packets read in the buffer queue of any channel are output. The technical solution in this paper can improve the transmission reliability of data packets.

Description

A data protection method and device

technical field

The present invention relates to the technical field of optical transmission network, in particular to a data protection method and device.

Background technique

The lower backplane switching of OTN (Optical Transport Network, Optical Transport Network) can integrate OTN and packet switching on the same platform, which can provide operators with maximum flexibility in network design and cost optimization. Switch access) interface to complete TDM (Time Division Multiplexing, time division multiplexing) packet switching.

The packet exchange under the connection of NP (Network Processor, network processor) is realized through the exchange of Ethernet packets, and the interface can only be realized by the Interlaken interface. POTN (Packet Optical Transport Network, Packet Optical Transport Network) technology is a technology based on OTN technology with packet switching and transmission capabilities. It mainly combines PTN (Packet Transport Network, Packet Transport Network) with OTN, packet, TDM All advantages such as , packet switching, etc. are concentrated in the same device to realize multi-granule switching and achieve perfect integration of multiple technologies. The cross-connect board needs to use the Interlaken interface to realize cross-connection.

However, in the 5G fronthaul network, higher requirements are put forward for the switching and transmission delay performance of TDM packets and the reliability of transmitted data.

Contents of the invention

The technical problem to be solved by the present invention is to provide a data protection method and device, which can improve the reliability of data transmission.

According to the first aspect of the present application, an embodiment of the present invention provides a data protection method, including:

The source board adds a timestamp to the original data packet, and sends the time-stamped data packet to the sink board in parallel through two channels;

The sink board receives data packets in two channels in parallel, determines the data packets to be written into the buffer queue of each channel according to the timestamp carried by the data packets, and writes the data packets into the buffer queue of each channel respectively ;

The sink board reads data packets in parallel from the buffer queues of the two channels, and performs alignment processing on the data packets read by the two channels according to the timestamps carried by the data packets;

After the read cache operations of the two channels are successfully aligned, the sink board outputs the data packets read from the cache queue of any channel.

According to the second aspect of the present application, an embodiment of the present invention provides a data protection device, including:

The source-end single-board processing module is used to add a time stamp to the original data packet, and send the time-stamped data packet to the sink-end single board in parallel through two channels;

The sink-end single-board processing module is configured to receive data packets in two channels in parallel, determine the data packets written into the buffer queue of each channel according to the timestamp carried by the data packets, and write the data packets into each In the buffer queue of the channel, data packets are read in parallel from the buffer queues of the two channels, and the data packets read by the two channels are aligned according to the timestamps carried by the data packets. After the operation is aligned successfully, the data packets read from the buffer queue of any channel are output.

Compared with related technologies, in the data protection method and device provided by the embodiment of the present invention, the single board at the source end adds a time stamp to the original data packet, and sends the time-stamped data packet to the sink end in parallel through two channels single board; the sink-end single board receives data packets in two channels in parallel, determines the data packets written into the cache queue of each channel according to the timestamp carried by the data packets, and writes the data packets into the buffer queue of each channel respectively In the cache queue, data packets are read in parallel from the cache queues of the two channels, and the data packets read by the two channels are aligned according to the timestamps carried by the data packets, and the read cache operation of the two channels is aligned After success, output the data packets read from the buffer queue of any channel. The technical solutions of the embodiments of the present invention can improve the reliability of data transmission.

Description of drawings

FIG. 1 is a flowchart of a data protection method according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a time stamp carried in a TDM packet according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a data protection device according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a data protection device in Example 1 of the present invention.

Detailed ways

In order to make the purpose, technical solution and advantages of the present invention more clear, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

Example 1

As shown in Figure 1, an embodiment of the present invention provides a data protection method, including:

Step S110, the source board adds a timestamp to the original data packet, and sends the time-stamped data packet to the sink board in parallel through two channels;

In step S120, the sink board receives data packets in two channels in parallel, determines the data packets to be written into the cache queue of each channel according to the timestamp carried by the data packets, and writes the data packets into the buffer queue of each channel respectively. in the buffer queue;

Step S130, the sink board reads data packets in parallel from the buffer queues of the two channels, and performs alignment processing on the data packets read by the two channels according to the timestamps carried by the data packets;

Step S140, after the read buffer operation of the two channels is successfully aligned, the sink board outputs the data packets read from the buffer queue of any channel;

In the foregoing implementation manners, the source board provides a reference basis for data alignment for parallel reception of the sink board by adding a time stamp to the original data packet. The sink board receives data packets in two channels in parallel, and controls operations of the write cache and the read cache according to the time stamps carried in the data packets. When reading the cache, it can be judged whether the data packets read by the two channels are aligned by checking whether the time stamps carried by the data packets read by the two channels are the same. When the read operations of the two channels are aligned, any one channel can be used as the current working channel, and the other channel can be used as the standby channel. When the working channel fails, since the data read by the two channels is consistent, seamless switching between the working channel and the backup channel can be achieved, thereby meeting the stringent requirements of the 5G fronthaul network for communication delay and reliability.

In one embodiment, the data packet includes: a time division multiplexed TDM data packet;

In one embodiment, adding a time stamp to the original data packet includes: adding a time stamp to the header of the TDM data packet;

Wherein, as shown in Figure 2, the TDM data packet includes: header and load; Wherein, header includes 16-bit timestamp and 16-bit OH (Overhead, overhead);

In one embodiment, the two channels are Interlaken channels; wherein, Interlaken is a high-speed channelized interface protocol;

In one embodiment, the determining the data packet written into the buffer queue of each channel according to the timestamp carried by the data packet and writing the data packet into the buffer queue of each channel respectively includes:

For each channel, when the time stamp of the data packet received by the channel changes from the maximum value to the minimum value, the time when the data packet carrying the time stamp of the minimum value is received is taken as the reference time, and at the reference time All previously received data packets are written into the buffer queue of the channel;

In one embodiment, the alignment processing of the data packets read by the two channels according to the timestamps carried by the data packets includes:

When the number of data packets allowed to be read in the buffer queues of the two channels reaches or exceeds the read threshold, the buffer queues of the two channels are read at the same time. When the first n data packets read from the buffer queues of the two channels When the timestamps carried by the data packets are the same, it is determined that the data packets read by the two channels are aligned;

Wherein, n can take a value of 1, or 2 or 3 or other values;

In one embodiment, the alignment processing of the data packets read by the two channels according to the timestamps carried by the data packets further includes:

Determines read caching operations for both channels when the number of read-allowed packets in one channel's cache queue meets or exceeds the read threshold, while the other channel's cache queue has zero allowed-read packets The alignment condition is not met;

In one embodiment, the determining the data packet written into the buffer queue of each channel according to the timestamp carried by the data packet and writing the data packet into the buffer queue of each channel respectively includes:

Query the alarm information of each channel;

For any channel, when the alarm information of the channel is not queried, trigger the write cache processing of the channel;

In one embodiment, after querying the alarm information of each channel, the method further includes:

After querying the alarm information of any channel, processing the alarm information;

The alarm information includes at least one of the following: Interlaken channel misalignment, de-skew failure, CRC (Cyclic Redundancy Check, cyclic redundancy check) check error, packet header and packet tail mismatch error, and meta frame length error;

In one embodiment, the method also includes:

After the sink board outputs the data packets read from the buffer queue of the first channel, if an alarm occurs in the first channel, output the data packets read from the buffer queue of the second channel;

In one embodiment, the method also includes:

After the alarm of the first channel is recovered, the write operation to the buffer queue of the first channel is retriggered, and the read cache operation of the first channel and the second channel are re-aligned.

In one embodiment, the buffer queue of each channel is a FIFO (First Input First Output, First In First Out) queue.

Example 2

As shown in Figure 2, an embodiment of the present invention provides a data protection device, including:

The source-end single-board processing module 10 is configured to add a time stamp to the original data packet, and send the time-stamped data packet to the sink-end single board in parallel through two channels;

The sink-end single-board processing module 20 is configured to receive data packets in two channels in parallel, determine the data packets written into the cache queue of each channel according to the timestamp carried by the data packets, and write the data packets into each channel respectively. In the cache queue of one channel, data packets are read in parallel from the cache queues of two channels, and the data packets read by the two channels are aligned according to the timestamps carried by the data packets. After the cache operation is aligned successfully, the data packets read from the cache queue of any channel are output.

In one embodiment, the data packet includes: a time division multiplexed TDM data packet;

In one embodiment, the source-end single-board processing module is configured to add a time stamp to the original data packet in the following manner: add a time stamp to the header of the TDM data packet;

In one embodiment, the two passages are Interlaken passages;

In one embodiment, the sink-end single-board processing module is configured to determine the data packets written into the cache queue of each channel according to the timestamp carried by the data packets in the following manner and write the data packets respectively into the buffer queue of each channel: for each channel, when the time stamp of the data packet received by the channel changes from the maximum value to the minimum value, the time when the data packet carrying the minimum value time stamp is received is taken as At a reference time, write all data packets received before the reference time into the buffer queue of the channel;

In one embodiment, the sink-end single-board processing module is configured to perform alignment processing on the data packets read by the two channels according to the timestamps carried by the data packets in the following manner: when the buffer queues of the two channels When the number of data packets allowed to be read in all reaches or exceeds the read threshold, the buffer queues of the two channels are read at the same time. When the timestamps carried by the first n data packets read from the buffer queues of the two channels are the same At the same time, determine the alignment of the data packets read by the two channels;

Wherein, n can take the value of 1 or 2 or 3 or other values;

In one embodiment, the sink-end single-board processing module is further configured to perform alignment processing on the data packets read by two channels according to the timestamps carried by the data packets in the following manner: when the buffer queue of one channel When the number of data packets allowed to be read in reaches or exceeds the read threshold, and the number of data packets allowed to be read in the cache queue of another channel is zero, it is determined that the read cache operations of the two channels do not meet the alignment condition;

In one embodiment, the sink-end single-board processing module is configured to determine the data packets written into the cache queue of each channel according to the timestamp carried by the data packets in the following manner and write the data packets respectively Enter the cache queue of each channel: query the alarm information of each channel; for any channel, when the alarm information of the channel is not queried, trigger the write cache processing of the channel;

In one embodiment, the sink-side single-board processing module is further configured to process the alarm information after querying the alarm information of each channel, if the alarm information of any channel is inquired;

The alarm information includes at least one of the following: Interlaken channel misalignment, de-skew failure, CRC (Cyclic Redundancy Check, cyclic redundancy check) check error, packet header and packet tail mismatch error, and meta frame length error;

In one embodiment, the sink-side single-board processing module is further configured to output the data packets read from the buffer queue of the first channel, and if an alarm occurs on the first channel, output the data packets from the first channel The data packets read in the buffer queue of the second channel are output;

In one embodiment, the sink-side single-board processing module is further configured to re-trigger the write operation to the buffer queue of the first channel after the alarm of the first channel recovers, and Re-align with the read cache operation of the second channel.

Example 1

As shown in Figure 4, this example provides a data protection device, including: a source board and a sink board; the source board includes: a TDM packet processing module, a first channel sending module, and a second channel A sending module; the sink board includes: a first channel receiving module, a second channel receiving module, a first alarm processing module, a second alarm processing module, a FIFO read and write control module, a first FIFO module, and a second FIFO module , and the package output module;

The TDM packet processing module is used to add a time stamp to the original TDM data packet, and distribute the time stamped TDM data packet to the first channel sending module and the second channel sending module in parallel;

The first channel sending module is configured to send the time stamped TDM data packet to the sink board through the first Interlaken channel;

The second channel sending module is configured to send the TDM data packet with the time stamp added to the sink end single board through the second Interlaken channel;

The first channel receiving module is used to receive the TDM packet through the first Interlaken channel, and notify the first alarm processing module to inquire whether there is alarm information in the first Interlaken channel;

The first alarm processing module is used to process the alarm information after inquiring about the alarm information of the first Interlaken channel, and notify the FIFO read and write control module; when not inquiring about the alarm information of the first Interlaken channel, notify The first Interlaken channel interface of the FIFO read-write control module is normal;

The second channel receiving module is used to receive the TDM packet through the second Interlaken channel, and notifies the second alarm processing module to inquire whether there is alarm information in the second Interlaken channel;

The second alarm processing module is used to process the alarm information after inquiring about the alarm information of the second Interlaken channel, and notify the FIFO read and write control module; when not inquiring about the alarm information of the second Interlaken channel, notify The interface of the second Interlaken channel of the FIFO read-write control module is normal;

Wherein, the alarm information may include at least one of the following: Interlaken channel misalignment, de-skew failure, CRC (Cyclic Redundancy Check, cyclic redundancy check) check error, packet header and packet tail mismatch error, and metaframe wrong length;

The FIFO read and write control module is used to know that after the first Interlaken channel interface is normal, when the timestamp of the data packet received by the first Interlaken channel changes from a maximum value to a minimum value, it will receive and carry the minimum value timestamp The time of the data packet is used as a reference time to trigger the first FIFO module to write the buffer; and for knowing that the interface of the second Interlaken channel is normal, when the timestamp of the data packet received by the second Interlaken channel changes from the maximum to the minimum value, the moment of receiving the data packet carrying the minimum value timestamp is used as the reference moment to trigger the second FIFO module to write the cache;

The first FIFO module is used to write all data packets received before the reference time into the FIFO buffer queue of the first Interlaken channel;

The second FIFO module is used to write all data packets received before the reference time into the FIFO buffer queue of the second Interlaken channel;

The FIFO read-write control module is also used to inquire about the quantity of data packets allowed to be read in the FIFO cache queue of the first Interlaken channel, and inquire about the quantity of the data packets allowed to be read in the FIFO cache queue of the second Interlaken channel; when two When the number of data packets allowed to be read in the buffer queues of two Interlaken channels reaches or exceeds the read threshold, the first FIFO module and the second FIFO module are triggered to read the FIFO buffer queues simultaneously; When the time stamps carried by the first n data packets read in the queue are the same, notify the packet output module that the data packets are aligned; When the number of data packets allowed to be read in the cache queue of an Interlaken channel is 0, it is determined that the read cache operations of the two Interlaken channels do not meet the alignment conditions;

The packet output module is used to select the data packets read from the FIFO buffer queue of the first Interlaken channel to output after knowing that the data packets read by the FIFO buffer queues of the two Interlaken channels are aligned, or to select from the second Interlaken channel The data packets read in the FIFO buffer queue are output;

The FIFO read and write control module is also used to select the data packet read from the FIFO buffer queue of the first Interlaken channel for output, if it is learned that an alarm occurs in the first Interlaken channel, then select the FIFO buffer queue from the second Interlaken channel output the data packets read in; when the first Interlaken channel alarm is recovered, re-trigger the write buffer of the first FIFO module, and re-control the read buffer of the first FIFO module and the second FIFO module and perform data packet alignment processing.

In the above example, the source board provides a data alignment reference for parallel reception of the sink board by adding a time stamp to the original data packet. The sink board receives the data packets in parallel on the two Interlaken channels, and controls the operations of the write cache and the read cache according to the timestamps carried in the data packets. When reading the cache, it can be judged whether the data packets read by the two Interlaken channels are aligned by checking whether the time stamps carried by the data packets read by the two Interlaken channels are the same. When the read operations of two Interlaken channels are aligned, any one channel can be used as the current working channel, and the other channel can be used as the standby channel. When the working channel fails, since the data read by the two channels is consistent, seamless switching between the working channel and the backup channel can be achieved, thereby meeting the stringent requirements of the 5G fronthaul network for communication delay and reliability.

Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, the functional modules/units in the system, and the device can be implemented as software, firmware, hardware, and an appropriate combination thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be composed of several physical components. Components cooperate to execute. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit . Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). As known to those of ordinary skill in the art, the term computer storage media includes both volatile and nonvolatile media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data. permanent, removable and non-removable media. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, tape, magnetic disk storage or other magnetic storage devices, or can Any other medium used to store desired information and which can be accessed by a computer. In addition, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media .

It should be noted that the present invention can also have other various embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these Corresponding changes and deformations should belong to the scope of protection of the appended claims of the present invention.

Claims (8)

1. A data protection method comprising: The source board adds a timestamp to the original data packet, and sends the time-stamped data packet to the sink board in parallel through two channels; The sink board receives data packets in two channels in parallel, determines the data packets to be written into the buffer queue of each channel according to the timestamp carried by the data packets, and writes the data packets into the buffer queue of each channel respectively ; The sink board reads data packets in parallel from the buffer queues of the two channels, and performs alignment processing on the data packets read by the two channels according to the timestamps carried by the data packets; After the read cache operation of the two channels is successfully aligned, the sink board outputs the data packets read from the cache queue of any channel; Wherein, the alignment processing of the data packets read by the two channels according to the timestamps carried by the data packets includes: When the number of data packets allowed to be read in the buffer queues of the two channels reaches or exceeds the read threshold, the buffer queues of the two channels are read at the same time. When the first n data packets read from the buffer queues of the two channels When the timestamps carried by the data packets are the same, it is determined that the data packets read by the two channels are aligned. 2. The method of claim 1, wherein: The determining the data packets written into the buffer queue of each channel according to the timestamp carried by the data packets and writing the data packets into the buffer queue of each channel respectively includes: For each channel, when the time stamp of the data packet received by the channel changes from the maximum value to the minimum value, the time when the data packet carrying the time stamp of the minimum value is received is taken as the reference time, and at the reference time All previously received packets are written to the channel's buffer queue. 3. The method of claim 1, wherein: The alignment processing of the data packets read by the two channels according to the timestamps carried by the data packets also includes: Determines read caching operations for both channels when the number of read-allowed packets in one channel's cache queue meets or exceeds the read threshold, while the other channel's cache queue has zero allowed-read packets Alignment condition not met. 4. The method of claim 1, wherein: The determining the data packets written into the buffer queue of each channel according to the timestamp carried by the data packets and writing the data packets into the buffer queue of each channel respectively includes: Query the alarm information of each channel; For any channel, when the alarm information of the channel is not queried, the write cache processing of the channel is triggered. 5. The method of claim 1, further comprising: After the sink board outputs the data packets read from the buffer queue of the first channel, if an alarm occurs in the first channel, output the data packets read from the buffer queue of the second channel; After the alarm of the first channel is recovered, the write operation to the buffer queue of the first channel is retriggered, and the read cache operation of the first channel and the second channel are re-aligned. 6. The method according to any one of claims 1-5, characterized in that: The two passages are Interlaken passages; The data packets are time-division multiplexed TDM data packets. 7. A data protection device comprising: The source-end single-board processing module is used to add a time stamp to the original data packet, and send the time-stamped data packet to the sink-end single board in parallel through two channels; The sink-end single-board processing module is configured to receive data packets in two channels in parallel, determine the data packets written into the buffer queue of each channel according to the timestamp carried by the data packets, and write the data packets into each In the buffer queue of the channel, data packets are read in parallel from the buffer queues of the two channels, and the data packets read by the two channels are aligned according to the timestamps carried by the data packets. After the operation alignment is successful, output the data packets read from the buffer queue of any channel; Wherein, the sink-end single-board processing module is configured to perform alignment processing on the data packets read by the two channels according to the timestamps carried by the data packets in the following manner: when the buffer queues of the two channels allow reading When the number of data packets reaches or exceeds the read threshold, the cache queues of the two channels are read at the same time. When the timestamps carried by the first n data packets read from the cache queues of the two channels are the same, two Packet alignment for channel reads. 8. The device of claim 7, wherein: The sink-side single-board processing module is configured to determine, according to the timestamp carried by the data packets, the data packets written into the buffer queue of each channel in the following manner and write the data packets into the buffer queue of each channel respectively Middle: For each channel, when the time stamp of the data packet received by the channel changes from the maximum value to the minimum value, the time when the data packet carrying the minimum value time stamp is received is taken as the reference time, and the All packets received before the reference time are written into the channel's buffer queue.

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