CN111224645A - DC-DC conversion circuit and time signal generator thereof - Google Patents
DC-DC conversion circuit and time signal generator thereof Download PDFInfo
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- H—ELECTRICITY
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- H03K7/08—Duration or width modulation ; Duty cycle modulation
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
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Abstract
本发明公开了一种直流‑直流转换电路及其时间信号产生器。时间信号产生器产生时间信号以使直流对直流转换电路将输入电压转换为输出电压。直流对直流转换电路耦接负载并有负载电流流经负载。时间信号产生器包括模拟数字转换单元、补偿单元、计数单元、比较单元及逻辑单元。模拟数字转换单元分别接收输出电压、输入电压及负载电流并分别转换为相对应的数字信号。补偿单元分别接收该些数字信号并进行运算处理，以产生补偿信号。计数单元依据时钟信号与触发信号来提供计数信号。比较单元接收补偿信号与计数信号以提供比较信号。逻辑单元接收触发信号与比较信号以提供时间信号。本发明可有效提升直流对直流转换电路运作于重载稳态时的电源转换效率。
The present invention discloses a DC-DC conversion circuit and a time signal generator thereof. The time signal generator generates a time signal so that the DC-DC conversion circuit converts an input voltage into an output voltage. The DC-DC conversion circuit is coupled to a load and a load current flows through the load. The time signal generator includes an analog-to-digital conversion unit, a compensation unit, a counting unit, a comparison unit and a logic unit. The analog-to-digital conversion unit receives the output voltage, the input voltage and the load current respectively and converts them into corresponding digital signals respectively. The compensation unit receives the digital signals respectively and performs calculation processing to generate a compensation signal. The counting unit provides a counting signal based on a clock signal and a trigger signal. The comparison unit receives the compensation signal and the counting signal to provide a comparison signal. The logic unit receives the trigger signal and the comparison signal to provide a time signal. The present invention can effectively improve the power conversion efficiency of the DC-DC conversion circuit when it operates in a heavy-load steady state.
Description
Technical Field
The present invention relates to a dc-dc conversion circuit, and more particularly, to a dc-dc conversion circuit and a time signal generator thereof.
Background
When the dc-dc converter circuit with constant on-time is operated in a heavy-load steady state, since its on-time is constant, the time interval of the time signal provided by the dc-dc converter circuit is shortened (as shown in fig. 1A, the off-on time interval is shortened from TOFF1 to TOFF 2), the switching period is shortened, and the average value of the inductor current passing through the output inductor is increased (as shown in fig. 1B, the inductor current is changed from Iind1 to Iind 2), in order to offset the power conversion loss caused by the parasitic resistance of the elements in the circuit.
However, the short period of the time signal means that the switching frequency of the output stage of the dc-dc converter circuit increases, which results in the power conversion efficiency of the dc-dc converter circuit being deteriorated when the dc-dc converter circuit operates in a heavy load steady state.
Disclosure of Invention
The invention provides a direct current-direct current conversion circuit and a time signal generator thereof, which are used for solving the problems in the prior art.
A preferred embodiment of the present invention is a time signal generator. In this embodiment, the time signal generator generates the time signal to make the dc-dc conversion circuit convert the input voltage into the output voltage. The DC-DC conversion circuit is coupled to the load and has a load current flowing through the load. The time signal generator comprises an analog-digital conversion unit, a compensation unit, a counting unit, a comparison unit and a logic unit. The analog-digital conversion unit respectively receives the output voltage, the input voltage and the load current and respectively converts the output voltage, the input voltage and the load current into a digital input voltage signal, a digital output voltage signal and a digital load current signal. The compensation unit receives the digital output voltage signal, the digital input voltage signal and the digital load current signal respectively, and performs operation processing on the digital output voltage signal, the digital input voltage signal and the digital load current signal to generate a compensation signal. The counting unit provides a counting signal according to the clock signal and the trigger signal. The comparison unit receives the compensation signal and the counting signal to provide a comparison signal. The logic unit receives the trigger signal and the comparison signal to provide the time signal.
In an embodiment of the present invention, the time signal is related to the digital input voltage signal, the digital output voltage signal and the digital load current signal.
In an embodiment of the present invention, during a heavy load, the load current flowing through the load increases, so that the digital load current signal related to the load current increases. The compensation signal generated by the compensation unit and the comparison signal provided by the comparison unit are increased accordingly.
In an embodiment of the present invention, the compensation unit includes a first multiplier, a second multiplier, an adder, and a divider. The first multiplier is used for multiplying the digital load current signal by a first constant to obtain a first product. The second multiplier is used for multiplying the digital input voltage signal by a second constant to obtain a second product. The adder is coupled to the first multiplier for adding the first product to the digital output voltage signal to obtain a sum. The divider is coupled to the adder and the second multiplier for dividing the sum by the second product to obtain the compensation signal.
In an embodiment of the invention, the time signal also increases with the sum value, and an increase of the time signal is related to an increase of the digital load current signal.
In an embodiment of the present invention, the compensation unit includes a first multiplier, a second multiplier, a first divider, a second divider, and an adder. The first multiplier is used for multiplying the digital load current signal by a first constant to obtain a first product. The second multiplier is used for multiplying the digital input voltage signal by a second constant to obtain a second product. The first divider is coupled to the first multiplier and the second multiplier for dividing the load current signal by the second product to obtain a first quotient. The second divider is coupled to the second multiplier for dividing the digital output voltage by the second product to obtain a second quotient. The adder is coupled to the first divider and the second divider for adding the first quotient and the second quotient to obtain the compensation signal.
Another preferred embodiment of the present invention is a dc-dc converter circuit. In this embodiment, the dc-dc conversion circuit converts the input voltage into the output voltage. The DC-DC conversion circuit is coupled to the load and has a load current flowing through the load. The DC-DC conversion circuit includes an output stage, a driving circuit, a feedback circuit and a time signal generator. The output stage is coupled to the load and receives at least one driving signal to convert the input voltage into an output voltage. The driving circuit is coupled to the output stage and generates at least one driving signal according to the time signal. The feedback circuit is coupled to the output stage and generates a trigger signal according to the output voltage. The time signal generator is coupled between the feedback circuit and the driving circuit, and receives the input voltage, the output voltage, the load current and the trigger signal to generate a time signal. The time signal generator comprises a compensation unit which respectively receives a digital output voltage signal related to the output voltage, a digital input voltage signal related to the input voltage and a digital load current signal related to the load current, and carries out operation processing on the digital output voltage signal, the digital input voltage signal and the digital load current signal to generate a compensation signal and provide a time signal according to the compensation signal.
In an embodiment of the invention, the time signal generator further includes an analog-to-digital conversion unit coupled to the compensation unit, and respectively receiving the output voltage, the input voltage and the load current, and respectively converting the output voltage, the input voltage and the load current into a digital output voltage signal, a digital input voltage signal and a digital load current signal.
In one embodiment of the present invention, the time signal is related to the digital input voltage signal, the digital output voltage signal and the digital load current signal.
In an embodiment of the invention, during the heavy load period, the load current flowing through the load increases, so that the digital load current signal related to the load current increases, and the compensation signal generated by the compensation unit also increases accordingly.
Compared with the prior art, the direct current-direct current conversion circuit and the time signal generator thereof can adjust the time signal provided by the direct current-direct current conversion circuit through the compensation signal related to the load current, so that when the direct current-direct current conversion circuit operates in a heavy load steady state to increase the load current, the conduction time of the time signal provided by the time signal generator time signal is increased, and the switching frequency of the direct current-direct current conversion circuit is kept constant to improve the power conversion efficiency of the direct current-direct current conversion circuit when the direct current-direct current conversion circuit operates in the heavy load steady state.
The advantages and spirit of the present invention can be further understood by the following detailed description of the invention and the accompanying drawings.
Drawings
Fig. 1A is a schematic diagram illustrating that the off time and the period of the pwm signal provided by the conventional dc-dc conversion circuit are shortened under a heavy load steady state.
Fig. 1B is a schematic diagram illustrating that an average value of an inductor current of a conventional dc-dc conversion circuit becomes larger in a heavy-load steady state and a period thereof becomes shorter.
Fig. 2 is a schematic diagram of a time signal generator applied to a dc-dc conversion circuit according to a preferred embodiment of the invention.
FIG. 3 is a functional block diagram of the time signal generator in FIG. 2.
FIG. 4A is a diagram of an embodiment of a digital time signal generator.
FIG. 4B shows another embodiment of a digital time signal generator.
Fig. 5A and 5B are schematic diagrams of a conventional digital time signal generator and a time signal provided by the digital time signal generator of the present invention in a steady state under a light load, respectively.
Fig. 5C and 5D are schematic diagrams of the time signals provided by the conventional digital time signal generator and the digital time signal generator of the present invention under the heavy load steady state, respectively.
Description of the main element symbols:
ton1, Ton 2: time signal
Toff1, Toff 2: length of off time
Iind1, Iind 2: inductive current
2: DC-DC conversion circuit
1: time signal generator
10: analog-to-digital conversion unit
11: compensation unit
12: counting unit
14: comparison unit
16: logic unit
DR: driving circuit
And OS: output stage
LD: load(s)
FB: feedback circuit
CLK: clock signal
TR: trigger signal
GND: ground voltage
SVout: digital output voltage signal
Vout: output voltage
SVin: digital input voltage signal
Vin: input voltage
SIL: digital load current signal
IL: load current
S1: compensating signal
S2: counting signal
S3: comparing signals
Ton: time signal
DS 1: a first drive signal
DS 2: second drive signal
M1: first multiplier
M2: second multiplier
DIV: divider
DIV 1: first divider
DIV 2: second divider
ADD: adder
And (4) SUM: sum of all values
T1, T2, T1 ', T2': length of on-time
D1, D2, D1 ', D2': period of time signal
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. The same or similar numbered elements/components used in the drawings and the embodiments are used to represent the same or similar parts.
A preferred embodiment according to the present invention is a time signal generator. In this embodiment, the time signal generator is applied to the dc-dc conversion circuit for generating the time signal.
Referring to fig. 2, fig. 2 is a schematic diagram illustrating the application of the time signal generator in the embodiment to the dc-dc conversion circuit. As shown in FIG. 2, the DC-DC converting circuit 2 is coupled to the load LD and has a load current ILFlows through the load LD. During heavy load, the load current I through the load LDLIt will increase.
The dc-dc conversion circuit 2 includes a time signal generator 1, a driving circuit DR, an output stage OS and a feedback circuit FB. The time signal generator 1 is coupled to the driving circuit DR and the feedback circuit FB. The driving circuit DR is coupled to the time signal generator 1 and the output stage OS. The output stage OS is coupled to the input voltage Vin, the ground voltage GND, the driving circuit DR, the feedback circuit FB and the load LD, and generates an output voltage Vout. The feedback circuit FB is coupled to the output voltage Vout and the time signal generator 1.
The time signal generator 1 receives an input voltage Vin, an output voltage Vout, and a load current ILThe clock signal CLK and the trigger signal TR provide a time signal Ton to the driving circuit DR. The driving circuit DR generates a first driving signal DS1 and a second driving signal DS2 to the output stage OS according to the time signal Ton. The output stage OS is driven by the first driving signal DS1 and the second driving signal DS2 to generate the output voltage Vout. The feedback circuit FB generates a trigger signal TR to the time signal generator 1 according to the output voltage Vout.
In practical applications, the output stage OS includes a first switch and a second switch connected in series between the input voltage Vin and the ground voltage GND, and is driven by a first driving signal D1 and a second driving signal D2 respectively to output an inductor current Iind between the first switch and the second switch and generate the output voltage Vout.
Referring to fig. 3, fig. 3 is a functional block diagram of the time signal generator 1 in fig. 2. As shown in fig. 3, the time signal generator 1 includes an analog-to-digital conversion unit 10, a compensation unit 11, a counting unit 12, a comparison unit 14, and a logic unit 16. The analog-to-digital conversion unit 10 is coupled to the compensation unit 11. The compensation unit 11 and the counting unit 12 are coupled to the comparison unit 14. The comparison unit 14 is coupled to the logic unit 16.
The analog-to-digital conversion unit 10 receives an output voltage Vout, an input voltage Vin, and a load current ILAnd respectively converted into a digital output voltage signal SVout, a digital input voltage signal SVin and a digital load current signal SILAnd then supplied to the compensation unit 11.
The compensation unit 11 receives the digital output voltage signal SVout, the digital input voltage signal SVin and the digital load current signal SI respectivelyLAnd for the digital output voltage signal SVout, the digital input voltage signal SVin and the digital load current signal SILThe arithmetic processing is performed to generate a compensation signal S1. The counting unit 12 provides a counting signal S2 according to the clock signal CLK and the trigger signal TR.
The comparing unit 14 receives the compensation signal S1 from the compensating unit 11 and the count signal S2 from the counting unit 12, and provides a comparison signal S3 to the logic unit 16 according to the compensation signal S1 and the count signal S2. The logic unit 16 receives the trigger signal TR and the comparison signal S3, and provides a time signal Ton to the driving circuit DR according to the trigger signal TR and the comparison signal S3.
In practical applications, the time signal Ton provided by the logic unit 16 of the time signal generator 1, the digital input voltage signal SVin, the digital output voltage signal SVout and the digital load current signal SILHowever, the present invention is not limited thereto.
During light load, load current ILThe resulting compensation value is omitted and the time signal Ton provided by the logic unit 16 remains unchanged. During heavy load, the load current I through the load LDLIncrease so as to be in contact with the load current ILCorrelated digital load current signal SILIs increased and the compensation unit 11 is based on the digital load current signal SILThe generated compensation signal S1 and the comparison signal S3 provided by the comparison unit 14 according to the compensation signal S1 are also increased, so that the time signal Ton provided by the logic unit 16 is also increased along with the comparison signal S3 and the amount of the time signal Ton is increased by the digital load current signal SILThe amount of (2) is not limited to this.
Referring to fig. 4A, fig. 4A is an embodiment of a digital time signal generator. As shown in fig. 4A, the time signal generator 1 includes a compensation unit 11, a counting unit 12, a comparison unit 14 and a logic unit 16. The compensation unit 11 includes a first multiplier M1, a second multiplier M2, an adder ADD, and a divider DIV. The adder ADD is coupled to the first multiplier M1. The divider DIV is coupled to the adder ADD and the second multiplier M2.
The first multiplier M1 is used for providing the digital load current signal SILMultiplying by a first constant ki to obtain a first product (ki SIL). The second multiplier M2 is configured to multiply the digital input voltage signal SVin by a second constant kv to obtain a second product (kv SVin). The adder ADD is used for adding the first product ki SI to the digital output voltage signal SVoutLTo obtain the SUM SUM ═ (SVout + ki SI ═ SI)L). The divider DIV is configured to divide the SUM by the second product (kv SVin) to obtain the compensation signal S1, i.e. the compensation signal S1 (SVout + ki SI)L)/(kv*SVin)。
The counting unit 12 provides a counting signal S2 according to the clock signal CLK and the trigger signal TR. The comparing unit 14 receives the compensation signal S1 from the compensating unit 11 and the count signal S2 from the counting unit 12, and provides a comparison signal S3 to the logic unit 16 according to the compensation signal S1 and the count signal S2. The logic unit 16 receives the trigger signal TR and the comparison signal S3, and provides a time signal Ton to the driving circuit DR according to the trigger signal TR and the comparison signal S3.
It should be noted that the digital output voltage signal SVout, the digital input voltage signal SVin and the digital load current signal SI provided to the compensation unit 11LThe output voltage Vout, the input voltage Vin and the load current I can be converted by the analog-to-digital conversion unit 10LBut not limited thereto.
Referring to fig. 4B, fig. 4B is another embodiment of a digital time signal generator. As shown in fig. 4B, the time signal generator 1 includes a compensation unit 11, a counting unit 12, a comparison unit 14 and a logic unit 16. The compensation unit 11 includes a first multiplier M1, a second multiplier M2, a first divider DIV1, a second divider DIV2, and an adder ADD. The first multiplier M1 is coupled to the first divider DIV 1. The second multiplier M2 is coupled to the divider DIV and coupled to the first divider DIV1 and the second divider DIV 2. The first divider DIV1 and the second divider DIV2 are coupled to the adder ADD.
The first multiplier M1 is used for providing the digital load current signal SILMultiplying by a first constant ki to obtain a first product (ki SIL). The second multiplier M2 is configured to multiply the digital input voltage SVin signal by a second constant kv to obtain a second product (kv SVin). A first divider DIV1 for dividing the first product (ki SI)L) Dividing the first product (kv SVin) to obtain a first quotient (ki SI)L) V (kv SVin). The second divider DIV2 is configured to divide the digital output voltage signal SVout by the second product (kv SVin) to obtain a second quotient SVout/(kv SVin). The adder ADD is used for adding the first quotient (ki) SIL) V SVin is added to the second quotient SVout/(kv SVin) to obtain a compensation signal S1, i.e., a compensation signal S1 (SVout + ki SI)L)/(kv*SVin)。
It should be noted that the digital output voltage signal SVout, the digital input voltage signal SVin and the digital load current signal SI provided to the compensation unit 11LThe output voltage Vout, the input voltage Vin and the load current I can be converted by the analog-to-digital conversion unit 10LBut not limited thereto.
Next, please refer to fig. 5A to 5D. Fig. 5A and 5B are schematic diagrams of a conventional digital time signal generator and a time signal provided by the digital time signal generator of the present invention in a steady state under a light load, respectively. Fig. 5C and 5D are schematic diagrams of the time signals provided by the conventional digital time signal generator and the digital time signal generator of the present invention under the heavy load steady state, respectively.
As shown in fig. 5A and 5B, in the steady state of light load, because the characteristics of the digital circuit, a slight calculation error (for example, a compensation value caused by the load current in the light load state) is omitted, the period D1 and the on-time length T1 of the time signal Ton1 provided by the conventional digital time signal generator and the period D2 and the on-time length T2 of the time signal Ton2 provided by the digital time signal generator of the present invention are not changed, for example, the periods of both are 1000ns and the on-times of both are 300 ns.
As shown in fig. 5C, in the heavy-duty steady state, the on-time length T1 'of the time signal Ton1 provided by the conventional digital time signal generator is still maintained at 300ns, but this also causes the period D1' of the time signal Ton1 to change from 1000ns to 860ns, which is shortened by 140ns in total, resulting in that the switching frequency of the conventional dc-dc conversion circuit becomes high and the power conversion efficiency thereof is affected.
In contrast, as shown in fig. 5D, in the heavy-load steady state, the on-time length T2 'of the time signal Ton2 provided by the digital time signal generator of the present invention changes from 300ns to 340ns as the load current increases, and the period D2' of the time signal Ton2 only changes from 1000ns to 995ns, which only shortens 5ns in total, so that the switching frequency of the dc-dc converter circuit can be maintained constant to improve the power conversion efficiency.
Another preferred embodiment according to the present invention is a dc-dc converter circuit. In this embodiment, the dc-dc conversion circuit is used to convert an input voltage into an output voltage.
As shown in FIG. 2, the DC-DC converting circuit 2 is coupled to a load LD and has a load current ILFlows through the load LD. The dc-dc conversion circuit 2 includes an output stage OS, a driving circuit DR, a feedback circuit FB and a time signal generator 1. The output stage OS is coupled to the load LD and is used for receiving at least one driving signal DS 1-DS 2 to convert the input voltage Vin into the output voltage Vout. The driving circuit DR is coupled to the output stage OS and configured to generate at least one driving signal DS 1-DS 2 according to the time signal Ton. The feedback circuit FB is coupled to the output stage OS for generating the trigger signal TR according to the output voltage Vout. The time signal generator 1 is coupled between the feedback circuit FB and the driving circuit DR, and is configured to receive an input voltage Vin, an output voltage Vout, and a load current ILAnd a trigger signal TR to generate a time signal Ton.
As shown in fig. 3, the time signal generator 1 comprises a compensation unit 11. The compensation units 11 respectively receive digital output voltages related to the output voltage VoutSignal SVout, digital input voltage signal SVin related to input voltage Vin and load current ILCorrelated digital load current signal SILAnd to the digital output voltage signal SVout, the digital input voltage signal SVin and the digital load current signal SILThe arithmetic processing is performed to generate the compensation signal S1 and provide the time signal Ton according to the compensation signal S1. Therefore, the time signal Ton, the digital input voltage signal SVin, the digital output voltage signal SVout and the digital load current signal SILIt is related.
Furthermore, the time signal generator 1 comprises an analog-to-digital conversion unit 10. The analog-to-digital conversion unit 10 receives an output voltage Vout, an input voltage Vin, and a load current ILAnd respectively converted into a digital output voltage signal SVout, a digital input voltage signal SVin and a digital load current signal SILAnd then supplied to the compensation unit 11.
During heavy load, a load current I flowing through the load LDLIncrease so as to be in contact with the load current ILCorrelated digital load current signal SILIncreasing, the compensation signal S1 generated by the compensation unit 11 also increases. For other components in the dc-dc conversion circuit 2 and their operation, please refer to the above embodiments, which are not described herein.
Compared with the prior art, the dc-dc conversion circuit and the time signal generator thereof of the invention can adjust the time signal provided to the driving circuit of the dc-dc conversion circuit by the compensation signal related to the load current, so that when the dc-dc conversion circuit operates in a heavy load steady state and the load current is increased, the on-time in the time signal provided by the time signal generator of the invention is increased, thereby maintaining the constant switching frequency of the dc-dc conversion circuit and improving the power conversion efficiency of the dc-dc conversion circuit when the dc-dc conversion circuit operates in the heavy load steady state.
The foregoing detailed description of the preferred embodiments is intended to more clearly illustrate the features and spirit of the present invention, and not to limit the scope of the invention by the preferred embodiments disclosed above. On the contrary, it is intended to cover various modifications and equivalent arrangements included within the scope of the claims.
Claims (10)
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| CN201811415834.3A CN111224645B (en) | 2018-11-26 | 2018-11-26 | DC-DC conversion circuit and time signal generator thereof |
| TW108142759A TWI789561B (en) | 2018-11-26 | 2019-11-25 | Dc-dc converter and time signal generator thereof |
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| US20150146458A1 (en) * | 2013-11-27 | 2015-05-28 | Infineon Technologies Austria Ag | System and Method for Switched Mode Power Supply |
| CN105048811A (en) * | 2015-08-17 | 2015-11-11 | 西安交通大学 | Conduction time correction fixed-frequency cycle-skip controller and method of DC-DC converter |
| CN107809176A (en) * | 2016-09-08 | 2018-03-16 | 力智电子股份有限公司 | DC-DC converter and control method thereof |
| TWI613883B (en) * | 2017-01-06 | 2018-02-01 | 茂達電子股份有限公司 | Constant on-time converter having fast transient response |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111224645B (en) | 2023-10-20 |
| TW202037049A (en) | 2020-10-01 |
| TWI789561B (en) | 2023-01-11 |
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