CN111009610A

CN111009610A - Capacitive electronic chip component

Info

Publication number: CN111009610A
Application number: CN201910939145.0A
Authority: CN
Inventors: A·马扎基; P·弗纳拉
Original assignee: STMicroelectronics Rousset SAS
Current assignee: STMicroelectronics Rousset SAS
Priority date: 2018-10-08
Filing date: 2019-09-30
Publication date: 2020-04-14
Also published as: FR3087027A1; CN210805823U; US20200111866A1; US10971578B2

Abstract

Embodiments of the present disclosure relate to capacitive electronic chip components. The present disclosure relates to a capacitive component including a trench and a first portion of a first silicon oxide layer vertically aligned with the trench and a first portion of a second conductive layer and a third conductive layer including polysilicon or amorphous silicon, the first The first portion of the layer is located between and in contact with the first portion of the second and third layers.

Description

Capacitive electronic chip component

Technical Field

The present disclosure relates generally to electronic devices, and in particular to capacitive components of electronic integrated circuit chips and electronic chips including such capacitive components.

Background

Electronic integrated circuit chips typically include transistors and/or memory cells. Such chips also typically include capacitive components.

Disclosure of Invention

Embodiments overcome all or some of the disadvantages of known electronic chips.

Embodiments overcome all or some of the disadvantages of known electronic chip capacitive components.

Embodiments provide a capacitor component comprising a trench and a first portion of a first silicon oxide layer vertically aligned with the trench and first portions of a second conductive layer and a third conductive layer comprising polysilicon or amorphous silicon, the first portion of the first layer being located between and in contact with the first portions of the second layer and the third layer.

According to an embodiment, the first portion of the second layer is positioned vertically aligned with the first portion of the third layer.

According to an embodiment, the first layer, the second layer and the first portion of the third layer form a stack.

According to an embodiment, the side of the first portion of the first, second and third layer corresponds to a side of the stack.

According to an embodiment, the stack is located entirely over the trench.

According to an embodiment, the capacitive component includes an insulating layer located in the trench.

According to an embodiment, the insulating layer completely fills the trench.

According to an embodiment, the trench is filled with polysilicon walls separated from the trench walls by an insulating layer.

According to an embodiment, the periphery of the first portion of the second layer is separated from the first portion of the third layer by an annular portion of the oxide-nitride-oxide tri-layer structure.

An embodiment provides an electronic chip comprising a first capacitive component as defined above.

According to an embodiment, the chip further comprises a transistor gate comprising a second portion of the second layer and resting on a second portion of the first layer.

According to an embodiment, the chip comprises a second capacitive component such as defined above, the second and third layers of the first and second capacitive components are common, and the first layers have different thicknesses.

According to an embodiment, the chip comprises an additional capacitive component comprising a first portion of the oxide-nitride-oxide tri-layer structure between the second layer and an additional portion of the third layer.

According to an embodiment, the chip comprises a second part of the three-layer structure located between the floating gates and the control gates of the memory cells, the floating gates and the control gates preferably comprising parts of the second layer and the third layer, respectively.

Embodiments provide a method of forming a capacitive component, comprising forming a trench and a first portion of a first silicon oxide layer vertically aligned with the trench and first portions of a second conductive layer and a third conductive layer comprising polysilicon or amorphous silicon, the first portion of the first layer being between and in contact with the first portions of the second layer and the third layer.

According to an embodiment, the first, second and third layers form a stack, the stack being obtained from the first, second and third layers by etching a region surrounding the stack.

According to an embodiment, the method is a method of forming an electronic chip.

According to an embodiment, the method includes simultaneously forming the first layer and at least a portion of a gate insulator of the transistor.

According to an embodiment, the method includes simultaneously forming the second layer and at least a portion of the floating gate of the memory cell.

According to an embodiment, the method comprises forming the third layer and at least a portion of the transistor gate simultaneously.

The foregoing and other features and advantages are discussed in detail below in the following non-limiting description of specific embodiments in connection with the accompanying drawings.

Drawings

FIGS. 1A-1C illustrate three steps of an embodiment of a method of forming an electronic chip;

FIGS. 2A-2C illustrate three additional steps of the embodiment of the method of FIGS. 1A-1C;

FIG. 3 shows an embodiment of a capacitive microchip device;

FIGS. 4 to 7 show steps of an embodiment of a method for forming a capacitive component of an electronic chip; and

fig. 8 is a cross-sectional view schematically showing the structure of an electronic chip obtained by an embodiment of the method for forming a capacitive component.

Detailed Description

Like elements in different figures are denoted by like reference numerals. In particular, structural and/or functional elements common to different embodiments may be denoted with the same reference numerals and may have the same structural, dimensional and material properties.

For clarity, only steps and elements useful for understanding the described embodiments are shown and described in detail. In particular, components of the transistors and memory cells other than gates and gate insulators are neither described nor shown, and the embodiments described herein are compatible with common transistors and memory cells.

Throughout this disclosure, the term "connected" is used to indicate a direct electrical connection between circuit components, the circuit components having no intervening components other than conductors, and the term "coupled" is used to indicate an electrical connection that may be either direct between circuit components or via one or more intervening components.

In the following description, when referring to terms defining an absolute position, such as the terms "top," "bottom," "left," "right," and the like, or terms defining a relative position, such as the terms "above," "below," "above," and the like, or terms defining a direction, such as the terms "horizontal," "vertical," and the like, it is meant to refer to the orientation of the drawing figures unless otherwise indicated.

The terms "about", "substantially" and "approximately" as used herein refer to a tolerance of ± 10%, preferably ± 5%, of the value in question.

Fig. 1A-2C show six successive steps S1, S2, S3, S4, S5, and S6 of an embodiment of a method of forming an electronic chip. Each step is illustrated by a partial simplified cross-sectional view of the structure obtained after that step. The chip obtained by the method comprises a transistor, a memory cell and a capacitive component. Transistors typically include a gate separated from a channel region between a drain region and a source region by a gate insulator. The memory cell typically includes a transistor having a floating gate with a control gate on top.

In step S1 of fig. 1A, a semiconductor substrate 102, preferably made of silicon, is provided. A trench 104 is formed in the substrate 102 from a front surface (or upper surface) of the substrate. The trench 104 has a depth of, for example, more than 100nm, preferably more than 300 nm. In this embodiment, the trench is filled with an electrically insulating layer, such as silicon oxide. The trench is preferably completely filled with an insulating layer. Preferably, after the filling, a portion of the insulating layer located outside the trench is removed. The insulator portion 106 located in the trench may be flush with the front surface of the substrate 102. As a variation, the tops of these portions are located above the front surface of the substrate 102.

The next steps S2 to S6 of the method as shown in fig. 1B-2C are directed to forming capacitive components located in respective portions C1, C2 and C3 on the insulator 106 of the trench 104. Preferably, steps S2 to S6 further aim to form, in the portions M1, T2 and T3 located on the substrate region delimited by the trench 104:

a stack of floating and control gates of the memory cells, separated by a first gate insulator, in the portion M1;

-in the portion T2, a transistor gate insulated by a second gate insulator; and

in the portion T3, the transistor gate is insulated by a third gate insulator.

The elements shaped during steps S2 to S6 are shown only in the portions C1, C2, C3, M1, T2, and T3 of the electronic chip. The formation and possible removal of elements located outside the portions C1, C2, C3, M1, T2 and T3 are not described and, on the basis of the present description, the steps described herein are compatible with usual electronic chip manufacturing methods, within the abilities of a person skilled in the art.

In step S2 shown in fig. 1B, a conductive layer 120 including polysilicon or amorphous silicon is formed on the structure obtained in step S1. The silicon preferably comprises crystals having a dimension in a direction parallel to the front surface of less than about 200nm, such as 200nm, or less than the thickness of layer 120. The layer 120 preferably has a thickness in the range of 100nm to 150 nm. Layer 120 is fully conductive, i.e., does not include an insulating region. Preferably, layer 120 is made of doped polysilicon only or doped amorphous silicon only. As a variant, the layer 120 comprises, in addition to polycrystalline silicon or amorphous silicon, a conductive layer, for example a metal layer. Layer 120 includes a portion of each of portions M1, C1, C2, and C3. In this specification, layer portions have the same thickness as the relevant layer.

Sections T2 and T3 do not have layer 120. To achieve this, as an example, layer 120 is deposited and then layer 120 is removed from layers T2 and T3 by dry etching using a mask that does not cover portions T2 and T3.

In step S3 shown in fig. 1C, the oxide-nitride-oxide tri-layer structure 140 is deposited. Trilayer structure 140 includes a portion of each of portions M1 and C1. The three-layer structure 140 is formed of a silicon oxide layer 142, a silicon nitride layer 144, and a silicon oxide layer 146 in this order. Thus, each portion of the tri-layer structure includes a portion of each of

layers

142, 144, and 146. Trilayer structure 140 covers and preferably contacts portions of layer 120 located in sections M1 and C1. The segments T2, C2, T3 and C3 do not include the tri-layer structure 140. For this purpose, the trilayer structure 140 is preferably removed after deposition in the portions T2, C2, T3 and C3, for example by etching in the portions C2 and C3 up to the layer 120 and in the portions T2 and T3 up to the substrate 102.

In step S4 shown in fig. 2A, a silicon oxide layer 200 having a portion in each of the portions C2 and T2 is formed on the structure obtained after step S3. In portion C2, layer 200 is in contact with polysilicon layer 120. In portion T2, layer 200 is preferably in contact with substrate 102, but it may also be provided that any additional layers, such as dielectric layers, are formed on substrate 102 prior to forming layer 200. Preferably, the layer 200 is deposited over the entire front surface of the structure, and the layer 200 is grown in all portions C1, M1, C2, T2, C3 and T3 on the front surface. Layer 200 then corresponds to the increase in thickness of upper layer 144 of the three-layer structure in sections M1 and C1. Layer 200 is then removed from portions T3 and C3. As an example, the layer 200 is obtained by thermal oxidation of the upper surface of the layer 120 in the portions C2 and C3 and of the substrate in the portions T2 and T3. The oxide thus formed is then removed from the portions T3 and C3.

In step S5 shown in fig. 2B, a silicon oxide layer 220 having a portion in each of the portions C3 and T3 is formed on the structure obtained after step S4. In section C3, layer 220 is in contact with layer 120. In portion T3, layer 220 is preferably in contact with substrate 102, but additional layers may be provided between substrate 102 and layer 220. Preferably, layer 220 is deposited over the entire front surface of the structure, or layer 220 is grown in all portions C1, M1, C2, T2, C3, and T3 on the front surface. Layer 220 then corresponds to the increase in thickness of upper layer 144 of trilayer structure 140 in sections M1 and C1. Layer 220 then corresponds to the increase in thickness of layer 200 in sections C2 and T2. By way of example, layer 220 is obtained by thermal oxidation of the upper surface of layer 120 in portion C3 and of the substrate in portion T3. Thermal oxidation may increase the thickness of layer 200.

Preferably, after step S5, the thickness of tri-layer structure 140 is in the range of about 12nm to about 17nm, preferably in the range of 12nm to 17nm, for example 14.5 nm. Preferably, after step S5, the thickness of layer 200 is in the range of about 4nm to about 7nm, preferably in the range of 4nm to 7nm, for example 5.7 nm. The thickness of layer 220 is preferably less than the thickness of layer 200. Preferably, the thickness of layer 220 is in the range of about 2nm to about 3nm, preferably in the range of 2nm to 3nm, for example 2.1 nm.

In step S6 shown in fig. 2C, a conductive layer 240 including doped polysilicon or doped amorphous silicon is formed on the structure obtained after step S5. Layer 120 is fully conductive, i.e., does not include an insulating region. Preferably, layer 240 is made of doped polysilicon. Alternatively, layer 240 includes a conductive sublayer, such as a metallic sublayer, having polysilicon resting thereon. Layer 240 has a portion in each of sections C1, C2, C3, M1, T2, and T3. These portions of layer 240 are positioned to align vertically with portions of layer 120 of portions C1, C2, C3, and M1. Layer 240 is preferably in contact with trilayer structure 140 in sections M1 and C1. In sections C2 and C3, layer 240 is in contact with

layers

200 and 220, respectively. In section T2, layer 240 is preferably in contact with layer 200, but one or more additional layers, such as dielectric layers, may be provided between

layers

200 and 240. In portion T3, layer 240 is preferably in contact with layer 220, but one or more additional layers, such as dielectric layers, may be provided between layer 220 and layer 240. Layer 240 preferably has a thickness in the range from 100nm to 300nm, for example 200 nm.

Step S6 specifies:

in portion C1, capacitive component 260 comprises a stack of parts of tri-layer structure 140 between portions of

conductive layers

120 and 240;

in section C2, capacitive component 262 comprises a stack of portions of dielectric layer 200 between portions of

layers

120 and 240;

in section C3, capacitive component 264 comprises a stack of portions of dielectric layer 220 between portions of

layers

120 and 240;

in portion M1, the stack of floating gates of memory cells is defined by a portion of layer 120, a portion of dielectric tri-layer structure 140, and a portion of control gates of memory cells defined by a portion of layer 240;

in the portion T2, the transistor gate is defined by a portion of the conductive layer 240, resting on the gate insulator defined by a portion of the layer 200; and

in portion T3, the transistor gate is defined by a portion of conductive layer 240, resting on a gate insulator defined by a portion of layer 220.

In the above method:

simultaneously forming the conductive portion 120 of the capacitive component and the floating gate of the memory cell;

simultaneously forming a dielectric of the capacitive component and a gate insulator of the transistor and a gate insulator of the memory cell; and

the conductive portion 240 of the capacitive component and the gates of the transistors and the gates of the memory cells are formed simultaneously.

Thus, the capacitive component is obtained without additional steps with respect to a chip comprising only transistors and memory cells.

Because

capacitive components

260, 262, and 264 include conductor-dielectric-conductor stacks located on the isolation trenches, the surface area of the chip is reduced relative to the surface area of a chip whose capacitive components are located between isolation trenches.

The capacitive component 260 may be used for high voltages, for example, on the order of greater than 10V. Such a high voltage corresponds, for example, to the programming of the memory cell. Capacitor with a capacitor elementThe component 262 may be used for averaging voltages, for example, in a range of the order of from 0V to 6.5V, for example 5V. Such an average voltage corresponds for example to the logic level of the digital circuit. The capacitive component 264 may be used for low voltages, for example, in the range of the order of 0V to 1.4V. Such low voltages correspond to filtering applications, e.g. decoupling, such as decoupling of the power supply voltage, or radio reception. For the same capacitance value, the smaller the surface area they occupy due to the small dielectric thickness of the capacitive components. Thus, for component 264, greater than from 12 fF/. mu.m can be achieved²To 20 fF/. mu.m²A capacitance value of the order of (d). Preferably, the capacitance value of component 264 is greater than 18fF/μm²Of the order of magnitude of (d). Thus, the surface area occupied by the capacitive components of the chip is reduced compared to a chip comprising only capacitive components adapted for high voltages and/or average voltages.

In addition,

capacitive components

262 and 264 are located on the insulator 106 of the trench, which are more capable of filtering radio frequencies than are the following capacitive components: the capacitive component is located directly on a conductor such as a semiconductor substrate; or the capacitive component is separated from such a conductor by an insulator having a thickness less than the thickness of insulator 106.

In the above method, one or more of the portions C1, C2, C3, M1, T2, and T3 may be omitted while maintaining at least one of the

capacitive components

262 and 264.

Fig. 3 shows an embodiment of a capacitive microchip device 300.

Capacitive component 300 is similar to component 264 of fig. 2, in that each trench 104 is replaced by one or more trenches 302, with the stack of portions of

layers

120, 220, and 240 overlying trenches 302 and overlying regions of substrate 102 located between trenches 302 and on either side of the trenches. Layer 304 electrically insulates the substrate region from the stack. The layer 304 has a thickness, for example, of the order of less than 15nm, preferably 3.2 nm. The trenches 302 have their walls and their bottom covered with an electrically insulating layer 305. The trenches are filled with an electrical conductor, preferably doped polysilicon, which then forms a conductive wall 306 in each trench 302 separated from the substrate by an insulating layer 305. For example, layer 305 has a thickness in the order of the thickness of layer 304.

The trench 302 preferably has a depth in the range from 300nm to 600 nm. The trench preferably has a width in the range from 0.1 μm to 0.3 μm. Layer 120 is separated from wall 306, for example, by an insulating layer portion 320. Wall 306 and layer 120 are then joined together (connection 330). As a variant, the layer 120 is in contact with the wall 306. Layer 120 and wall 306 are coupled to, preferably connected to, terminal a of capacitive component 300.

Preferably, the trench 302 defines a P-type doped region 310 of the substrate 102. The region 310 is preferably located on a common N-type doped region 312. The trenches 302 reach, preferably penetrate, into the regions 312 such that the regions 310 are electrically insulated from each other. Region 310 is coupled to terminal B of capacitive component 300. The upper layer 240 is coupled to terminal B.

Thus, for the same occupied surface area, capacitive component 300 formed between terminals a and B has a capacitance value that is greater than the capacitance value of a capacitive component that includes only trench 302, layer 304, and region 310. Further, capacitive component 300 has a capacitance value that is greater than the capacitance value of a similar capacitive component for the same occupied surface area, where layer 220 would be replaced by an oxide-nitride-oxide tri-layer structure, such as tri-layer structure 140.

Preferably, to form a chip including capacitive component 300, steps S2 through S6 of the method of fig. 1B-2C are performed, wherein these portions of

layers

120, 220, and 240 are formed simultaneously in

capacitive components

300 and 264. Thus, portions of

layers

120, 220, and 240 of

capacitive components

300 and 264 are portions of the

same layers

120, 220, and 240.

As a variation, in the method of fig. 1A-2C, the formation of capacitive component 264 is replaced with the formation of capacitive component 300. In another variation, the portion of layer 220 is replaced by a portion of layer 200 in capacitive component 300. Preferably, these portions of

layers

120, 200, and 240 are then formed simultaneously in

capacitive components

300 and 262. The formation of capacitive element 262 may also be replaced by the formation of capacitive element 300.

Fig. 4 to 7 are cross-sectional views schematically illustrating steps of an embodiment of a method for forming a capacitive component. As an example, the capacitive component is capacitive component 264 of the method of fig. 1A-2C, located in section C3. The method of fig. 4 to 7 focuses more particularly on the formation and removal of elements located outside the portion C3.

The steps of fig. 4 and 5 correspond to step S3 of fig. 1C. The layer 120 is formed in the part C3 in step S2. Layer 120 extends across the entire portion C3 and preferably over a portion of insulator 106 (portion 410) outside of portion C3.

In the step of fig. 4, three-layer structure 140 is formed inside and outside portion C3. Trilayer structure 140 is formed on the portion of layer 120 located inside portion C3 and is also formed on insulator 106 of trench 104, preferably in contact with insulator 106. The three-layer structure 140 may be entirely deposited on the upper surface of the structure obtained in step S2.

In the step of fig. 5, tri-layer structure 140 is etched inside and outside portion C3. The horizontal portion of layer 140 is completely removed by this etch. In practice, however, portions 510 of layer 140 may remain against the sides of layer 120.

The steps of fig. 6 and 7 correspond to step S6 of fig. 2C. A silicon oxide layer 220 is formed on layer 120 in step S5. Silicon oxide layer 220 may extend (portion 610) on the sides of layer 120.

In the step of fig. 6, a conductive layer 240 is formed on the structure obtained in step S5. In this step, the conductive layer 240 preferably covers the entire upper surface of the structure.

In the step of fig. 7, a portion of the structure surrounding portion C3 is etched. Thus, the resulting capacitive element 264 corresponds to the insulating stack formed by

layers

120, 220, and 240 located only in portion C3. As an example, all regions outside the portion C3 on the insulator 106 of the associated trench 104 are removed. In other words, the sides of stack 264 correspond to the sides of the stack of

layers

120, 220, and 240, and to the edges of portion C3. The sides of each

layer

120, 220, and 240 are not covered by portions of the conductive layer. In a next step, not shown, the sides of the stack 710 may be covered with an electrical insulator.

In other embodiments, layer 240 may be etched such that a portion of layer 240 remains on the sides of layer 120 and/or on portions 510 and/or portions 610, leaving portions 510 and/or 610 in place. However, the upper corners of layer 120 are then surrounded by layer 240 and insulated from layer 240 only by layer 220 and

portions

510 and 610. This will result in a tip effect which reduces the breakdown voltage of the capacitor. Also, the presence of portion 510 may result in a lower breakdown voltage and/or a higher noise level for the capacitor. In contrast, the methods of fig. 4-7 allow for avoiding problems caused by the upper corners and

portions

510 and 610 of layer 120.

Fig. 8 is a cross-sectional view schematically showing the structure of an electronic chip obtained by an embodiment of the method for forming a capacitive component. As an example, the capacitive component is capacitive component 264 of the method of fig. 1A-2C, located in section C3 of the electronic chip. Similar to the method of fig. 4-7, the method of fig. 8 more specifically focuses on forming and removing elements located outside of portion C3.

In a step corresponding to step S2 of fig. 1B, layer 120 is in section C3. Layer 120 extends across the entire portion C3 and preferably over a portion of insulator 106 (portion 410) outside of portion C3.

In a step corresponding to step S3 of fig. 1C, triple-layered structure 140 is formed inside and outside portion C3. Trilayer structure 140 is formed on the portion of layer 120 that is inside portion C3 and is also formed on insulator 106 of trench 104, preferably in contact with insulator 106. The three-layer structure 140 may be deposited on the entire upper surface of the structure obtained in step S2. Next, trilayer structure 140 is etched inside portion C3 and outside annular portion 810 of the electronic chip surrounding portion C3, leaving annular portion 815 of trilayer structure 140 surrounding portion C3.

In step S5 of fig. 2B, a silicon oxide layer 220 is formed on layer 120. Silicon oxide layer 220 may extend outside portion C3 onto annular portion 815 of tri-layer structure 140.

In a step corresponding to step S6 of fig. 2C, conductive layer 240 is formed in portion C3 and in annular portion 820 extending around portion C3, e.g., from the perimeter of portion C3. The ring portion 820 of the electronic chip may correspond to the interior of the ring portion 810. Layer 240 may be formed only within portions C3 and 820, or may be formed inside and outside of both portions C3 and 820 and removed outside of portions C3 and 820. This results in a portion of conductive layer 240 being located only in portions C3 and 820. In the resulting capacitive element, the periphery of the portion of conductive layer 240 is separated from the portion of conductive layer 120 by annular portion 815 of tri-layer structure 140.

Various embodiments and modifications have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that other variations will occur to those skilled in the art. As an example, each of the methods of fig. 4-7 and the method of fig. 8 may be applied to capacitive component 262 located in portion C2 instead of capacitive component 264. In another example, the methods of fig. 4-7 are applied to both

capacitive components

262 and 264.

Finally, the practical implementation of the described embodiments and variants is within the abilities of one skilled in the art based on the functional indications given above.

Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the disclosure. Accordingly, the foregoing description is by way of example only and is not intended as limiting.

The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by this disclosure.

Claims

1. A capacitive component, comprising:

a semiconductor substrate;

a trench in the semiconductor substrate;

a silicon oxide layer vertically arranged with the first trench; and

a first conductive layer and a second conductive layer comprising polysilicon or amorphous silicon, the silicon oxide layer being located between and in contact with the first conductive layer and the second conductive layer.

2. The capacitive component of claim 1, wherein the first conductive layer is positioned in vertical alignment with the second conductive layer.

3. The capacitive component of claim 1, wherein the silicon oxide layer forms a stack with the first and second conductive layers.

4. The capacitive component of claim 3, wherein sides of the silicon oxide layer and sides of the first and second conductive layers correspond to sides of the stack.

5. The capacitive component of claim 3, wherein the stack is entirely over the trench.

6. The capacitive component of claim 1, comprising an insulating layer in the trench.

7. The capacitive component of claim 6, wherein the insulating layer completely fills the trench.

8. The capacitive component of claim 6, wherein the insulating layer lines walls of the trench, the capacitive device further comprising polysilicon walls separated from the substrate by the insulating layer.

9. The capacitive component of claim 1, wherein the first conductive layer comprises a periphery, the capacitive component further comprising:

an oxide-nitride-oxide structure in a ring shape separating the periphery of the first conductive layer from the second conductive layer.

10. An electronic chip, comprising:

a semiconductor substrate;

a first capacitive component, the first capacitive component comprising:

a first trench in the semiconductor substrate;

a first silicon oxide layer vertically arranged with the first trench; and

a first conductive layer and a second conductive layer comprising polysilicon or amorphous silicon, the first silicon oxide layer being located between and in contact with the first conductive layer and the second conductive layer.

11. The chip of claim 10, further comprising a transistor gate comprising a third conductive layer and a fourth conductive layer resting on the third conductive layer.

12. The chip of claim 10, comprising a second capacitive component, the second capacitive component comprising:

a second trench in the semiconductor substrate;

a second silicon oxide layer vertically arranged with the second trench; and

a third conductive layer and a fourth conductive layer comprising polysilicon or amorphous silicon, the second silicon oxide layer being located between and in contact with the third conductive layer and the fourth conductive layer, and the first silicon oxide layer and the second silicon oxide layer having different thicknesses.

13. The chip of claim 10, comprising a second capacitive component, the second capacitive component comprising:

a third conductive layer and a fourth conductive layer; and

a first oxide-nitride-oxide tri-layer structure between the third conductive layer and the fourth conductive layer.

14. The chip of claim 13, comprising a memory cell comprising a floating gate, a control gate, and a second oxide-nitride-oxide tri-layer structure between the floating gate and the control gate, the floating gate and the control gate comprising a fifth conductive layer and a sixth conductive layer.

15. A method, comprising:

forming a capacitive component comprising:

forming a trench in a semiconductor substrate;

forming a first portion of a first conductive layer vertically aligned with the trench, the first conductive layer comprising polysilicon or amorphous silicon;

forming a first portion of a silicon oxide layer vertically aligned with the trench on the first portion of the first conductive layer; and

forming a first portion of a second conductive layer comprising polysilicon or amorphous silicon, the first portion of the silicon oxide layer being between and in contact with the first portions of the first and second conductive layers.

16. The method of claim 15, wherein a first portion of the silicon oxide layer and a first portion of the first and second conductive layers form a stack, the stack being obtained from the silicon oxide layer and the first and second conductive layers by etching a region surrounding the stack.

17. The method of claim 15, wherein the first portion of the first conductive layer comprises a periphery, the method further comprising:

forming an oxide-nitride-oxide structure in a ring shape, the oxide-nitride-oxide structure separating the periphery of the first portion of the first conductive layer from the first portion of the second conductive layer.

18. The method of claim 15, comprising simultaneously forming a first portion of the silicon oxide layer and a second portion of the silicon oxide layer, the second portion of the silicon oxide layer being a gate insulator of a transistor.

19. The method of claim 15, comprising simultaneously forming a first portion of the first conductive layer and a second portion of the first conductive layer, the second portion of the first conductive layer being a floating gate of a memory cell.

20. The method of claim 15, comprising simultaneously forming a portion of the second conductive layer and a second portion of the second conductive layer, the second portion of the second conductive layer being a transistor gate.