CN110783357B - CMOS image sensor with time delay integration and method of forming the same - Google Patents

Abstract

A time delay integrated CMOS image sensor and method of forming the same, the time delay integrated CMOS image sensor comprising: the substrate comprises a plurality of unit areas arranged along a first direction; the first photoelectric region, the second photoelectric region and the source drain region are mutually separated and positioned in the substrate, the source drain region is positioned between the first photoelectric region and the second photoelectric region, and the first photoelectric region and the second photoelectric region respectively cross the plurality of unit regions; and the first gate structure, the second gate structure, the third gate structure and the fourth gate structure are positioned on the substrate in the unit area. Thus, the performance of the time delay integrated CMOS image sensor can be improved.

Description

CMOS image sensor with time delay integration and method of forming the same

technical field

The present invention relates to the field of semiconductors, in particular to a CMOS image sensor with time delay integration and a method for forming the same.

Background technique

Image sensors have been widely used in digital cameras, mobile phones, medical devices, automobiles and other applications. With the rapid development of image sensor technology, people have higher requirements for the performance of image sensors.

Time Delay Integration (TDI) image sensor is an evolution of linear image sensor. The imaging mechanism of the time delay integral image sensor is to expose the pixels passing through the photographed object line by line, and accumulate the exposure results, so as to solve the problem of weak imaging signal caused by insufficient exposure time of high-speed moving objects. The time delay integrating image sensor can increase the effective exposure time and improve the image signal-to-noise ratio.

Time-delay integral image sensors are divided into two types: CCD and CMOS. One is to make a TDI image sensor on the CCD process. Due to the particularity of the CCD process, other processing circuits cannot be integrated on the image sensor, and the versatility and flexibility are poor. Another TDI image sensor is a CMOS type. The TDI image sensor is based on a general CMOS manufacturing process, and a device similar to a CCD function is embedded, namely an eCCD (embedded CCD), thereby forming a TDI-CMOS image sensor.

However, the existing time delay integration CMOS image sensors still need to improve the performance.

SUMMARY OF THE INVENTION

The technical problem solved by the present invention is to provide a time delay integration CMOS image sensor and its forming method, so as to improve the performance of the time delay integration CMOS image sensor.

In order to solve the above technical problems, the technical solution of the present invention provides a time delay integration CMOS image sensor, comprising: a substrate, the substrate includes a plurality of unit regions arranged along a first direction; a photoelectric region, a second photoelectric region and a source-drain region, the first photoelectric region and the second photoelectric region are arranged along a second direction, the second direction and the first direction are perpendicular to each other, the source-drain region The first photoelectric region and the second photoelectric region are located between the first photoelectric region and the second photoelectric region, and the first photoelectric region and the second photoelectric region respectively span the plurality of unit regions; a first gate structure, and the first gate structure is located on the first photoelectric region; a second gate structure is located on the substrate in the cell region, and the second gate structure is located on the on the second photoelectric region; a third gate structure, a part or all of the third gate structure is located on the substrate in the cell region, and the third gate structure is located in the first photoelectric region and all the on the surface of the substrate between the source and drain regions; a fourth gate structure, part or all of the fourth gate structure is located on the substrate in the unit region, and the fourth gate structure is located on the first gate structure on the surface of the substrate between the two photoelectric regions and the source and drain regions.

Optionally, at least one third gate structure and at least one fourth gate structure are located on the substrate surface of the cell region, and at least one of the source and drain regions is located in the cell region.

Optionally, the first photoelectric region has first ions, the second photoelectric region has first ions, and the source and drain regions also have first ions.

Optionally, the first gate structure further extends to the surface of the substrate outside the source and drain regions between the first photoelectric region and the second photoelectric region in the unit region.

Optionally, the second gate structure further extends to the surface of the substrate outside the source and drain regions between the first photoelectric region and the second photoelectric region in the unit region.

Optionally, it further includes: a plurality of second doping regions located in the substrate between adjacent source and drain regions, the second doping regions have second ions, and the conductivity type of the second ions is the same as that of all the second doping regions. The conductivity types of the first ions are opposite, the plurality of second doping regions are arranged along the first direction, and the first gate structure extends onto the second doping regions.

Optionally, it further includes: a plurality of second doping regions located in the substrate between adjacent source and drain regions, the second doping regions have second ions, and the conductivity type of the second ions is the same as that of all the second doping regions. The conductivity types of the first ions are opposite, the plurality of second doping regions are arranged along the first direction, and the second gate structure extends onto the second doping regions.

Optionally, the number of the source-drain region, the third gate structure and the fourth gate structure is one, and the source-drain region, the third gate structure and the fourth gate structure are all one. Each of the quad-gate structures spans the plurality of cell regions.

Optionally, the first gate structure further extends to the base surface between the projection of the third gate structure on the base surface and the first photoelectric region.

Optionally, the second gate structure further extends to the substrate surface between the projection of the fourth gate structure on the substrate surface and the second photovoltaic region.

Optionally, the substrate further has one or more isolation structures, and the isolation structures are located in one or both of the first photoelectric region and the second photoelectric region, which is opposite to the source and drain regions. side.

Correspondingly, the technical solution of the present invention also provides a method for forming a CMOS image sensor with any of the above-mentioned time delay integration.

Compared with the prior art, the technical scheme of the present invention has the following beneficial effects:

The time delay integration CMOS image sensor provided by the technical solution of the present invention has a first gate structure, a second gate structure, part or all of the third gate structure, and part or all of the third gate structure in each of the unit regions. Four gate structure, and the third gate structure is located on the surface of the substrate between the first photoelectric region and the source-drain region, and the fourth gate structure is located between the second photoelectric region and the source substrate surface between drain regions. Therefore, when the channel under the third gate structure is opened, electrons overflow after the channel under the first gate structure reaches full well, and when the channel under the fourth gate structure is opened When the channel under the second gate structure reaches the full well, the electrons that overflow after the well can be transferred to the same source and drain regions, and are transferred from the source and drain regions to the electrons that are electrically interconnected with the source and drain regions. An interconnect layer, absorbed by the interconnect layer. Therefore, one source-drain region can correspond to the overflow electrons of two photoelectric regions, so that the image sensor can reduce the number of the source-drain regions while having the anti-dispersion structure. The area of the second photoelectric region provides space, that is, the pixel fill factor of the time delay integration CMOS image sensor can be increased, so that the time delay integration CMOS image sensor can obtain higher sensitivity and dynamic range, and the time delay integration can be improved. Delay-integrating CMOS image sensor performance.

Further, since the first gate structure also extends to the substrate surface outside the source and drain regions between the first photoelectric region and the second photoelectric region in the unit region, the first gate structure can be increased. A photosensitive surface corresponding to a photoelectric region, and increasing the number of charges when the channel under the first gate structure reaches full well capacity, thereby improving the sensitivity and dynamic range of the time delay integration CMOS image sensor, thereby improving the The time-delay-integrated CMOS image sensor performance.

Further, since the conductivity type of the second ions is opposite to the conductivity type of the first ions, and at least one of the first gate structures extends to the second doping region, the first gate structure is There is an anti-doped region between the photoelectric region and the second photoelectric region, so that the dark current between the first photoelectric region and the second photoelectric region can be isolated, and the CMOS image sensor of the time delay integration is improved. performance.

Description of drawings

FIG. 1 is a schematic top-view structure diagram of a time delay integration CMOS image sensor;

Fig. 2 is the cross-sectional structure schematic diagram of Fig. 1 along the A-B tangent direction;

3 to 4 are schematic structural diagrams of a time delay integration CMOS image sensor according to an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a time delay integration CMOS image sensor according to another embodiment of the present invention;

6 to 7 are schematic structural diagrams of a time delay integration CMOS image sensor according to another embodiment of the present invention.

Detailed ways

As described in the background art, time delay integration CMOS image sensors need to increase in performance.

Under the condition of strong light, the electrons in the channel below the gate structure overflow into the adjacent channel after reaching the full well, which is called dispersion phenomenon. The signal cannot reflect the real illumination, causing the number of saturated pixels to increase more than the actual number, resulting in image color distortion, halo and other defects in the output image, thus reducing the quality of the output image of the CMOS image sensor with time delay integration.

FIG. 1 is a schematic top view of a time delay integration CMOS image sensor, and FIG. 2 is a schematic cross-sectional structure of FIG. 1 along the tangential direction of A-B.

Please refer to FIG. 1 and FIG. 2 , the time delay integration CMOS image sensor includes: a substrate 10, the substrate 10, the substrate 10 is a P-type silicon substrate, and the substrate 10 includes a plurality of photoelectric regions arranged at intervals I and isolation region II, the substrate has a photoelectric doping region 11 in the photoelectric region I, a source and drain region 13 and an isolation trench structure 12 in the isolation region II, the photoelectric doping region The region 11 is doped with N-type ions opposite to the conductivity type of the substrate 10, thus forming a photodiode, and the source and drain regions 13 are doped with N-type ions; several first gate structures located on the surface of the photoelectric region I 21; a plurality of second gate structures 22 located on the surface of the isolation region II, and the projection of the second gate structures 22 on the surface of the substrate 10, located in the photoelectrically doped region 11 on the surface of the substrate 10 and the projection of the source and drain regions 13 on the surface of the substrate 10 .

In the above embodiment, by applying a fixed positive voltage to the second gate structure 22, the channel under the second gate structure 22 can be opened, and by applying a fixed positive voltage to the source and drain regions 13 The voltage can form a channel in the source and drain regions 13 , so that electrons in the photoelectric doping region 11 can be transported into the channel of the source and drain regions 13 and transferred from the channel of the source and drain regions 13 to the interconnection layer that is electrically interconnected with the source and drain regions 13 and absorbed by the interconnection layer, so that when the electrons in the channel of the first gate structure 21 reach the full well and overflow occurs, the overflowed Electrons can be absorbed by the interconnection layer to achieve the effect of anti-dispersion phenomenon.

However, in order to achieve the effect of the above-mentioned anti-diffusion phenomenon, it is necessary to separately arrange a source-drain region 13 and a second gate structure 22 to correspond to a first gate structure 21, and in order to avoid electrons between the photoelectric regions I To solve the problem of crosstalk, an isolation structure 12 needs to be arranged in each of the isolation regions II to prevent the crosstalk of electrons in the channel under the first gate structure 21 in the adjacent photoelectric region I, so the area occupied by the isolation region II is relatively small. is large, resulting in reducing the ratio of the area of the photoelectric region I, reducing the pixel fill factor of the time delay integrating CMOS image sensor, thereby reducing the sensitivity and dynamic range of the time delay integrating CMOS image sensor, namely The performance of the time delay integrated CMOS image sensor is reduced.

In order to solve the above-mentioned technical problems, the technical solution of the present invention provides a CMOS image sensor with time delay integration. By realizing that one source and drain region corresponds to two photoelectric regions at the same time, the number of source and drain regions and isolation structures is reduced, thereby reducing the number of source and drain regions. The occupied area of the isolation region improves the performance of the time delay integration CMOS image sensor.

In order to make the above objects, features and beneficial effects of the present invention more clearly understood, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

3 to 4 are schematic structural diagrams of a time delay integration CMOS image sensor according to an embodiment of the present invention.

Please refer to FIGS. 3 and 4 . FIG. 3 is a schematic top view of a time delay integration CMOS image sensor according to an embodiment of the present invention, and FIG. 4 is a schematic cross-sectional structure of FIG. 3 along the M-N tangent direction. The formation method of the image sensor includes: : providing a substrate 100, the substrate 100 includes a plurality of unit regions V arranged along the first direction Y; forming a first photoelectric region 110, a second photoelectric region 120, and a plurality of discrete sources in the substrate 100 Drain region 130 .

The material of the substrate 100 is a semiconductor material.

In this embodiment, the material of the substrate 100 is silicon.

In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of Group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

In this embodiment, the substrate 100 includes a substrate (not shown in the figure) and a silicon epitaxial layer (not shown in the figure) on the surface of the substrate. The surface of the substrate 100 is the surface of the silicon epitaxial layer, and the The substrate 100 is doped with third ions.

In this embodiment, the first photoelectric region 110 and the second photoelectric region 120 are arranged along a second direction X, and the second direction X and the first direction Y are perpendicular to each other, and the source and drain regions 130 Located between the first photoelectric region 110 and the second photoelectric region 120 , the first photoelectric region 110 and the second photoelectric region 120 straddle the plurality of unit regions V respectively.

In this embodiment, the method for forming the first photoelectric region 110 includes: doping the substrate 100 with first ions. The conductivity types of the third ions are opposite to the conductivity types of the first ions, that is, the conductivity types of the first ions of the first photoelectric region 110 and the third ions of the substrate 100 are opposite. photodiodes, which are able to convert incident light into electrons.

In this embodiment, the method for forming the second photoelectric region 120 includes: doping the substrate 100 with first ions. The conductivity types of the third ions are opposite to those of the first ions, that is, the conductivity types of the first ions of the second photoelectric region 120 and the third ions of the substrate 100 are opposite. photodiodes, which are able to convert incident light into electrons.

In this embodiment, the first ions are N-type ions, and the third ions are P-type ions.

In other embodiments, the first ions are P-type ions, and the third ions are N-type ions. The P-type ions include boron ions or BF ²⁺ ions, and the N-type ions include phosphorus ions or arsenic ions.

In this embodiment, each of the cell regions V includes one of the source and drain regions 130 .

The method for forming the source and drain regions 130 includes: doping a first ion in a part of the substrate 100 between the first photoelectric region 110 and the second photoelectric region 120 of the cell region V.

In this embodiment, the method for forming the time delay and integration CMOS image sensor further includes: forming an isolation structure 170 in the substrate, and the isolation structure 170 is located in the first photoelectric region 110 and the second photoelectric region One or all of the regions 120 are on the opposite side of the source and drain regions 130 , and the isolation structure 170 spans the plurality of cell regions V.

In this embodiment, the method for forming the isolation structure 170 includes: forming a groove (not shown) in the substrate 100, the groove being exposed on the surface of the substrate 100; An isolation structure material layer (not shown) is formed on the surface of the substrate 100 ; the isolation structure material layer is planarized until the surface of the substrate 100 is exposed, so as to form the isolation structure 170 .

Please continue to refer to FIG. 3 and FIG. 4 , a first gate structure 140 is formed on the substrate 100 in the unit region V, and the first gate structure 140 is located on the first photoelectric region 110 ; A second gate structure 150 is formed on the substrate 100 in the cell region V, and the second gate structure 150 is located on the first photoelectric region 120; a third gate is formed on the substrate 100 in the cell region V pole structure 161, and the third gate structure 161 is located on the surface of the substrate 100 between the first photoelectric region 110 and the source and drain regions 130; a fourth gate structure is formed on the substrate 100 in the unit region V A gate structure 162 is provided, and the fourth gate structure 162 is located on the surface of the substrate 100 between the second photoelectric region 120 and the source and drain regions 130 .

In this embodiment, the first gate structure 140 includes a first gate dielectric layer (not shown in the figure) formed on the surface of the substrate 100, and a first gate dielectric layer formed on the surface of the first gate dielectric layer electrode layer.

In this embodiment, the second gate structure 150 includes a second gate dielectric layer (not shown in the figure) formed on the surface of the substrate 100 , and a second gate dielectric layer formed on the surface of the second gate dielectric layer electrode layer.

In this embodiment, the third gate structure 161 includes a third gate dielectric layer (not shown in the figure) formed on the surface of the substrate 100, and a third gate formed on the surface of the third gate dielectric layer electrode layer.

In this embodiment, the fourth gate structure 162 includes a fourth gate dielectric layer (not shown in the figure) formed on the surface of the substrate 100, and a fourth gate formed on the surface of the fourth gate dielectric layer electrode layer.

In this embodiment, a plurality of the first gate structures 140 also extend to the source and drain regions 130 between the first photoelectric region 110 and the second photoelectric region 120 in the unit region V outside the substrate 100 surface.

In another embodiment, a plurality of the first gate structures 340 (as shown in FIG. 5 ) do not extend between the first photovoltaic region 110 and the second photovoltaic region 120 in the cell region V the surface of the substrate 100 outside the source and drain regions 330 (as shown in FIG. 5 ).

In this embodiment, a plurality of the first gate structures 140 also extend to the surface of the isolation structure 170 in the cell region V. As shown in FIG.

In another embodiment, the plurality of first gate structures do not extend to the surface of the isolation structures within the cell region.

In this embodiment, a plurality of the second gate structures 150 also extend to the source and drain regions 130 between the first photoelectric region 110 and the second photoelectric region 120 in the unit region V outside the substrate 100 surface.

In another embodiment, the second gate structure 350 (as shown in FIG. 5 ) does not extend to the space between the first photovoltaic region 110 and the second photovoltaic region 120 in the cell region V , the surface of the substrate 100 outside the source and drain regions 330 (as shown in FIG. 5 ).

In this embodiment, a plurality of the second gate structures 150 also extend to the surface of the isolation structure 170 in the cell region V. As shown in FIG.

In another embodiment, the plurality of second gate structures do not extend to the surface of the isolation structures within the cell region.

In this embodiment, the method for forming the time delay integration CMOS image sensor further includes: forming a plurality of second doping regions 180 in the substrate 100 between the adjacent source and drain regions 130 , the second doping regions 180 . The regions 180 are arranged along the first direction Y, and the second doped region 180 is also located between the first photoelectric region 110 and the second photoelectric region 120 .

In another embodiment, the second doped region is not formed.

In this embodiment, the method for forming the second doped region 180 includes: doping the substrate 100 with second ions, and the conductivity type of the second ions and the conductivity type of the first ions On the contrary, the conductivity type of the second doped region 180 is made opposite to the conductivity type of the first photoelectric region 110 .

In this embodiment, the second ions are P-type ions. In other embodiments, the second ions are N-type ions. The P-type ions include boron ions or BF ²⁺ ions, and the N-type ions include phosphorus ions or arsenic ions.

In this embodiment, a plurality of the first gate structures 140 extend to the second doped regions 180 .

In this embodiment, a plurality of the second gate structures 150 extend to the second doped regions 180 .

In other embodiments, several first gate structures or several second gate structures extend over the second doped region.

Correspondingly, an embodiment of the present invention further provides a time delay integration CMOS image sensor, please refer to FIG. 3 and FIG. 4 , including: a substrate 100, the substrate 100 includes a plurality of unit regions V arranged along the first direction Y; A first photoelectric region 110, a second photoelectric region 120 and a plurality of discrete source and drain regions 130 in the substrate 100; a first gate structure 140 and a second gate on the substrate of the unit region V The pole structure 150 , the third gate structure 161 and the fourth gate structure 162 .

The material of the substrate 100 is a semiconductor material.

In this embodiment, the material of the substrate 100 is silicon.

In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of Group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

In this embodiment, the substrate 100 includes a substrate (not shown in the figure) and a silicon epitaxial layer (not shown in the figure) on the surface of the substrate. The surface of the substrate 100 is the surface of the silicon epitaxial layer, and the The substrate 100 has third ions in it.

In this embodiment, the first photoelectric region 110 and the second photoelectric region 120 are arranged along a second direction X, the second direction X and the first direction Y are perpendicular to each other, and the plurality of source and drain regions 130 is located between the first photoelectric region 110 and the second photoelectric region 120 , and the first photoelectric region 110 and the second photoelectric region 120 straddle the plurality of unit regions V respectively.

In this embodiment, there are first ions in the first photoelectric region 110 . The conductivity types of the third ions are opposite to the conductivity types of the first ions, that is, the conductivity types of the first ions of the first photoelectric region 110 and the third ions of the substrate 100 are opposite. photodiodes, which are able to convert incident light into electrons.

In this embodiment, there are first ions in the second photoelectric region 120 . The conductivity types of the third ions are opposite to those of the first ions, that is, the conductivity types of the first ions of the second photoelectric region 120 and the third ions of the substrate 100 are opposite. photodiodes, which are able to convert incident light into electrons.

In this embodiment, the first ions are N-type ions, and the third ions are P-type ions.

In other embodiments, the first ions are P-type ions, and the third ions are N-type ions. The P-type ions include boron ions or BF ²⁺ ions, and the N-type ions include phosphorus ions or arsenic ions.

In this embodiment, each of the cell regions V includes one of the source and drain regions 130 , and the source and drain regions 130 have first ions in them.

In this embodiment, the time delay integration CMOS image sensor further includes: an isolation structure 170 located in the substrate 100 , and the isolation structure 170 is located in the first photoelectric region 110 and the second photoelectric region 120 One or all of them are on the opposite side of the source and drain regions 130 , and the isolation structure 170 spans the plurality of unit regions V.

Since the isolation structure 170 is provided on the opposite side of the source and drain regions 130 in one or both of the first photoelectric region 110 and the second photoelectric region 120 , the image sensor can improve the sensitivity to the first photoelectric region 110 and the second photoelectric region 120 . A photoelectric region 110 and the isolation effect of current crosstalk and light crosstalk on the second photoelectric region 120, thereby improving the performance of the time delay integration CMOS image sensor.

In this embodiment, the first gate structure 140 includes a first gate dielectric layer (not shown in the figure) on the surface of the substrate 100 and a first gate electrode layer on the surface of the first gate dielectric layer .

In this embodiment, the second gate structure 150 includes a second gate dielectric layer (not shown in the figure) on the surface of the substrate 100 and a second gate electrode layer on the surface of the second gate dielectric layer .

In this embodiment, the third gate structure 161 includes a third gate dielectric layer (not shown in the figure) on the surface of the substrate 100 and a third gate electrode layer on the surface of the third gate dielectric layer .

In this embodiment, the fourth gate structure 162 includes a fourth gate dielectric layer (not shown in the figure) on the surface of the substrate 100 and a fourth gate electrode layer on the surface of the fourth gate dielectric layer .

In this embodiment, the first gate structure 140 is located on the first photovoltaic region 110 , the second gate structure 150 is located on the first photovoltaic region 120 , and the third gate structure 161 On the surface of the substrate 100 between the first photoelectric region 110 and the source-drain region 130 , the fourth gate structure 162 is located on the second photoelectric region 120 and the fourth gate structure 162 on the surface of the substrate 100 between the source and drain regions 130 .

Since each of the cell regions V has a first gate structure 140, a second gate structure 150, a third gate structure 161 and a fourth gate structure 162, and the third gate structure 161 is located in the The surface of the substrate 100 between the first photoelectric region 110 and the source and drain regions 130, the fourth gate structure 162 is located on the surface of the substrate 100 between the second photoelectric region 120 and the source and drain regions 130, therefore , when the channel under the third gate structure 161 is opened, the electrons that overflow after the channel under the first gate structure 161 reaches a full well, and when the channel under the fourth gate structure 162 is opened When the channel under the second gate structure 162 reaches the full well, the electrons that overflow after the channel is full can be transferred to the source and drain regions 130 in the same cell region V, so that the source and drain regions 130 can simultaneously Corresponding to the overflow electrons generated by the first photoelectric region 110 and the second photoelectric region 120, the time delay integration CMOS image sensor can reduce the number of the source and drain regions while having an anti-dispersion structure, thereby, Provide space for increasing the area of the first photoelectric region 110 and the second photoelectric region 120, that is, the pixel filling factor of the time delay integration CMOS image sensor can be increased, so that the time delay integration CMOS image sensor can obtain Higher sensitivity and dynamic range improve the performance of the time delay integrating CMOS image sensor.

Not only that, when the source-drain region 130 is electrically interconnected with the interconnection layer, electrons entering the source-drain region 130 can also be transferred from the source-drain region 130 to the electrical interconnection with the source-drain region 130 The interconnection layer is absorbed by the interconnection layer. Therefore, the source and drain regions 130 will not overflow with electrons, so that the source and drain regions 130 can always receive electrons from the first photoelectric region 110 and the The overflowed electrons in the second photoelectric region 120 improve the stability of the time delay integration CMOS image sensor, and reduce the interference of the time delay integration CMOS image sensor caused by the overflow electrons in the source and drain regions 130 .

In this embodiment, a plurality of the first gate structures 140 also extend to the source and drain regions 130 between the first photoelectric region 110 and the second photoelectric region 120 in the unit region V outside the substrate 100 surface.

Since the first gate structure 140 also extends to the surface of the substrate 100 between the first photoelectric region 110 and the second photoelectric region 120 in the cell region V and outside the source and drain regions 130, it can The photosensitive surface corresponding to the first photoelectric region 110 is increased, and the number of charges when the channel under the first gate structure 140 reaches the full well capacity is increased, thereby improving the sensitivity of the time delay integration CMOS image sensor and dynamic range to improve the performance of the time delay integrating CMOS image sensor.

In another embodiment, a plurality of the first gate structures 340 (as shown in FIG. 5 ) do not extend between the first photovoltaic region 110 and the second photovoltaic region 120 in the cell region V the surface of the substrate 100 outside the source and drain regions 330 (as shown in FIG. 5 ).

In this embodiment, a plurality of the first gate structures 140 also extend to the surface of the isolation structure 170 in the cell region V. As shown in FIG.

Since the first gate structure 140 also extends to the surface of the isolation structure 170 in the unit region V, the photosensitive surface corresponding to the first photoelectric region 110 can be further increased, and the first photoelectric region 110 can be further increased. The number of charges when the channel under the gate structure 140 reaches the full well capacity, thereby improving the sensitivity and dynamic range of the time delay integrating CMOS image sensor, so as to improve the performance of the time delay integrating CMOS image sensor.

In another embodiment, the plurality of first gate structures do not extend to the surface of the isolation structures within the cell region.

In this embodiment, a plurality of the second gate structures 150 also extend to the source and drain regions 130 between the first photoelectric region 110 and the second photoelectric region 120 in the unit region V outside the substrate 100 surface.

Since the second gate structure 150 also extends to the surface of the substrate 100 between the first photoelectric region 110 and the second photoelectric region 120 in the cell region V and outside the source and drain regions 130, it can The photosensitive surface corresponding to the second photoelectric region 120 is increased, and the number of charges when the channel under the second gate structure 150 reaches the full well capacity is increased, thereby improving the sensitivity of the time delay integration CMOS image sensor and dynamic range to improve the performance of the time delay integrating CMOS image sensor.

In another embodiment, a plurality of the second gate structures 350 (as shown in FIG. 5 ) do not extend between the first photovoltaic region 110 and the second photovoltaic region 120 in the cell region V the surface of the substrate 100 outside the source and drain regions 330 (as shown in FIG. 5 ).

In this embodiment, a plurality of the second gate structures 150 also extend to the surface of the isolation structure 170 in the cell region V. As shown in FIG.

Since the second gate structure 150 also extends to the surface of the isolation structure 170 in the unit region V, the photosensitive surface corresponding to the second photoelectric region 120 can be further increased, and the second photoelectric region 120 can be further increased. The number of charges when the channel under the gate structure 150 reaches the full well capacity, thereby improving the sensitivity and dynamic range of the time delay integration CMOS image sensor, so as to improve the performance of the time delay integration CMOS image sensor.

In another embodiment, the plurality of second gate structures do not extend to the surface of the isolation structures within the cell region.

In this embodiment, the time delay integration CMOS image sensor further includes: a plurality of second doped regions 180 in the substrate 100 between the adjacent source and drain regions 130 , the second doped regions 180 along the The first direction Y is arranged, and the second doped region 180 is also located between the first photoelectric region 110 and the second photoelectric region 120 . There are second ions in the second doped region 180, and the conductivity type of the second ions is opposite to that of the first ions, so that the conductivity type of the second doped region 180 is the same as the conductivity type of the first ions. The conductivity types of the first photoelectric regions 110 are opposite.

In another embodiment, there are no second doped regions in the substrate between adjacent source and drain regions.

In this embodiment, the second ions are P-type ions. In other embodiments, the second ions are N-type ions. The P-type ions include boron ions or BF ²⁺ ions, and the N-type ions include phosphorus ions or arsenic ions.

In this embodiment, a plurality of the first gate structures 140 extend on the second doped regions 180 .

Since the conductivity type of the second ions is opposite to the conductivity type of the first ions, and at least one of the first gate structures 140 extends to the second doping region 180, the first gate structure 140 is There is an anti-doping region between the photoelectric region 110 and the second photoelectric region 120, so that the dark current between the first photoelectric region 110 and the second photoelectric region 120 can be isolated, and the time delay integral can be improved. CMOS image sensor performance.

In this embodiment, a plurality of the second gate structures 150 extend to the second doped regions 180 .

Since the conductivity type of the second ions is opposite to that of the first ions, and at least one of the second gate structures 150 extends to the second doping region 180, the first There is an anti-doping region between the photoelectric region 110 and the second photoelectric region 120, so that the dark current between the first photoelectric region 110 and the second photoelectric region 120 can be isolated, and the time delay integral can be improved. CMOS image sensor performance.

In other embodiments, several first gate structures or several second gate structures extend over the second doped region.

In this embodiment, in a direction perpendicular to the surface of the substrate 100 , the depth of the second doping region 180 is smaller than the depth of the source and drain regions 130 .

6 to 7 are schematic structural diagrams of a time delay integration CMOS image sensor according to another embodiment of the present invention.

Please refer to FIG. 6 and FIG. 7 , FIG. 6 is a schematic top view of a time delay integration CMOS image sensor according to another embodiment of the present invention, and FIG. 7 is a cross-sectional structure diagram of FIG. 6 along the U-W tangent direction. The method for forming a CMOS image sensor includes: providing a substrate 200, the substrate 200 including a plurality of unit regions P arranged along a first direction Y; forming a first photoelectric region 210 and a second photoelectric region 220 separated from each other in the substrate 200 and source and drain regions 230 .

The material of the substrate 200 is a semiconductor material.

In this embodiment, the material of the substrate 200 is silicon.

In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of Group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

In this embodiment, the substrate 200 includes a substrate (not shown in the figure) and a silicon epitaxial layer (not shown in the figure) located on the surface of the substrate. The surface of the substrate 200 is the surface of the silicon epitaxial layer, and the The substrate 200 is doped with third ions.

In this embodiment, the first photoelectric region 210 and the second photoelectric region 220 are arranged along a second direction X, and the second direction X and the first direction Y are perpendicular to each other, and the source and drain regions 230 Located between the first photoelectric region 210 and the second photoelectric region 220 , the first photoelectric region 210 and the second photoelectric region 220 straddle the plurality of unit regions P respectively.

In this embodiment, the method for forming the first photoelectric region 210 includes: doping the substrate 200 with first ions. The conductivity types of the third ions are opposite to the conductivity types of the first ions, that is, the conductivity types of the first ions of the first photoelectric region 210 and the third ions of the substrate 200 are opposite. photodiodes, which are able to convert incident light into electrons.

In this embodiment, the method for forming the second photoelectric region 220 includes: doping the substrate 200 with first ions. The conductivity types of the third ions are opposite to those of the first ions, that is, the conductivity types of the first ions of the second photoelectric region 220 and the third ions of the substrate 200 are opposite. photodiodes, which are able to convert incident light into electrons.

In this embodiment, the first ions are N-type ions, and the third ions are P-type ions.

In other embodiments, the first ions are P-type ions, and the third ions are N-type ions. The P-type ions include boron ions or BF ²⁺ ions, and the N-type ions include phosphorus ions or arsenic ions.

In this embodiment, the method for forming the source and drain regions 230 includes: in a part of the substrate 100 between the first photoelectric region 110 and the second photoelectric region 120 and spanning the plurality of unit regions P, doping The first ions are doped, thereby forming source and drain regions 230 across the plurality of cell regions P.

In this embodiment, the method for forming the time delay integration CMOS image sensor further includes: forming an isolation structure 270 in the substrate, and the isolation structure 270 is located in the first photoelectric region 210 and the second photoelectric region One or all of the regions 220 are on the opposite side of the source and drain regions 230 , and the isolation structure 270 spans the plurality of unit regions P.

In this embodiment, the method for forming the isolation structure 270 includes: forming a groove (not shown) in the substrate 200, the groove being exposed on the surface of the substrate 200; in the groove and An isolation structure material layer (not shown) is formed on the surface of the substrate 200 ; the isolation structure material layer is planarized until the surface of the substrate 200 is exposed, so as to form the isolation structure 270 .

Please continue to refer to FIG. 6 and FIG. 7 , a first gate structure 240 is formed on the substrate 200 in the unit region P, and the first gate structure 240 is located on the first photoelectric region 210 ; The second gate structure 250 is formed on the substrate 200 in the unit region P, and the second gate structure 250 is located on the second photoelectric region 220; the third gate structure 261 is formed on the substrate 200, so The third gate structure 261 is located on the surface of the substrate 200 between the first photoelectric region 210 and the source and drain regions 230, and the third gate structure 261 spans several of the cell regions P; A fourth gate structure 262 is formed on the substrate 200, the fourth gate structure 262 is located on the surface of the substrate 200 between the second photoelectric region 220 and the source and drain regions 230, and the fourth gate The structure 262 spans several of the cell regions P.

In this embodiment, the first gate structure 240 includes a first gate dielectric layer (not shown in the figure) formed on the surface of the substrate 200, and a first gate dielectric layer formed on the surface of the first gate dielectric layer electrode layer.

In this embodiment, the second gate structure 250 includes a second gate dielectric layer (not shown in the figure) formed on the surface of the substrate 200 and a second gate dielectric layer formed on the surface of the second gate dielectric layer electrode layer.

In this embodiment, the third gate structure 261 includes a third gate dielectric layer (not shown in the figure) formed on the surface of the substrate 200, and a third gate formed on the surface of the third gate dielectric layer electrode layer.

In this embodiment, the fourth gate structure 262 includes a fourth gate dielectric layer (not shown in the figure) formed on the surface of the substrate 200, and a fourth gate formed on the surface of the fourth gate dielectric layer electrode layer.

In this embodiment, a plurality of the first gate structures 240 also extend to a portion of the third gate structure 261 in the unit region P between the projection of the surface of the substrate 200 and the first photoelectric region 210 on the surface of the substrate 200.

In another embodiment, the first gate structure does not extend to a portion of the third gate structure in the cell region on the substrate surface between the projection of the substrate surface and the first photovoltaic region.

In this embodiment, a plurality of the first gate structures 240 also extend to the surface of the isolation structure 270 in the cell region P. As shown in FIG.

In another embodiment, the plurality of first gate structures do not extend to the surface of the isolation structures within the cell region.

In this embodiment, a plurality of the second gate structures 250 also extend to a portion of the fourth gate structure 262 in the unit region P between the projection of the surface of the substrate 200 and the second photoelectric region 220 on the surface of the substrate 200.

In another embodiment, the plurality of second gate structures do not extend to a portion of the fourth gate structure in the cell region on the substrate surface between the projection of the substrate surface and the second photovoltaic region.

In this embodiment, a plurality of the second gate structures 250 also extend to the surface of the isolation structure 270 in the cell region P.

In another embodiment, the plurality of second gate structures do not extend to the surface of the isolation structures within the cell region.

Correspondingly, another embodiment of the present invention further provides a time delay integration CMOS image sensor, please refer to FIG. 6 to FIG. 7 , including: a substrate 200 , the substrate 200 includes a plurality of unit regions P arranged along the first direction Y ; the first photoelectric region 210, the second photoelectric region 220 and the source and drain regions 230 which are separated from each other in the substrate 200; the first gate structure 240, the second gate structure 240, the second The gate structure 250, the third gate structure 261 located on the surface of the substrate 200 between the first photoelectric region 210 and the source and drain regions 230, and the second photoelectric region 220 and the source and drain regions 230 The fourth gate structure 262 between the surface of the substrate 200 .

The material of the substrate 200 is a semiconductor material.

In this embodiment, the material of the substrate 200 is silicon.

In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of Group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

In this embodiment, the substrate 200 includes a substrate (not shown in the figure) and a silicon epitaxial layer (not shown in the figure) located on the surface of the substrate. The surface of the substrate 200 is the surface of the silicon epitaxial layer, and the The substrate 200 has third ions in it.

In this embodiment, the first photoelectric region 210 and the second photoelectric region 220 are arranged along a second direction X, and the second direction X and the first direction Y are perpendicular to each other, and the source and drain regions 230 Located between the first photoelectric region 210 and the second photoelectric region 220, the first photoelectric region 210, the second photoelectric region 220 and the source-drain region 230 span the plurality of unit regions P respectively .

In this embodiment, there are first ions in the first photoelectric region 210 . The conductivity types of the third ions are opposite to those of the first ions, that is, the conductivity types of the first ions of the first photoelectric region 210 and the third ions of the substrate 200 are opposite. photodiodes, which are able to convert incident light into electrons.

In this embodiment, there are first ions in the second photoelectric region 220 . The conductivity types of the third ions are opposite to those of the first ions, that is, the conductivity types of the first ions of the second photoelectric region 220 and the third ions of the substrate 200 are opposite. photodiodes, which are able to convert incident light into electrons.

In this embodiment, there are first ions in the source and drain regions 230 .

In this embodiment, the first ions are N-type ions, and the third ions are P-type ions.

In other embodiments, the first ions are P-type ions, and the third ions are N-type ions. The P-type ions include boron ions or BF ²⁺ ions, and the N-type ions include phosphorus ions or arsenic ions.

In this embodiment, the time delay integration CMOS image sensor further includes: an isolation structure 270 located in the substrate, and the isolation structure 270 is located in the first photoelectric region 210 and the second photoelectric region 220 One or all of the sides are opposite to the source and drain regions 230 , and the isolation structure 270 spans the plurality of cell regions P. As shown in FIG.

Since one or both of the first photoelectric region 210 and the second photoelectric region 220 has the isolation structure 270 on the side opposite to the source and drain regions 230 , the image sensor can improve the sensitivity of the first photoelectric region 210 and the second photoelectric region 220 A photoelectric region 210 and the isolation effect on the current crosstalk and light crosstalk of the second photoelectric region 220, thereby improving the performance of the time delay integration CMOS image sensor.

In this embodiment, the first gate structure 240 includes a first gate dielectric layer (not shown in the figure) on the surface of the substrate 200 and a first gate electrode layer on the surface of the first gate dielectric layer .

In this embodiment, the second gate structure 250 includes a second gate dielectric layer (not shown in the figure) located on the surface of the substrate 200, and a second gate electrode layer located on the surface of the second gate dielectric layer .

In this embodiment, the third gate structure 261 includes a third gate dielectric layer (not shown in the figure) on the surface of the substrate 200 and a third gate electrode layer on the surface of the third gate dielectric layer .

In this embodiment, the fourth gate structure 262 includes a fourth gate dielectric layer (not shown in the figure) on the surface of the substrate 200, and a fourth gate electrode layer on the surface of the fourth gate dielectric layer .

In this embodiment, the first gate structure 240 is located on the first photovoltaic region 210 , the second gate structure 250 is located on the second photovoltaic region 220 , and the third gate structure 261 Located on the surface of the substrate 100 between the first photoelectric region 210 and the source-drain region 230, and the third gate structure 261 spans a plurality of the cell regions P, the fourth gate structure 262 is located at On the surface of the substrate 200 between the second photoelectric region 220 and the source and drain regions 230 , the fourth gate structure 262 spans several of the cell regions P.

Since each of the unit regions P has a first gate structure 240 and a second gate structure 250 , the third gate structure 261 is located between the first photoelectric region 210 and the source and drain regions 230 . The surface of the substrate 200, the fourth gate structure 262 is located on the surface of the substrate 200 between the second photoelectric region 220 and the source and drain regions 230, and each of the cell regions P has a part of the third gate Therefore, when the channel under the third gate structure 261 is opened, the channel under the first gate structure 261 overflows after reaching the full well. Electrons, and when the channel under the fourth gate structure 262 is opened, the electrons overflowing after the channel under the second gate structure 262 reaches a full well can be transferred into the source and drain regions 230 . Therefore, the source and drain regions 230 can correspond to the overflow electrons generated by the first photoelectric region 210 and the second photoelectric region 220 at the same time, so that the time delay integration CMOS image sensor has an anti-dispersion structure and can reduce the The number of the source and drain regions provides space for increasing the area of the first photoelectric region 210 and the second photoelectric region 220, that is, the pixel fill factor of the time delay integration CMOS image sensor can be increased, so that the The time delay integration CMOS image sensor obtains higher sensitivity and dynamic range, and improves the performance of the time delay integration CMOS image sensor.

Not only that, when the source-drain region 230 is electrically interconnected with the interconnect layer, electrons entering the source-drain region 230 can also be transferred from the source-drain region 230 to the electrical interconnection with the source-drain region 230 The interconnection layer is absorbed by the interconnection layer. Therefore, the source-drain region 230 will not overflow with electrons, so that the source-drain region 230 can always receive electrons from the first photoelectric region 210 and the The overflow electrons in the second photoelectric region 220 improve the stability of the time delay integration CMOS image sensor, and reduce the interference of the time delay integration CMOS image sensor caused by the overflow electrons in the source and drain regions 230 .

In this embodiment, a plurality of the first gate structures 240 also extend to a portion of the third gate structure 261 in the unit region P between the projection of the surface of the substrate 200 and the first photoelectric region 210 on the surface of the substrate 200.

Since the first gate structure 240 also extends to the part of the third gate structure 261 in the unit region P on the surface of the substrate 200 between the projection of the surface of the substrate 200 and the first photoelectric region 210 , Therefore, the photosensitive surface corresponding to the first photoelectric region 210 can be increased, and the number of charges when the channel under the first gate structure 240 reaches the full well capacity can be increased, thereby improving the time delay integration CMOS image sensor The sensitivity and dynamic range to improve the performance of the time delay integral CMOS image sensor.

In another embodiment, the first gate structure does not extend to a portion of the third gate structure in the cell region on the substrate surface between the projection of the substrate surface and the first photovoltaic region.

In this embodiment, a plurality of the first gate structures 240 also extend to the surface of the isolation structure 270 in the cell region P. As shown in FIG.

Since the first gate structure 240 also extends to the surface of the isolation structure 270 in the unit region P, the photosensitive surface corresponding to the first photoelectric region 210 can be further increased, and the first photoelectric region 210 can be further increased. The number of charges when the channel under the gate structure 240 reaches the full well capacity, thereby improving the sensitivity and dynamic range of the time delay integration CMOS image sensor, so as to improve the performance of the time delay integration CMOS image sensor.

In another embodiment, the plurality of first gate structures do not extend to the surface of the isolation structures within the cell region.

In this embodiment, a plurality of the second gate structures 250 also extend to a portion of the fourth gate structure 262 in the unit region P between the projection of the surface of the substrate 200 and the second photoelectric region 220 on the surface of the substrate 200.

Since the second gate structure 250 also extends to the part of the fourth gate structure 262 in the unit region P on the surface of the substrate 200 between the projection of the surface of the substrate 200 and the second photoelectric region 220, Therefore, the photosensitive surface corresponding to the second photoelectric region 220 can be increased, and the number of charges when the channel under the second gate structure 250 reaches the full well capacity can be increased, thereby improving the time delay integration CMOS image sensor The sensitivity and dynamic range to improve the performance of the time delay integrating CMOS image sensor.

In another embodiment, the plurality of second gate structures 450 do not extend to a portion of the fourth gate structure in the cell region on the substrate surface between the projection of the substrate surface and the second photovoltaic region.

In this embodiment, a plurality of the second gate structures 250 also extend to the surface of the isolation structure 270 in the cell region P.

Since the second gate structure 250 also extends to the surface of the isolation structure 270 in the unit region P, the photosensitive surface corresponding to the second photoelectric region 220 can be further increased, and the second photoelectric region 220 can be further increased. The number of charges when the channel under the gate structure 250 reaches the full well capacity, thereby improving the sensitivity and dynamic range of the time delay integrating CMOS image sensor, so as to improve the performance of the time delay integrating CMOS image sensor.

In another embodiment, the plurality of second gate structures do not extend to the surface of the isolation structures within the cell region.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (12)

1. A time delay integrated CMOS image sensor, comprising:

the substrate comprises a plurality of unit areas arranged along a first direction;

the first photoelectric region, the second photoelectric region and the source drain region are separated from each other and located in the substrate, the first photoelectric region and the second photoelectric region are arranged along a second direction, the second direction is perpendicular to the first direction, the source drain region is located between the first photoelectric region and the second photoelectric region, and the first photoelectric region and the second photoelectric region respectively cross the plurality of unit regions;

a first gate structure on the substrate in the cell region, the first gate structure being on the first photovoltaic region;

a second gate structure on the substrate in the cell region, the second gate structure on the second photovoltaic region;

a third gate structure, wherein part or all of the third gate structure is located on the substrate in the cell region, and the third gate structure is located on the surface of the substrate between the first photovoltaic region and the source/drain region;

and part or all of the fourth gate structure is positioned on the substrate in the unit region, and the fourth gate structure is positioned on the surface of the substrate between the second photoelectric region and the source-drain region.

2. The time delay integrated CMOS image sensor of claim 1, wherein at least one third gate structure and at least one fourth gate structure are located on a substrate surface of the cell region, and at least 1 of the source drain regions are located within the cell region.

3. The time delay integrated CMOS image sensor of claim 2, wherein the first photo-electric region has first ions therein, the second photo-electric region has first ions therein, and the source and drain regions also have first ions therein.

4. The time delay integrated CMOS image sensor of claim 3, wherein the first gate structure further extends to a substrate surface outside the source drain regions between the first and second photo-electric regions within the cell region.

5. The time delay integrated CMOS image sensor of claim 3 or 4, wherein the second gate structure further extends to a substrate surface outside the source drain regions between the first photovoltaic region and the second photovoltaic region within the cell region.

6. The time delay integrated CMOS image sensor of claim 4, further comprising: the second doped regions are arranged in the substrate between the adjacent source and drain regions, second ions are arranged in the second doped regions, the conductivity type of the second ions is opposite to that of the first ions, the second doped regions are arranged along the first direction, and the first grid structure extends to the second doped regions.

7. The time delay integrated CMOS image sensor of claim 5, further comprising: the second doped regions are arranged in the substrate between the adjacent source and drain regions, second ions are arranged in the second doped regions, the conductivity type of the second ions is opposite to that of the first ions, the second doped regions are arranged along the first direction, and the second grid structures extend onto the second doped regions.

8. The time delay integrated CMOS image sensor of claim 1, wherein the number of the source drain regions, the third gate structures, and the fourth gate structures is 1, and the source drain regions, the third gate structures, and the fourth gate structures all span the plurality of cell regions.

9. The time delay integrated CMOS image sensor of claim 8, wherein the first gate structure further extends to a substrate surface between a projection of the third gate structure onto the substrate surface and the first photovoltaic region.

10. The time delay integrated CMOS image sensor of claim 8, wherein the second gate structure further extends to the substrate surface between a projection of the fourth gate structure onto the substrate surface and the second photovoltaic region.

11. The time delay integrated CMOS image sensor of claim 1, further comprising more than 1 isolation structure in the substrate, the isolation structure being located on a side of one or both of the first and second photovoltaic regions opposite the source and drain regions.

12. A method of forming a time delay integrated CMOS image sensor as claimed in any one of claims 1 to 11.

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