CN110661687B

CN110661687B - Full-communication double-bus exchange platform

Info

Publication number: CN110661687B
Application number: CN201910747482.XA
Authority: CN
Inventors: 吴军; 储开华; 张剑锋; 杨鹏飞
Original assignee: Panda Electronics Group Co Ltd; Nanjing Panda Handa Technology Co Ltd
Current assignee: Nanjing Panda Handa Technology Co Ltd
Priority date: 2019-08-14
Filing date: 2019-08-14
Publication date: 2021-11-05
Anticipated expiration: 2039-08-14
Also published as: CN110661687A

Abstract

The invention discloses a full-communication double-bus exchange platform, which comprises more than one transceiving channel module, more than one baseband processing module, a bus exchange module, a user interface module and a 125M clock.

Description

Full-communication double-bus exchange platform

Technical Field

The invention relates to a full-communication double-bus exchange platform, belonging to the technical field of electronics.

Background

Bus exchange is a key technology of a multifunctional integrated communication system, and plays an important role in improving data transmission capability of a digital processing platform. The traditional communication platform adopts a PCI bus, an Ethernet bus or a RapidIO bus, and the single bus design exchange easily causes the preemption of the control data and the high-speed baseband data of the communication system on the bus, thereby causing large data delay and packet loss and reducing the system reliability. With the development of a comprehensive integrated communication system, the system has higher and higher requirements on data exchange capacity in a multifunctional multi-module digital processing platform, and the existing single-bus design cannot well support point-to-point and point-to-many high-bandwidth and low-delay data communication among multiple modules in the platform.

Disclosure of Invention

The purpose of the invention is as follows: in order to overcome the defects in the prior art, the invention provides a full-communication dual-bus exchange platform, which adopts a mainstream high-speed serial bus gigabit Ethernet and a RapidIO bus, is compatible with the advantages of an Ethernet interface, convenience for expansion, external control, high speed and low time delay of the RapidIO interface, provides the Ethernet and the RapidIO interface for each communication module in a digital processing platform, and improves the digital signal processing capability of the system. The exchange platform is suitable for vehicle-mounted, ship-mounted, no-load and other embedded integrated communication systems.

The technical scheme is as follows: in order to achieve the purpose, the invention adopts the technical scheme that:

a full-communication double-bus exchange platform comprises more than one transceiving channel module, more than one baseband processing module, a bus exchange module, a user interface module and a 125M clock, wherein the transceiving channel module, the baseband processing module, the bus exchange module and the user interface module are all provided with an Ethernet interface and a RapidIO interface, and the 125M clock is respectively connected with the transceiving channel module, the baseband processing module, the bus exchange module and the user interface module to provide a unified reference clock; the bus exchange module is respectively connected with the transceiving channel module, the baseband processing module and the user interface module through an Ethernet interface and a RapidIO interface, low-speed control signals are transmitted through the Ethernet interface, high-speed baseband data signals are transmitted through the RapidIO interface, the bus exchange module comprises a CPLD singlechip and an AVR singlechip, the CPLD singlechip is used for completing low-speed control signal exchange configuration of the Ethernet interface, and the AVR singlechip is used for completing high-speed baseband data signal exchange configuration of the RapidIO interface.

Further: the power module is respectively connected with the transceiving channel module, the baseband processing module, the bus exchange module and the user interface module.

Further: the CPLD singlechip is connected with a BCM55680 Ethernet switch.

Further: the CPLD single chip microcomputer is connected with an ISL6123 chip and a Tsi578 chip, the ISL6123 chip is connected with the Tsi578 chip, a P _ CLK of the Tsi578 chip is used as an internal register and an I2C interface clock, the frequency is single-ended 100MHz, an S _ CLK _ P/N of the Tsi578 chip is used as a reference clock of an SERDES, and the frequency is differential 156.25 MHz.

Compared with the prior art, the invention has the following beneficial effects:

the invention provides Ethernet and RapidIO interfaces for each module, respectively provides a control data channel and a high-speed baseband signal data channel, greatly improves the data processing bandwidth in the system, reduces the system delay, improves the system reliability, supports the point-to-point and point-to-many data communication with high bandwidth and low delay among multiple modules in the platform, and can effectively improve the communication and data processing capacity of the comprehensive communication system. The method is suitable for vehicle-mounted, ship-mounted and no-load embedded integrated communication systems, and provides high-speed serial bus exchange with high bandwidth and low time delay for the systems. All modules in the system can realize point-to-point and point-to-many full interconnection communication through Ethernet and RapidIO interfaces, and the method has important significance for the development of a new generation of embedded integrated communication system.

Drawings

FIG. 1 is a schematic diagram of an Ethernet bus switch;

FIG. 2 is a schematic diagram of PCI bus switching

FIG. 3 is a schematic diagram of a fully-connected dual-bus switch platform

FIG. 4 is a diagram of an 8-way gigabit Ethernet switch

FIG. 5 is a 16-way 1X 1.25G data exchange

FIG. 6 is a schematic diagram of reference clocks for three transmission rates

FIG. 7 is a block diagram of a reference clock application

Detailed Description

The present invention is further illustrated by the following description in conjunction with the accompanying drawings and the specific embodiments, it is to be understood that these examples are given solely for the purpose of illustration and are not intended as a definition of the limits of the invention, since various equivalent modifications will occur to those skilled in the art upon reading the present invention and fall within the limits of the appended claims.

The conventional integrated communication system bus switching platform generally includes ethernet bus switching (fig. 1) and PCI bus switching (fig. 2), and a fully-connected dual-bus switching platform of the present invention, as shown in fig. 3, includes more than one transceiving channel module, more than one baseband processing module, a bus switching module, a user interface module, a 125M clock, and a power supply module, where the power supply module is connected to the transceiving channel module, the baseband processing module, the bus switching module, and the user interface module, respectively. The receiving and transmitting channel module, the baseband processing module, the bus switching module and the user interface module are all provided with an Ethernet interface and a RapidIO interface, and the 125M clock is respectively connected with the receiving and transmitting channel module, the baseband processing module, the bus switching module and the user interface module and provides a unified reference clock; the bus exchange module is respectively connected with the transceiving channel module, the baseband processing module and the user interface module through an Ethernet interface and a RapidIO interface, low-speed control signals are transmitted through the Ethernet interface, high-speed baseband data signals are transmitted through the RapidIO interface, the bus exchange module comprises a CPLD singlechip and an AVR singlechip, the CPLD singlechip is used for completing low-speed control signal exchange configuration of the Ethernet interface, and the AVR singlechip is used for completing high-speed baseband data signal exchange configuration of the RapidIO interface. By providing an Ethernet interface and a RapidIO interface for each module in the system and respectively providing a control data channel and a high-speed baseband signal data channel, the data processing bandwidth in the system is greatly improved, the system delay is reduced, and the system reliability is improved. The bus exchange module completes the exchange of control data and baseband data among all modules in the integrated communication system. Wherein, the Ethernet bus completes the low-speed control signal exchange, and RapidIO completes the high-speed baseband data signal exchange. The bus exchange platform is configured by adopting a CPLD and an AVR singlechip to respectively configure the Ethernet exchange chip and the RapidIO exchange chip.

As shown in fig. 4, the ethernet switch employs a BCM55680 ethernet switch, which can provide 8-way gigabit ethernet switches.

RapidIO switching using Tsi578, as shown in FIG. 5, provides up to 16 way 1X 1.25G data switching capability, as shown in FIG. 6, where P _ CLK is a single ended 100MHz as the internal register and I2C interface clock. The S _ CLK _ P/N is used as a reference clock of the SERDES, is differential at 156.25MHz, and can adapt to three transmission rates of 1.25Gbps, 2.5Gbps and 3.125 Gbps.

As shown in fig. 7, a unified 125M clock is used inside the switching bus platform to provide a unified reference clock for each communication module.

The invention provides a high-bandwidth and low-delay data transmission channel between the communication modules in the digital processing platform, and can effectively improve the processing capability and reliability of the comprehensive communication system.

The above description is only of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and these are intended to be within the scope of the invention.

Claims

1. A full-communication double-bus exchange platform is characterized in that: the system comprises more than one transceiving channel module, more than one baseband processing module, a bus exchange module, a user interface module and a 125M clock, wherein the transceiving channel module, the baseband processing module, the bus exchange module and the user interface module are all provided with an Ethernet interface and a RapidIO interface, and the 125M clock is respectively connected with the transceiving channel module, the baseband processing module, the bus exchange module and the user interface module and provides a unified reference clock; the bus exchange module is respectively connected with the transceiving channel module, the baseband processing module and the user interface module through an Ethernet interface and a RapidIO interface, low-speed control signals are transmitted through the Ethernet interface, high-speed baseband data signals are transmitted through the RapidIO interface, the bus exchange module comprises a CPLD singlechip and an AVR singlechip, the CPLD singlechip is used for completing low-speed control signal exchange configuration of the Ethernet interface, and the AVR singlechip is used for completing high-speed baseband data signal exchange configuration of the RapidIO interface.

2. The all-inclusive dual-bus switching platform according to claim 1, wherein: the power module is respectively connected with the transceiving channel module, the baseband processing module, the bus exchange module and the user interface module.

3. The all-in-one dual-bus switching platform according to claim 2, wherein: the CPLD singlechip is connected with a BCM55680 Ethernet switch.

4. The all-in-one dual-bus switching platform according to claim 3, wherein: the CPLD single chip microcomputer is connected with an ISL6123 chip and a Tsi578 chip, the ISL6123 chip is connected with the Tsi578 chip, a P _ CLK of the Tsi578 chip is used as an internal register and an I2C interface clock, the frequency is single-ended 100MHz, an S _ CLK _ P/N of the Tsi578 chip is used as a reference clock of an SERDES, and the frequency is differential 156.25 MHz.