CN108563399B - Data reading method and device of storage device, terminal device and storage medium - Google Patents

Abstract

The invention relates to the technical field of storage equipment, and provides a data reading method and device of the storage equipment, terminal equipment and a computer storage medium. The data reading method comprises the following steps: acquiring a plurality of data reading commands issued by an upper computer; analyzing the data reading commands to respectively obtain a physical address corresponding to each data reading command, wherein the physical address comprises a flash chip selection address and a storage unit address; and submitting the data reading command to a flash controller according to the sequence of traversing the chip selection address firstly and then traversing the storage unit address, so that the controller sequentially executes the received data reading command. According to the invention, the data reading commands are sequenced according to the sequence of traversing the chip selection address firstly and then traversing the storage unit address, so that each chip selection storage area of the flash can start data preparation work in time, and the data reading efficiency of the storage device is obviously improved.

Description

Data reading method, device, terminal device and storage medium of storage device

technical field

The present invention relates to the technical field of storage devices, and in particular, to a data reading method, device, terminal device and computer storage medium of a storage device.

Background technique

In the current storage devices such as SSD, the storage chip generally uses flash. When reading data, because the flash reading data is an asynchronous operation process, that is, the host computer first sends a data read command to the flash, and then needs to wait for the flash to read data. The host computer can start to receive data when the data is ready. In view of this feature, the interleaving technology is usually used to improve the reading efficiency of data, that is, the interleaving technology is used between multiple channels of the flash and multiple chip selection storage areas to offset the data preparation time of the flash. .

However, since the addresses of the storage units corresponding to a series of data read commands sent by the host computer are randomly out of order, it is very likely that multiple consecutive data read commands will act on the same chip selection storage area of the flash, which leads to Other chip selection storage areas of the flash cannot start data preparation work in time, resulting in a waste of time resources. Therefore, using the traditional interleaving technology has little effect on improving the data reading efficiency of the storage device.

SUMMARY OF THE INVENTION

In view of this, the embodiments of the present invention provide a data reading method, apparatus, terminal device and computer storage medium for a storage device, which can significantly improve the data reading efficiency of the storage device.

A first aspect of the embodiments of the present invention provides a method for reading data from a storage device, including:

Obtain multiple data read commands issued by the host computer;

Analyzing the plurality of data read commands to obtain a physical address corresponding to each of the data read commands, where the physical addresses include a chip selection address and a storage unit address of the flash;

Submit the data read command to the controller of the flash according to the sequence of traversing the chip select address first and then the memory unit address, so that the controller executes the received data read in sequence Order.

A second aspect of the embodiments of the present invention provides a data reading apparatus of a storage device, including:

The data read command acquisition module is used to acquire multiple data read commands issued by the host computer;

The data read command parsing module is used to analyze the multiple data read commands, and obtain the physical addresses corresponding to each of the data read commands respectively, and the physical addresses include the chip selection address and storage unit address of the flash. ;

a data read command submission module, configured to submit the data read command to the controller of the flash in the order of traversing the chip select address first and then the memory unit address, so that the controller can sequentially The received data read command is executed.

A third aspect of the embodiments of the present invention provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, when the processor executes the computer program The steps of implementing the data reading method of the storage device provided by the first aspect of the embodiments of the present invention.

A fourth aspect of the embodiments of the present invention provides a computer-readable storage medium, where the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the implementation as provided in the first aspect of the embodiments of the present invention The steps of a data reading method of a storage device.

The data reading method of the storage device provided by the embodiment of the present invention includes: acquiring multiple data reading commands issued by a host computer; analyzing the multiple data reading commands to obtain each data reading command respectively The corresponding physical address, the physical address includes the chip selection address and storage unit address of the flash; submit the data read command to the flash in the order of traversing the chip selection address first and then traversing the storage unit address The controller, so that the controller sequentially executes the received data read commands. In the above process, by sorting the data read commands issued by the host computer in the order of traversing the chip select address first and then traversing the memory unit address, it can ensure that the adjacent data read commands after the sorting act on different chip select storage areas of the flash respectively. , so that each chip selection storage area of the flash can start the data preparation work in time. Through this setting, when a certain chip selection storage area is transmitting data, other chip selection storage areas are preparing data; when the chip selection storage area has finished transmitting data, the data preparation work of other chip selection storage areas is basically completed, and it is possible to Start to transmit data, thereby effectively avoiding the waste of time resources, and significantly improving the data reading efficiency of the storage device.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only for the present invention. In some embodiments, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without any creative effort.

1 is a flowchart of a first embodiment of a method for reading data from a storage device provided by an embodiment of the present invention;

2 is a flowchart of a second embodiment of a method for reading data from a storage device provided by an embodiment of the present invention;

3 is a flowchart of a third embodiment of a method for reading data from a storage device provided by an embodiment of the present invention;

4 is a structural diagram of an embodiment of a data reading apparatus of a storage device provided by an embodiment of the present invention;

FIG. 5 is a schematic diagram of a terminal device according to an embodiment of the present invention.

Detailed ways

In the following description, for the purpose of illustration rather than limitation, specific details such as specific system structures and technologies are set forth in order to provide a thorough understanding of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

The embodiments of the present invention provide a data reading method, apparatus, terminal device and computer storage medium for a storage device, which can significantly improve the data reading efficiency of the storage device.

Referring to FIG. 1, a first embodiment of a data reading method of a storage device in an embodiment of the present invention includes:

101. Obtain multiple data read commands issued by the host computer;

In this embodiment of the present invention, the storage device refers to various storage devices including a flash storage device, such as an SSD. After the host computer sends data read commands to the storage device, the main control chip of the storage device can obtain these data read commands, and submit these data read commands to the flash chip of the storage device to read the flash. data stored in the chip.

102. Analyze the plurality of data read commands to obtain a physical address corresponding to each of the data read commands, where the physical addresses include a chip selection address and a storage unit address of the flash;

After obtaining a plurality of data read commands issued by the host computer, the main control chip of the storage device parses these data read commands, and obtains the physical address corresponding to each data read command. Including the chip select address and storage unit address of the flash. The flash of a storage device is generally divided into multiple channels, each channel includes multiple chip selection storage areas, and each chip selection storage area includes multiple storage units. Each data read command will point to a certain storage unit, and the logical address in the data read command can be converted to the physical address of the flash by looking up the mapping table. After the main control chip parses the data read command issued by the host computer, the data read command containing the physical address information obtained by the analysis can be called a flash command.

103. Submit the data read command to the controller of the flash according to the sequence of traversing the chip selection address first and then traversing the memory unit address, so that the controller executes the received data in sequence read command.

After obtaining the physical address corresponding to each data read command, submit the data read command (ie each flash command) to the the controller of the flash, so that the controller executes the received data read commands in sequence. It should be pointed out that this embodiment is mainly aimed at a series of data read commands whose physical addresses point to the same channel of the flash.

The traditional way of reading data from storage devices is: the main control chip submits the obtained data read command to the flash controller, and the flash controller executes the received data read commands in sequence, that is, the sequence of flash execution commands and the upper The sequence of commands issued by the machine is the same.

In this embodiment, after the commands issued by the host computer are obtained, the order will be re-ordered, that is, the data read command will be submitted to the In the flash controller, the order in which the flash executes the commands is the sorted order. Assuming that the main control chip obtains 10 data read commands in turn, namely A, B, C, D, E, F, G, H, I and J, the physical addresses of these commands all point to the same channel of the flash. The channel includes a total of four chip selection storage areas CE0, CE1, CE2 and CE3, and each chip selection storage area includes a total of 8 storage units from die0 to die7. Where A corresponds to CE0-die3, B corresponds to CE3-die0, C corresponds to CE0-die1, D corresponds to CE1-die0, E corresponds to CE2-die2, F corresponds to CE1-die1, G corresponds to CE3-die6, H corresponds to CE2-die3, I corresponds to CE1-die5, and J corresponds to CE2-die0. In the sorting process, first traverse the chip select addresses CE0 to CE3, and then traverse the memory cell addresses die0 to die7, that is, according to the physical addresses CE0-die0, CE1-die0, CE2-die0, CE3-die0, CE0-die1, CE1-die1 , CE2-die1, CE3-die1, CE0-die2... in order. In addition, if there is a data read command corresponding to a die that is empty in the process of traversing CE0 to CE3, the data read command corresponding to the next die of the CE is extracted in sequence. For example, if CE2-die0 is empty, then Sort in the order of CE0-die0, CE1-die0, CE2-die1, CE3-die0, CE0-die1, CE1-die1, CE2-die2, CE3-die1, CE0-die2…. According to this rule, the above commands A, B, C, D, E, F, G, H, I and J are sorted as: C, D, J, B, A, F, E, G, I and H .

A channel of flash can only transmit data of one chip selection storage area at the same time, and data preparation work can be performed simultaneously between each chip selection storage area. When the flash executes a data read command corresponding to any storage unit in a chip selection storage area, the chip selection storage area starts data preparation work. It can be seen that the data read commands issued by the host computer are sorted according to the above rules and then executed, which can ensure that each chip selection storage area of the flash can start the data preparation work in time, so that when the current chip selection storage area transmits data, the later A chip selection storage area is preparing data; when the data transmission of the previous chip selection storage area is completed, the data preparation work of the next chip selection storage area is basically completed, and data transmission can be performed directly, thereby significantly improving the data reading efficiency.

The data reading method of the storage device provided by the embodiment of the present invention includes: acquiring multiple data reading commands issued by a host computer; analyzing the multiple data reading commands to obtain each data reading command respectively The corresponding physical address, the physical address includes the chip selection address and storage unit address of the flash; submit the data read command to the flash in the order of traversing the chip selection address first and then traversing the storage unit address The controller, so that the controller sequentially executes the received data read commands. In the above process, by sorting the data read commands issued by the host computer in the order of traversing the chip select address first and then traversing the memory unit address, it can ensure that the adjacent data read commands after the sorting act on different chip select storage areas of the flash respectively. , so that each chip selection storage area of the flash can start the data preparation work in time. Through this setting, when a certain chip selection storage area is transmitting data, other chip selection storage areas are preparing data; when the chip selection storage area finishes transmitting data, the data preparation work of other chip selection storage areas is basically completed. Data transmission can be started, thereby effectively avoiding the waste of time resources, and significantly improving the data reading efficiency of the storage device.

Referring to FIG. 2, a second embodiment of a method for reading data from a storage device in an embodiment of the present invention includes:

201. Obtain multiple data read commands issued by the host computer;

Step 201 is the same as step 101 , for details, please refer to the relevant description of step 101 .

202. Analyze the plurality of data read commands, and obtain the physical addresses corresponding to each of the data read commands, respectively, where the physical addresses include a channel address, a chip selection address, and a storage unit address of the flash;

The difference between step 202 and step 102 is that the physical address corresponding to the data read command obtained by parsing also includes the channel address of the flash.

203. Submit the data read command to the controller of the flash according to the sequence of first traversing the channel address, then traversing the chip selection address, and finally traversing the memory unit address, so that the controller sequentially The received data read command is executed.

In this embodiment, a series of data read commands whose physical addresses point to each channel of the flash will be reordered after the commands issued by the host computer are obtained, that is, the channel addresses are first traversed, then the chip selection addresses are traversed, and finally The data read command is submitted to the controller of the flash by traversing the order of the addresses of the storage units, and the order in which the flash executes the commands is the sorted order. Suppose the flash has 4 channels, namely ch0, ch1, ch2 and ch3, each channel includes four chip selection storage areas CE0, CE1, CE2 and CE3, and each chip selection storage area includes 8 die0 to die7 respectively. storage unit. In the sorting process, first traverse the channel addresses ch0 to ch3, then traverse the chip select addresses CE0 to CE3, and finally traverse the memory cell addresses die0 to die7, that is, according to the physical addresses ch0-CE0-die0, ch1-CE0-die0, ch2-CE0 -die0, ch3-CE0-die0, ch0-CE1-die0, ch1-CE1-die0, ch2-CE1-die0, ch3-CE1-die0, ch0-CE2-die0, ch1-CE2-die0, ch2-CE2-die0 , ch3-CE2-die0...ch3-CE3-die0, ch0-CE0-die1, ch1-CE0-die1, ch2-CE0-die1, ch3-CE0-die1, ch0-CE1-die1... in order. In addition, if there is a data read command corresponding to a CE that is empty in the process of traversing ch0 to ch3, then extract the data read command corresponding to the next CE of the corresponding channel in order. If in the process of traversing CE0 to CE3 If the data read command corresponding to a certain die is empty, the data read command corresponding to the next die of the CE is sequentially extracted. For example, if the data read command corresponding to ch2-CE0 is empty (that is, ch2-CE0-die0, ch2-CE0-die1...ch2-CE0-die7 are all empty), according to ch0-CE0-die0, ch1-CE0- The order of die0, ch2-CE1-die0, ch3-CE0-die0, ch0-CE1-die0... .

Each channel of the flash works independently, that is, it can transmit data at the same time, but one channel can only transmit the data of one chip selection storage area at the same time, and data preparation work can be performed between each chip selection storage area at the same time. It can be seen that the data read commands issued by the main control chip are sorted according to the above rules and then executed, which can ensure that each channel of the flash can start the data transmission work in time, and the chip selection storage area of each channel can start the data preparation work in time. Specifically, for flash, each channel can start data transmission work in time, and for any channel of flash, when the current chip selection storage area is transmitting data, the next chip selection storage area is preparing data; the current one When the data transmission in the chip selection storage area is completed, the data preparation for the next chip selection storage area is basically completed, and data transmission can be performed directly, thereby significantly improving the data reading efficiency.

The data reading method of the storage device provided by the embodiment of the present invention includes: acquiring multiple data reading commands issued by a host computer; analyzing the multiple data reading commands to obtain each data reading command respectively Corresponding physical address, the physical address includes the channel address, chip selection address and storage unit address of the flash; according to the sequence of first traversing the channel address, then traversing the chip selection address, and finally traversing the storage unit address The data read command is submitted to the controller of the flash, so that the controller sequentially executes the received data read command. Using the data reading method of this embodiment can ensure that each channel of the flash starts data transmission work in time, and the chip selection storage area of each channel can start data preparation work in time, which greatly improves the data reading efficiency of multi-channel flash.

Referring to FIG. 3 , a third embodiment of a method for reading data from a storage device in an embodiment of the present invention includes:

301. Obtain multiple data read commands issued by the host computer;

302. Parse the multiple data read commands, and obtain the physical addresses corresponding to each of the data read commands respectively;

Steps 301-302 are the same as steps 101-102, for details, please refer to the relevant description of steps 101-102.

303. Arrange the multiple data read commands into the spare nodes in the preset command queue in turn, and each spare node is placed into a data read command;

That is, the parsed data read commands (that is, flash commands) are sequentially queued into the spare nodes (ie, the nodes that have not been placed into the command) in the preset command queue, and each spare node is placed into a data read command. It should be noted that the order here refers to the order in which the main control chip obtains and parses the data read commands.

Specifically, the command queue can be preset through the following steps:

The specified memory space is selected by the main control chip of the storage device;

The memory space is divided into N nodes to form the command queue, each node is used to store a data read command, and N is an integer greater than 1.

Preferably, the number of nodes N of the command queue is more than twice the number of storage units of the flash.

By setting N to be more than twice the number of storage units, when each storage unit executes a command, the CPU of the main control chip can parse the command issued by the host computer at the same time, so as to achieve the effect of parallel processing and further improve the processing efficiency. efficiency.

304. Cache the data read commands in the command queue into the linked list of each storage unit of the flash according to the corresponding physical addresses in turn;

The data read commands in the command queue are sequentially cached in the linked list of each storage unit of the flash according to the corresponding physical addresses. It should be noted that all data read commands can be queued into the command queue first, and then the data read commands in the command queue are cached to the linked list of each storage unit according to the corresponding physical address; it is also possible to read several data first. The command is queued into the command queue, and then the data read command in the command queue is buffered to the linked list of each storage unit, so that the command queue and the command buffer can be performed simultaneously, which can improve the processing efficiency.

During the initialization process of the flash, a linked list is created for each storage unit of the flash. The linked list is mainly used to cache data read commands, thereby facilitating the ordering of data read commands. Assuming that the physical address corresponding to the data read command A is ch0-CE1-die3, A is cached in the linked list of the memory unit die3 of the channel ch0 and the chip select CE1, and so on. It should be noted that a linked list of a storage unit has multiple nodes, which can cache multiple data read commands. in the linked list of storage units.

Specifically, a linked list header may be created for each storage unit, and the linked list header is used to manage each node of the storage unit linked list, such as allocation and reclamation of each node.

Specifically, a linked list header for managing spare nodes may also be created, which is used to manage allocation and recycling of spare nodes in the task queue.

The specific node management process is as follows: the head of the linked list is set with two pointers, a head pointer points to the head node, a tail pointer points to the tail node, each node has a pointer, and the relationship between two adjacent nodes is that the previous node pointer points to next node. Each time a node is taken from the tail pointer, the next node pointed to by this node will be found first, and then the tail pointer at the head of the linked list will point to this node. When each node enters the linked list, first point the pointer of the node to the node pointed to by the head pointer in the head of the linked list, and then point the head pointer in the linked list to the entered node.

305. Submit the data read command cached in the linked list of each storage unit to the controller of the flash.

It should be pointed out that when submitting the data read command cached in the linked list of each storage unit to the controller of the flash, the sequence of traversing the chip selection address and then the memory unit address is followed; or the channel address is traversed first, and then The sequence of traversing the chip selection address and finally traversing the memory unit address (for details, please refer to the relevant descriptions in the first embodiment and the second embodiment).

Optionally, step 305 may include:

(1) judge whether the total number of data read commands cached in the linked list of all storage units of the flash is greater than the first threshold;

(2) If the total number is greater than the first threshold, submit the first data read command cached in the linked list of the target storage unit to the controller of the flash; the target storage unit is in accordance with the traversal order The determined storage unit that should currently submit the data read command.

For the above step (1), it is determined whether the total number of data read commands buffered in the linked list of all storage units of the flash is greater than a first threshold. The larger the first threshold is set here, the better the task sorting effect is, but at the same time, the parallel processing effect of flash execution commands and main control chip parsing commands will be worse, so the first threshold cannot be set too large. Generally, it can be set to N/2, that is, half of the number of nodes in the command queue.

For the above step (2), if the total number is greater than the first threshold, submit the first data read command cached in the linked list of the target storage unit to the controller of the flash; the target storage unit is according to The storage unit determined by the traversal order that should currently submit the data read command. For example, if the current data read command that should be submitted according to the traversal order is ch3-CE1-die0, the first data read command cached in the linked list of the storage unit ch3-CE1-die0 (that is, the first data read command The data read command stored in the linked list) is submitted to the controller of the flash.

In addition, if the total number is less than or equal to the first threshold, the process may return to step 301 to wait for more data read commands to be buffered in the linked list of each storage unit of the flash. By setting in this way, the parallel processing of caching new commands to the linked list and submitting the commands cached in the linked list to the flash controller is achieved, which effectively improves the processing efficiency.

Optionally, step 305 may include:

(1) judging whether a new data reading command is obtained within a preset time length;

(2) If no new data read command is acquired within a preset time period, submit all the data read commands cached in the linked list of each storage unit to the controller of the flash.

For the above step (1), it is judged whether a new data read command is acquired within the preset time period, that is, whether the host computer issues a new data read command to the main control chip of the flash within the preset time period.

For the above step (2), if no new data read command is obtained within a preset time period, all data read commands cached in the linked list of each storage unit are submitted to the controller of the flash. Likewise, the traversal order is followed when submitting the data read command.

Further, if a new data read command is acquired within a preset time period, the new data read command is queued into a spare node in the command queue, and the new data read command is stored according to the corresponding physical address. The data read command is buffered in the linked list of the storage units of the flash. That is, if a new data read command is received, the new data read command is preferentially cached in the linked list of the storage unit until no new data read command is received. Then, all data read commands cached in the storage unit linked list are submitted to the controller of the flash for execution according to the traversal sequence. After all data read commands are submitted to the controller of the flash, the data read commands in the command queue can be cleared to free up more spare nodes.

Further, if there are not enough free nodes in the command queue (that is, all new data read commands cannot be queued), the number of caches in the linked list of each storage unit of the flash is compared with the new data. The same data read command as the read command is submitted to the controller of the flash, and the data read command submitted to the controller of the flash is cleared in the command queue to form the new data that can be queued Read the spare node for the command.

Since the number of nodes in the command queue is limited, there may be a problem that there are not enough free nodes in the queue to buffer new commands. At this time, a part of the data read commands are submitted to the controller of the flash, and then these data read commands are cleared in the command queue to free up spare nodes for new data read commands. It should be noted that when submitting a command to the flash controller, it is necessary to traverse the chip select address first, then the memory unit address in the order, or in the order of traversing the channel address first, then the chip select address, and finally the memory unit address. For example, if there is currently a new data read command, and there are no free nodes in the command queue, and the data read command with the physical address of ch0-CE0-die0 should be submitted in sequence, submit the linked list of ch0-CE0-die0 A data read command cached in the flash controller is sent to the flash controller, and then the data read command is cleared in the command queue to free up a spare node for a new data read command. In addition, if there are multiple data read commands cached in the linked list of ch0-CE0-die0, submit the data read command cached to the linked list earliest; if there is no cached data read command in the linked list of ch0-CE0-die0, Then submit a data read command cached in the linked list of ch0-CE0-die1.

The data reading method of the storage device provided by the embodiment of the present invention includes: acquiring multiple data reading commands issued by a host computer; analyzing the multiple data reading commands to obtain each data reading command respectively Corresponding physical addresses; arrange the multiple data read commands into the spare nodes in the preset command queue in turn, and each spare node is placed into a data read command; arrange the data read commands in the command queue Cache the data in the linked list of each storage unit of the flash sequentially according to the corresponding physical address; submit the data read command cached in the linked list of each storage unit to the controller of the flash. In this embodiment, by creating a linked list in each storage unit of the flash, and buffering all the acquired data read commands into the linked list of the corresponding storage unit, the ordering of the data read commands can be conveniently realized.

It should be understood that the size of the sequence numbers of the steps in the above-mentioned various embodiments does not mean the sequence of execution, and the execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention. .

The above mainly describes a data reading method of a storage device, and a data reading apparatus of a storage device will be described below.

Referring to FIG. 4, an embodiment of a data reading apparatus of a storage device in an embodiment of the present invention includes:

a data read command obtaining module 401, used to obtain a plurality of data read commands issued by the host computer;

The data read command parsing module 402 is configured to analyze the multiple data read commands, and obtain the physical addresses corresponding to each of the data read commands respectively, and the physical addresses include the chip select address of the flash and the storage unit. address;

The data read command submission module 403 is configured to submit the data read command to the controller of the flash according to the sequence of traversing the chip selection address first, and then traversing the memory unit address, so that the controller The received data read commands are sequentially executed.

Further, the physical address also includes the channel address of the flash, and the data read command submission module 403 can be specifically used for:

The data read command is submitted to the controller of the flash according to the sequence of first traversing the channel address, then traversing the chip selection address, and finally traversing the memory unit address.

An embodiment of the present invention further provides a terminal device, including a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the computer program, the implementation shown in FIG. 1 Steps to the data reading method of any storage device shown in FIG. 3 .

Embodiments of the present invention further provide a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, realizes the storage device of any of the storage devices shown in FIG. 1 to FIG. 3 . The steps of the data read method.

FIG. 5 is a schematic diagram of a terminal device according to an embodiment of the present invention. As shown in FIG. 5 , the terminal device 5 of this embodiment includes: a processor 50 , a memory 51 , and a computer program 52 stored in the memory 51 and executable on the processor 50 . When the processor 50 executes the computer program 52 , the steps in the above embodiments of the data reading method of each storage device are implemented, for example, steps 101 to 103 shown in FIG. 1 . Alternatively, when the processor 50 executes the computer program 52, the functions of the modules/units in each of the foregoing apparatus embodiments, such as the functions of the modules 401 to 403 shown in FIG. 4, are implemented.

The computer program 52 may be divided into one or more modules/units, which are stored in the memory 51 and executed by the processor 50 to accomplish the present invention. The one or more modules/units may be a series of computer program instruction segments capable of performing specific functions, and the instruction segments are used to describe the execution process of the computer program 52 in the terminal device 5 .

The terminal device 5 may be various types of computing devices such as mobile phones, desktop computers, notebooks, palm computers, and cloud servers. The terminal device may include, but is not limited to, the processor 50 and the memory 51 . Those skilled in the art can understand that FIG. 5 is only an example of the terminal device 5, and does not constitute a limitation on the terminal device 5, and may include more or less components than the one shown, or combine some components, or different components For example, the terminal device 5 may further include an input and output device, a network access device, a bus, and the like.

The so-called processor 50 may be a central processing unit (Central Processing Unit, CPU), or other general-purpose processors, digital signal processors (Digital Signal Processors, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), Off-the-shelf programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The memory 51 may be an internal storage unit of the terminal device 5 , such as a hard disk or a memory of the terminal device 5 . The memory 51 may also be an external storage device of the terminal device 5, such as a plug-in hard disk equipped on the terminal device 5, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, flash card (Flash Card) and so on. Further, the memory 51 may also include both an internal storage unit of the terminal device 5 and an external storage device. The memory 51 is used for storing the computer program and other programs and data required by the terminal device. The memory 51 can also be used to temporarily store data that has been output or will be output.

Those skilled in the art can clearly understand that, for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. Module completion, that is, dividing the internal structure of the device into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment may be integrated in one processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit, and the above-mentioned integrated units may adopt hardware. It can also be realized in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing from each other, and are not used to limit the protection scope of the present application.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, device and unit described above may refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

In the foregoing embodiments, the description of each embodiment has its own emphasis. For parts that are not described or described in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each particular application, but such implementations should not be considered beyond the scope of the present invention.

In the embodiments provided by the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the system embodiments described above are only illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be Incorporation may either be integrated into another system, or some features may be omitted, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. The above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.

The integrated unit, if implemented in the form of a software functional unit and sold or used as an independent product, may be stored in a computer-readable storage medium. Based on this understanding, the present invention can implement all or part of the processes in the methods of the above embodiments, and can also be completed by instructing relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium. When the program is executed by the processor, the steps of the foregoing method embodiments can be implemented. Wherein, the computer program includes computer program code, and the computer program code may be in the form of source code, object code, executable file or some intermediate form, and the like. The computer-readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM, Read-Only Memory) , Random Access Memory (RAM, RandomAccess Memory), electric carrier signal, telecommunication signal and software distribution medium, etc. It should be noted that the content contained in the computer-readable media may be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction, for example, in some jurisdictions, according to legislation and patent practice, the computer-readable media Excluded are electrical carrier signals and telecommunication signals.

The above-mentioned embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it is still possible to implement the foregoing implementations. The technical solutions described in the examples are modified, or some technical features thereof are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the within the protection scope of the present invention.

Claims (9)

1. A data reading method of a storage device, comprising:

acquiring a plurality of data reading commands issued by an upper computer;

analyzing the data reading commands to respectively obtain a physical address corresponding to each data reading command, wherein the physical address comprises a flash channel address, a chip select address and a storage unit address;

and submitting the data reading command to a flash controller according to the sequence of traversing the channel address, the chip selection address and the storage unit address, so that the controller sequentially executes the received data reading command.

2. The data reading method of the storage device according to claim 1, after parsing the plurality of data reading commands to obtain a physical address corresponding to each data reading command, further comprising:

sequentially discharging the data reading commands into spare nodes in a preset command queue, wherein each spare node is discharged into one data reading command;

caching the data reading commands in the command queue into linked lists of all storage units of the flash according to corresponding physical addresses in sequence, wherein the linked lists of all storage units of the flash are created in the initialization process of the flash;

the controller that submits the data reading command to the flash specifically includes:

and submitting the data reading command cached in the linked list of each storage unit to the controller of the flash.

3. The data reading method of the storage device according to claim 2, wherein the submitting the data reading command buffered in the linked list of each storage unit to the controller of the flash includes:

judging whether the total number of the data reading commands cached in the linked lists of all the storage units of the flash is larger than a first threshold value or not;

if the total number is larger than a first threshold value, submitting a first data reading command cached in a linked list of a target storage unit to the flash controller, wherein the target storage unit is a storage unit which is determined according to the traversal order and should submit the data reading command currently.

4. The data reading method of the storage device according to claim 2, wherein the submitting the data reading command buffered in the linked list of each storage unit to the controller of the flash includes:

judging whether a new data reading command is acquired within a preset time length;

and if the new data reading command is not acquired within the preset time length, submitting all the data reading commands cached in the linked lists of the storage units to the flash controller.

5. The data reading method of the storage device according to claim 4, further comprising:

and if a new data reading command is acquired within a preset time length, the new data reading command is arranged into the vacant nodes in the command queue, and the new data reading command is cached into the linked list of the flash storage unit according to the corresponding physical address.

6. The data reading method of the storage device according to claim 5, further comprising:

if the command queue does not have enough spare nodes, submitting the data reading commands, the quantity of which is the same as that of the new data reading commands, cached in the linked list of each storage unit of the flash to the controller of the flash, and clearing the data reading commands submitted to the controller of the flash in the command queue to form the spare nodes capable of being arranged in the new data reading commands.

7. A data reading apparatus of a storage device, comprising:

the data reading command acquisition module is used for acquiring a plurality of data reading commands issued by the upper computer;

the data reading command analysis module is used for analyzing the data reading commands to respectively obtain a physical address corresponding to each data reading command, wherein the physical address comprises a flash channel address, a chip selection address and a storage unit address;

and the data reading command submitting module is used for submitting the data reading command to the flash controller according to the sequence of traversing the channel address, then traversing the chip selection address and finally traversing the storage unit address, so that the controller sequentially executes the received data reading command.

8. A terminal device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of the data reading method of the memory device according to any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium, in which a computer program is stored, which, when being executed by a processor, carries out the steps of a data reading method of a storage device according to any one of claims 1 to 6.

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