CN108538331B - First read strategy in memory - Google Patents

Abstract

There is provided an apparatus, comprising: a block of memory cells; and control circuitry configured to perform an operation involving sensing of selected memory cells of the block in response to a command to perform the operation, and after the operation, perform a soft erase of the block of memory cells. Also disclosed is a method: applying a pass voltage to unselected memory cells of the connected set of memory cells, applying a sense voltage to selected memory cells of the connected set of memory cells; sensing the selected memory cell while applying the sensing voltage; after sensing, driving the control gate voltage of the unselected memory cells from the pass voltage to a lower level, resulting in a downward coupling of the voltage of the channels of the connected set of memory cells; generating a hole current in the channel to neutralize the voltage of the channel when the control gate voltage is driven at a lower level; and floating the control gate voltage of the unselected memory cells after the hole current is generated.

Description

First read strategy in memory

This application is a divisional application of the invention patent application with the application number 201810149225.1 and the invention title "First Read Countermeasure in Memory" filed on February 13, 2018.

technical field

The present technology relates to the operation of memory devices.

Background technique

The use of semiconductor memory devices in various electronic devices has become increasingly popular. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices.

Charge storage materials (such as floating gates) or charge trapping materials can be used in such memory devices to store charges representing data states. The charge trapping material can be arranged vertically in a three-dimensional (3D) stacked memory structure, or horizontally in a two-dimensional (2D) memory structure. One example of a 3D memory structure is the Bit Cost Scalable (BiCS) architecture, which includes stacks of alternating conductive and dielectric layers.

A memory device includes memory cells, which may be arranged in strings, eg, with select gate transistors provided at ends of the strings to selectively connect the channels of the strings to source lines or bit lines. However, various challenges exist in operating such memory devices.

SUMMARY OF THE INVENTION

In one embodiment, an apparatus includes: a block of memory cells connected to a set of word lines; a voltage detector connected to one or more word lines in the set of word lines, the voltage detection a control circuit configured to perform an evaluation of the voltage of one or more word lines; and a control circuit in communication with the voltage detector, the control circuit configured to determine, based on the evaluation, a device for use in a read block The read voltage set for the selected memory cell.

A method includes: in response to a read command involving a selected memory cell of a block, prior to reading the selected memory cell, determining whether a condition for applying a pre-read voltage pulse to the selected memory cell is met; if all the conditions are met; the conditions described, a pre-read voltage pulse is applied to the selected memory cell prior to reading the selected memory cell; and if the condition is not met, the pre-read voltage pulse is not applied to the selected memory cell Read the selected memory cell.

Another related apparatus contains means for performing each of the above steps. The above-described components may, for example, include components of the memory device 100 of FIGS. 1A and 2 . The power control module 116, for example, controls the power and voltage applied to the word lines, select gate lines, and bit lines during memory operation. Additionally, the above-described components may include the components of FIGS. 24A and 24B, including voltage drivers, switches, and pass transistors. The components may also include any of the control circuits in FIGS. 1A and 2 , such as control circuit 110 and controller 122 .

In another embodiment, an apparatus includes: timing means for periodically determining when to refresh a threshold voltage of a set of memory cells, the set of memory cells including one or more banks of memory cells; and for responding to means for timing the means to apply a voltage pulse to a set of word lines connected to memory cells of each of the one or more blocks.

In another embodiment, an apparatus includes: a block of memory cells; and a control circuit configured to, in response to a read or program command involving a selected memory cell of the block, sense the selected memory cell and then execute the memory Soft erase of a block of cells.

Description of drawings

1A is a block diagram of an exemplary memory device.

FIG. 1B illustrates an exemplary memory cell 200 .

Figure 1C depicts various features disclosed herein.

FIG. 1D illustrates an example of the temperature sensing circuit 115 of FIG. 1A .

FIG. 2 is a block diagram of an exemplary memory device 100 illustrating additional details of the controller 122 .

FIG. 3 is a perspective view of a memory device 600 including a block set in an exemplary 3D configuration of the memory structure 126 of FIG. 1 .

FIG. 4 depicts an exemplary cross-sectional view of a portion of one of the blocks of FIG. 3 .

FIG. 5 is a graph showing memory hole/pillar diameters in the stack of FIG. 4 .

FIG. 6 shows a close-up view of region 622 of the stack of FIG. 4 .

FIG. 7A depicts an exemplary view of NAND strings in sub-blocks in the 3D configuration according to FIG. 4 .

FIG. 7B illustrates word lines and SGD layers in an exemplary block set according to FIG. 4 .

8A depicts an exemplary Vth distribution for a memory cell under a first read condition compared to a second read condition, where eight data states are used.

Figure 8B depicts exemplary bit sequences for the lower, middle and upper pages of the data for the Vth distribution of Figure 8A, and associated read voltages.

FIG. 9 illustrates waveforms of an exemplary programming operation.

10A depicts a graph of exemplary waveforms in a programming operation showing upward coupling of word line voltages.

FIG. 10B shows a graph corresponding to the channel voltage (Vch) of FIG. 10A.

10C depicts a graph of exemplary waveforms in a read operation showing upward coupling of word line voltages.

FIG. 10D shows a graph corresponding to the channel voltage (Vch) of FIG. 10C.

FIG. 10E depicts the waveform of FIG. 10C showing the decay of the up-coupling voltage of the word line.

Figure 10F shows a graph of the channel voltage according to Figure 10E.

Figure 10G depicts a graph of Vth of a memory cell connected to an upwardly coupled word line according to Figures 10E and 10F.

Figure 11A depicts the control gate and channel voltages on a memory cell acting as a capacitor when the control gate voltage decreases in a sensing operation.

Figure 11B depicts a portion of a memory cell showing injection of electrons into the charge trapping region during weak programming.

12A illustrates the configuration of an example memory string just before the word line is discharged at the end of the sense operation.

Figure 12B illustrates the configuration of an example memory string just after the word lines are discharged at the end of the sensing operation.

12C illustrates an example memory string configuration when word lines are coupled up through channels.

Figure 12D illustrates the configuration of an example memory string when the word lines have been coupled up.

Figure 13A illustrates an exemplary process according to block 10 in Figure 1C.

Figure 13B shows a graph of shift on Vth versus time for different data states.

FIG. 13C shows a graph of read voltage versus detected word line voltage.

Figure 13D depicts a graph of read voltage versus detected word line voltage, where two sets of read voltages are used in the exemplary embodiment of Figure 13C.

Figure 13E illustrates another exemplary process in accordance with block 10 in Figure 1C.

Figure 14A illustrates an exemplary process according to block 11 in Figure 1C.

Figure 14B illustrates another exemplary process according to block 11 in Figure 1C.

FIG. 15A depicts a graph of exemplary waveforms in a read operation similar to that of FIG. 10C in which a pre-read voltage pulse is applied prior to the read operation.

FIG. 15B shows a graph corresponding to the channel voltage (Vch) of FIG. 15A.

Figure 15C depicts a plot of pre-read voltage pulse duration versus time since the last sensing operation according to step 1402b of the process of Figure 14A.

15D depicts a graph of pre-read voltage pulse duration versus detected word line voltage according to step 1402c of the process of FIG. 14A.

Figure 15E depicts a plot of pre-read voltage pulse duration versus temperature according to step 1402d of the process of Figure 14A.

15F depicts a graph of error count versus program pulse width according to the process of FIG. 14A.

Figure 16A illustrates an exemplary process according to block 12 in Figure 1C.

Figure 16B depicts a graph of periodic voltage pulses according to the process of Figure 16A.

Figure 16C shows a graph of the channel voltage according to Figure 16B.

Figure 16D depicts a graph of pulse period versus temperature according to block 1602a of Figure 16A.

Figure 17A illustrates an exemplary process according to block 13 in Figure 1C.

17B depicts a graph of exemplary erase voltages applied to a substrate in a normal erase operation.

Figure 17C shows a graph of verify voltages applied to word lines in a block according to Figure 17B.

18A illustrates the configuration of the exemplary memory string 1200 of FIG. 12A when holes are introduced into the channel from the substrate and the channel begins to neutralize in a soft erase operation according to step 1702 of FIG. 17 .

18B illustrates the configuration of an exemplary memory string when the channel is fully neutralized in the soft erase operation according to step 1702 of FIGS. 17 and 18A.

19A shows a diagram of exemplary waveforms in a read operation followed by a soft erase.

FIG. 19B shows the channel voltage during soft erase.

Figure 19C shows the SGS transistor voltage during soft erase.

Figure 19D shows the p-well voltage during soft erase.

20A illustrates the configuration of an exemplary memory string just after the word line is discharged at the end of a sense operation, where coupling is used to lower the SGD and SGS transistor voltages in a soft erase operation according to step 1702 of FIG. 17 .

20B illustrates the configuration of an exemplary memory string just after the word lines are discharged at the end of the sense operation, where SGD and SGS are driven negative voltages in a soft erase operation according to step 1702 of FIG. 17 . Transistor voltage drops.

Figure 20C shows an example when GIDL is used to introduce holes into the channel from the SGD and SGS transistors, and the channel begins to neutralize, in step 1702 according to Figure 17 and a soft erase operation according to Figure 20A or 20B, configuration of the memory string.

21A depicts a graph of exemplary waveforms in a read operation followed by a soft erase in accordance with FIGS. 20A and 20C, where the pass voltage ramps down to VpassL before ramping down to 0V.

FIG. 21B depicts the channel voltage during one example of soft erase.

21C illustrates SGS and/or SGD transistor voltages during one example of soft erase.

FIG. 21D depicts p-well voltages during one example of soft erase.

22A depicts a graph of exemplary waveforms in a read operation followed by a soft erase.

FIG. 22B depicts channel voltage during one example of soft erase.

FIG. 22C illustrates SGS and/or SGD transistor voltages during one example of soft erase.

22D depicts p-well voltages during one example of soft erase.

FIG. 23 illustrates an exemplary block diagram of the sensing block 51 in the column control circuit of FIG. 1A .

Figure 24A illustrates an example circuit for providing voltage to a block of memory cells.

24B illustrates an exemplary circuit according to FIG. 24B for detecting word line voltages according to the process of FIG. 13A.

Figure 25 illustrates a memory device 2500 in which voltage pulses are performed for a plurality of dies, one die at a time, according to the process of Figure 16A.

Detailed ways

Techniques are provided for improving the accuracy of read operations in memory devices. Corresponding memory devices are also provided.

In some memory devices, memory cells are linked to each other as NAND strings, such as in blocks or sub-blocks. Each NAND string includes one or more drain side SG transistors (SGD transistors) of the NAND string connected to the drain side of the bit line and one or more source sides of the NAND string connected to the source side of the source line Several series-connected memory cells between SG transistors (SGS transistors). Additionally, the memory cells may be arranged with a common control gate line (eg, a word line) that acts as a control gate. The set of word lines extends from the source side of the block to the drain side of the block. Memory cells can be connected in other types of strings and in other ways.

The memory cells may include data memory cells capable of storing user data, and dummy or non-data memory cells incapable of storing user data. The dummy word lines are connected to the dummy memory cells. One or more dummy memory cells may be provided at the drain and/or source terminals of the string of memory cells to provide gradual transitions in channel gradients.

During a programming operation, the memory cells are programmed according to the word line programming sequence. For example, programming may begin with a word line at the source side of the block and proceed to the word line at the drain side of the block. In one approach, each word line is fully programmed before programming the next word line. For example, the first word line WLO is programmed using one or more programming passes until programming is complete. Next, the second word line WL1 is programmed using one or more programming passes until programming is complete, and so on. A programming pass may involve an elevated set of programming voltages that are applied to word lines in corresponding programming loops or program-verify iterations, such as shown in FIG. 9 . A verify operation can be performed after each programming voltage to determine whether the memory cell has completed programming. When programming is complete for a memory cell, it can be locked from further programming while programming continues for other memory cells in subsequent programming loops.

Memory cells may also be programmed according to the sub-block programming order, in which case memory cells in one sub-block or portion of a block are programmed before memory cells in another sub-block are programmed.

Each memory cell can be associated with a data state according to the write data in the program command. Based on its data state, the memory cell will remain in the erased state or be programmed to the programmed data state. For example, in a one-bit-per-cell memory device, there are two data states, including an erased state and a programmed state. In a two-bit-per-cell memory device, there are four data states, including the erased state and three higher data states, referred to as the A, B, and C data states. In a three-bit-per-cell memory device, there are eight data states, including the erased state and seven higher data states, referred to as the A, B, C, D, E, F, and G data states (see Figure 8A) . In a four-bit-per-cell memory device, there are sixteen data states, including an erased state and fifteen higher data states. The data states may be referred to as S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14 and S15 data states, where S0 is the erased state.

After programming the memory cells, the data can be read back in a read operation. A read operation may involve applying a series of read voltages to a word line while the sensing circuit determines that cells connected to the word line are in a conducting or non-conducting state. If the cell is in a non-conducting state, the Vth of the memory cell exceeds the read voltage. The read voltage is set to a level expected to be between the threshold voltage levels of adjacent data states.

However, it has been observed that the Vth of a memory cell may vary depending on when a read operation occurs. For example, Vth may vary among memory cells depending on the up-coupling state of the word lines when a read operation occurs. The "first read" condition may be defined as where the word lines are not coupled up, and the "second read" condition may be defined as where the word lines are coupled up.

After a power-up event in the memory device, the memory cells may be in a first read condition. Checking for bad blocks can occur when a memory device is powered up for use. This operation involves applying 0V or other low voltage to the word line. Therefore, any upward coupling of the word line voltage is discharged.

The word line can also be discharged in the block when the word line voltage is set low. This can happen when an operation is being performed in another block while that block is inactive. Because the word line discharges over time, the cell may also be in the first read condition after a long time has elapsed since the last sensing operation. The upward coupling of the word lines causes Vth to shift in the cell due to unintentional programming or erasing. This Vth does not occur because the word lines are not significantly coupled up when in the first read condition.

A cell may be in a second read condition when a read occurs a short time (eg, seconds or minutes) after the last sensing operation. Because the word line is relatively strongly coupled up when in the second read condition, there is programming or erasing of the cell due to the word line voltage, and a corresponding shift in Vth. In particular, word lines with up-coupling voltages can result in weak programming of cells with relatively low Vth (below the up-coupling voltage) (eg, cells in lower programmed data states), resulting in Vth for these cells Shift up. In addition, there may be weak erases of cells with relatively high Vth (above the up-coupling voltage) (eg, cells in higher programmed data states), resulting in a downward shift in Vth for these cells.

As the word line discharges, the cell gradually transitions from the second read condition to the first read condition over time (eg, one hour).

The upward coupling of word line voltages is caused by the voltage of a sense operation, such as a verify operation that occurs in connection with a program operation, or a read operation that occurs after the program operation is complete. Sensing of a cell involves applying a sense voltage (eg, read/verify voltage) to a selected word line. At the same time, the read pass voltage is applied to the unselected word lines, and then steps down. This step down temporarily reduces the channel voltage due to capacitive coupling. Also due to capacitive coupling, this causes a rise or upward coupling of the word line voltage when the channel voltage rises back to its nominal level. For cells in lower data states, Vth gradually decreases as electrons trapped in the cell's charge-trapping material are released and returned to the channel. For cells in higher data states, Vth gradually increases as electrons are removed from the channel. See Figure 8A.

When a read operation occurs, it is not known whether the cell is in the first read condition or the second read condition, or possibly somewhere in between. One approach is to track the elapsed time since a power-up event or previous sensing operation. However, this elapsed time may not be an accurate indicator of whether the word lines are coupled up, or the degree to which they are coupled up, since other factors such as environmental factors and process variations may be relevant. Additionally, each block will need to be tracked separately.

The techniques presented herein address these and other issues.

Figure 1C depicts various features disclosed herein. The first feature includes detecting the up-coupling state of the word line and setting the read voltage accordingly (block 10). The second feature involves applying a pre-read voltage pulse just before the read operation (block 11). A third feature includes periodically applying voltage pulses to all word lines in the block (block 12). This can occur independently of the read command and involves refreshing the threshold voltage of the memory cell to the second read condition. A fourth feature involves performing a soft erase (block 13) just after a read or program operation.

Various other features and advantages are described below.

1A is a block diagram of an exemplary memory device. A memory device 100 , such as a non-volatile memory system, may contain one or more memory dies 108 . The memory die 108 includes a memory structure 126 of memory cells, such as an array of memory cells, control circuits 110 , and read/write circuits 128 . The memory structures 126 are addressable by word lines via row decoders 124 and by bit lines via column decoders 132 . The read/write circuit 128 contains a plurality of sense blocks 51, 52, . . . , 53 (sensing circuits) and allows pages of memory cells to be read or programmed in parallel. Typically, the controller 122 is included in the same memory device 100 (eg, a removable memory card) as the one or more memory dies 108 . The controller may be separate from the memory die. Commands and data may be transferred between host 140 and controller 122 via data bus 120 and between the controller and one or more memory dies 108 via lines 118 .

The memory structure can be 2D or 3D. The memory structure may include one or more arrays of memory cells, including a 3D array. Memory structures may include monolithic 3D memory structures in which multiple memory levels are formed over (and not in) a single substrate, such as a wafer, without intervening substrates. The memory structure may include any type of non-volatile memory monolithically formed as one or more physical levels of an array of memory cells having an active area disposed over a silicon substrate. The memory structure may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is over or within the substrate.

Control circuit 110 cooperates with read/write circuit 128 to perform memory operations on memory structure 126 and includes state machine 112 , on-chip address decoder 114 , and power control module 116 . State machine 112 provides chip-level control of memory operations. As discussed further below, the state machine may include a clock 112a to determine the elapsed time since the last sensing operation. As described further below, a storage area 113 may be provided, for example, for read voltage sets. In general, the memory area can store operating parameters and software/code. As an example, timer 113a may be used to determine when to periodically apply voltage pulses to word lines, as described below with respect to Figures 13E and 16A. A temperature sensor 115 may also be provided. See Figure 1D.

In one example, the state machine is programmable through software. In other embodiments, the state machine does not use software and is implemented entirely in hardware (eg, circuitry).

On-chip address decoder 114 provides an address interface between addresses used by the host or memory controller to hardware addresses used by decoders 124 and 132 . The power control module 116 controls the power and voltage applied to the word lines, select gate lines, and bit lines during memory operation. It may contain drivers for word lines, SGS and SGD transistors, and source lines. See Figure 24. In one approach, the sense block may include bit line drivers. The SGS transistor is the select gate transistor at the source terminal of the NAND string, and the SGD transistor is the select gate transistor at the drain terminal of the NAND string.

In some embodiments, some of the components may be combined. In various designs, one or more of the components (alone or in combination) (other than memory structure 126 ) may be conceived as at least one control circuit configured to perform the techniques described herein, including the steps of the process. For example, the control circuit may include any one or a combination of the following: control circuit 110, state machine 112, decoders 114 and 132, power control module 116, sense blocks 51, 52, ..., 53, read /Write circuit 128, controller 122, etc.

The off-chip controller 122 , which is a circuit in one embodiment, may include a processor 122 c , storage devices (memory) such as ROM 122 a and RAM 122 b , and an error correction code (ECC) engine 245 . The ECC engine can correct several read errors.

A memory interface 122d may also be provided. The memory interface that communicates with the ROM, RAM, and processor is the circuit that provides the electrical interface between the controller and the memory die. For example, a memory interface can change the format or timing of signals, provide buffers, isolate from surges, latch I/O, and so on. The processor may issue commands to the control circuit 110 (or any other component of the memory die) via the memory interface 122d.

The storage device includes code, such as a set of instructions, and the processor is operable to execute the set of instructions to provide the functions described herein. Alternatively or additionally, the processor may access code from a storage device 126a of the memory structure, such as a reserved area of memory cells in one or more word lines.

For example, a controller may use code to access memory structures, such as for program, read, and erase operations. The code may include bootstrap code and control code (eg, instruction sets). Boot code is software that initializes the controller and enables the controller to access memory structures during the boot or boot process. The controller may use the code to control one or more memory structures. Upon power up, processor 122c retrieves boot code from ROM 122a or storage 126a for execution, and the boot code initializes system components and loads control code into RAM 122b. Once the control code is loaded into RAM, it is executed by the processor. Control code contains drivers to perform basic tasks such as controlling and allocating memory, prioritizing the processing of instructions, and controlling input and output ports.

In general, the control code may contain instructions to perform the functions described herein, including the steps of the flowcharts discussed further below, and to provide voltage waveforms including those discussed further below. The control circuitry may be configured to execute instructions to perform the functions described herein.

In one example, the host is a computing device (eg, laptop computer, desktop computer, smartphone, tablet, digital camera) that includes one or more processors, one or more processor-readable storage devices (RAM, ROM, flash memory, hard drive, solid state memory) that stores processor-readable code (eg, software) to program one or more processors to perform the methods described herein. The host may also contain additional system memory, one or more input/output interfaces, and/or one or more input/output devices in communication with one or more processors.

Other types of non-volatile memory besides NAND flash memory can also be used.

Semiconductor memory devices include volatile memory devices such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices, such as resistive random access memory ("ReRAM"), electrically erasable In addition to programmable read only memory ("EEPROM"), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetoresistive random access memory ("MRAM") ”) non-volatile memory devices, and other semiconductor elements capable of storing information. Each type of memory device may have a different configuration. For example, flash memory devices may be configured in a NAND or NOR configuration.

Memory devices may be formed from passive and/or active elements in any combination. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching memory elements such as antifuses or phase change materials, and optionally include steering elements such as diodes or transistors . Also by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing charge storage regions such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

Multiple memory elements can be configured such that they are connected in series or such that each element is individually accessible. As a non-limiting example, a flash memory device in a NAND configuration (NAND memory) typically contains memory elements connected in series. A NAND string is an example of a series-connected set of transistors that includes memory cells and SG transistors.

A NAND memory array can be configured such that the array consists of multiple strings of memory, where a string consists of multiple memory elements that share a single bit line and are accessed as groups. Alternatively, the memory elements may be configured such that each element is individually accessible, eg, a NOR memory array. NAND and NOR memory configurations are examples, and memory elements may be configured in other ways.

The semiconductor memory elements located in and/or on the substrate may be arranged in two or three dimensions, such as a 2D memory structure or a 3D memory structure.

In a 2D memory structure, semiconductor memory elements are arranged in a single plane or at the level of a single memory device. Typically, in a 2D memory structure, the memory elements are arranged in a plane (eg, a plane in the x-y direction) that extends substantially parallel to the major surface of the substrate supporting the memory elements. The substrate may be a wafer on or in which the layers of memory elements may be formed, or it may be a carrier substrate, which is attached to the memory elements after formation. As a non-limiting example, the substrate may comprise a semiconductor such as silicon.

The memory elements may be arranged in a single memory device level in an ordered array, such as multiple rows and/or columns. However, the memory elements may be arranged in an irregular or non-orthogonal configuration. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.

The 3D memory array is arranged such that the memory elements occupy multiple planes or multiple memory device levels, forming three dimensions (ie, in the x, y, and z directions, where the z direction is substantially perpendicular to the major surface of the substrate, and x and y The orientation is substantially parallel to the structure on the major surface of the substrate).

As a non-limiting example, a 3D memory structure may be arranged vertically as a stack of multiple 2D memory device levels. As another non-limiting example, a 3D memory array may be arranged in multiple vertical columns (eg, columns extending substantially perpendicular to the major surface of the substrate (ie, in the y-direction)), where each column has multiple memories element. Columns can be arranged in a 2D configuration (eg, in the x-y plane), resulting in a 3D arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also form 3D memory arrays.

As a non-limiting example, in a 3D NAND memory array, memory elements may be coupled together to form NAND strings within a single horizontal (eg, x-y) memory device level. Alternatively, memory elements may be coupled together to form vertical NAND strings that span multiple horizontal memory device levels. Other 3D configurations can be envisaged where some NAND strings contain memory elements in a single memory level, while other strings contain memory elements spanning multiple memory levels. 3D memory arrays can also be designed in NOR configuration and ReRAM configuration.

Typically, in a monolithic 3D memory array, one or more memory device levels are formed over a single substrate. Optionally, the monolithic 3D memory array may also have one or more memory layers at least partially within a single substrate. As a non-limiting example, the substrate may comprise a semiconductor such as silicon. In a monolithic 3D array, each memory device level layer that makes up the array is typically formed on the underlying memory device level layer of the array. However, layers of adjacent memory device levels of a monolithic 3D memory array may be shared, or have intervening layers between memory device levels.

The 2D arrays can be formed separately and then packaged together to form non-monolithic memory devices with multiple layers of memory. For example, non-monolithic stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrates can be thinned or removed from their memory device levels prior to stacking, but since the memory device levels are initially formed over separate substrates, the resulting memory array is not a monolithic 3D memory array. Furthermore, multiple 2D memory arrays or 3D memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

Operation of the memory element and communication with the memory element typically require associated circuitry. As a non-limiting example, a memory device may have circuitry for controlling and driving memory elements to perform functions such as programming and reading. This associated circuit may be on the same substrate as the memory element and/or on a separate substrate. For example, the controller for memory read-write operations may be located on a separate controller chip and/or on the same substrate as the memory elements.

Those skilled in the art will recognize that the present technology is not limited to the 2D and 3D exemplary structures described, but covers all relevant memory as described herein and as understood by those skilled in the art of the spirit and scope of the present technology structure.

FIG. 1B illustrates an exemplary memory cell 200 . The memory cell includes a control gate CG that receives word line voltage Vwl, a drain at voltage Vd, a source at voltage Vs, and a channel at voltage Vch.

FIG. 1D illustrates an example of the temperature sensing circuit 115 of FIG. 1A . The circuit includes pMOSFETs 131a, 131b and 134, bipolar transistors 133a and 133b, and resistors R1, R2 and R3. I1, I2 and I3 refer to current. Voutput is the temperature-based output voltage provided to an analog-to-digital (ADC) converter 129 . Vbg is a temperature-dependent voltage. The voltage level generation circuit 135 uses Vbg to set several voltage levels. For example, the reference voltage can be divided into several levels by a resistor divider circuit.

The ADC compares Voutput to the voltage levels and selects the closest match among the voltage levels, outputting the corresponding digital value (VTemp) to the processor. This is data indicative of the temperature of the memory device. In one approach, ROM fuses 123 store data that correlates matching voltage levels to temperature. The processor then uses the temperature to set temperature-based parameters in the memory device.

Vbg is obtained by adding the base-emitter voltage (Vbe) across transistor 131b and the voltage drop across resistor R2. The bipolar transistor 133a has a larger area (N times) than the transistor 133b. PMOS transistors 131a and 131b are equal in size and arranged in a current mirror configuration such that currents I1 and I2 are substantially equal. We know that Vbg=Vbe+R2×I2 and I1=Ve/R1, thus I2=Ve/R1. Thus, Vbg=Vbe+R2×kT ln(N)/R1×q, where T is the temperature, k is the Boltzmann constant and q is the unit of charge. The source of the transistor 134 is connected to the supply voltage Vdd, and the node between the drain of the transistor and the resistor R3 is the output voltage Voutput. The gate of transistor 134 is connected to the same terminal as the gates of transistors 131a and 131b, and the current through transistor 134 mirrors the current through transistors 131a and 131b.

FIG. 2 is a block diagram of an exemplary memory device 100 illustrating additional details of the controller 122 . As used herein, a flash memory controller is a device that manages data stored on flash memory and communicates with a host, such as a computer or electronic device. A flash memory controller may have various functions in addition to the specific functions described herein. For example, a flash memory controller may format the flash memory to ensure correct operation of the memory, map out bad flash memory cells, and allocate spare memory cells to replace cells that fail in the future. Portions of the spare unit may be used to hold firmware to operate the flash memory controller and implement other features. In operation, when the host needs to read data from or write data to the flash memory, it will communicate with the flash memory controller. If the host provides a logical address to which data is to be read/written, the flash memory controller can translate the logical address received from the host to a physical address in the flash memory. (Alternatively, the host may provide a physical address). The flash memory controller may also perform various memory management functions, such as, but not limited to, wear leveling (scattering writes to avoid wear of a particular block of memory that is repeatedly written) and garbage collection (when a block is full After that, only valid pages of data are moved to new blocks, so full blocks can be erased and reused).

The interface between controller 122 and non-volatile memory die 108 may be any suitable flash interface. In one example, memory device 100 may be a card-based system, such as a Secure Digital (SD) or Micro Secure Digital (micro-SD) card. In alternative embodiments, the memory system may be part of an embedded memory system. For example, flash memory may be embedded in a host, such as in the form of a solid state disk (SSD) drive installed in a personal computer.

In some embodiments, the memory device 100 includes a single channel between the controller 122 and the non-volatile memory die 108, and the subject matter described herein is not limited to having a single memory channel.

The controller 122 includes a front-end module 208 that interfaces with the host, a back-end module 210 that interfaces with one or more non-volatile memory dies 108, and various other modules that perform functions that will be described in detail below.

For example, a component of a controller may take the form of a packaged functional hardware unit (eg, a circuit) designed to be used with other components, by a processor (eg, a microprocessor, or generally performing particular ones of the related functions) processing circuitry) executable program code portions (eg, software or firmware), or self-contained hardware or software components that interface with a larger system. For example, each module may contain an application specific integrated circuit (ASIC), field programmable gate array (FPGA), circuit, digital logic circuit, analog circuit, combination of discrete circuits, gates, or any other type of hardware or combination thereof. Alternatively or additionally, each module may contain software stored in a processor-readable device (eg, memory) to program the processor to cause the controller to perform the functions described herein. The architecture shown in FIG. 2 is an example implementation that may (or may not) use the components (eg, RAM, ROM, processor, interface) of the controller 122 illustrated in FIG. 1A .

Controller 122 may include recondition circuitry 212 for reconditioning memory cells or blocks of memory. Repair may include refreshing the data at its current location or reprogramming the data into a new word line or block as part of performing erratic word line maintenance, as described below.

Referring again to the modules of controller 122 , buffer manager/bus controller 214 manages buffers in random access memory (RAM) 216 and controls the internal bus arbitration of controller 122 . RAM may contain DRAM and/or SRAM. DRAM or Dynamic Random Access Memory is a type of semiconductor memory in which the memory is stored in the form of electrical charges. Each memory cell in DRAM is made of transistors and capacitors. Data is stored in capacitors. Due to leakage, the capacitor discharges charge, and thus the DRAM is a volatile device. To retain data in memory, the device must be refreshed regularly. In contrast, SRAM or static random access memory will retain the value as long as power is supplied.

Read only memory (ROM) 218 stores system boot code. Although illustrated in FIG. 2 as being located separate from the controller, in other embodiments one or both of RAM 216 and ROM 218 may be located in the controller. In other embodiments, portions of RAM and ROM may be located both within the controller 122 and external to the controller. Additionally, in some embodiments, controller 122, RAM 216, and ROM 218 may be located on separate semiconductor dies.

The front end module 208 includes a host interface 220 and a physical layer interface (PHY) 222, which provide an electrical interface to the host or next level memory bank controller. The selection of the type of host interface 220 may depend on the type of memory used. Examples of host interface 220 include, but are not limited to, SATA, SATA high-speed, SAS, Fibre Channel, USB, PCIe, and NVMe. Host interface 220 typically facilitates the transfer of data, control signals, and timing signals.

Backend module 210 includes an error correction controller (ECC) engine 224 that encodes data bytes received from the host, and decodes and error corrects data bytes read from non-volatile memory. Command sequencer 226 generates command sequences, such as program and erase command sequences, for transfer to non-volatile memory die 108 . A RAID (Redundant Array of Independent Dies) module 228 manages the generation of RAID parity and restores failed data. RAID parity may be used as an additional level of integrity protection for data being written into memory device 100 . In some cases, RAID module 228 may be part of ECC engine 224 . It should be noted that RAID parity can be added as an additional die or dies referred to by the common name, but it can also be added within an existing die, for example as an extra plane, or an extra area block, or extra word lines within a block. Memory interface 230 provides command sequences to non-volatile memory die 108 and receives status information from the non-volatile memory die. The flash control layer 232 controls the overall operation of the backend module 210 .

Additional components of the memory device 100 include a media management layer 238 that performs wear leveling of the memory cells of the non-volatile memory die 108 . The memory system also includes other discrete components 240 , such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may interface with the controller 122 . In alternate embodiments, one or more of physical layer interface 222 , RAID module 228 , media management layer 238 , and buffer management/bus controller 214 are optional components that are not required in controller 122 .

A flash translation layer (FTL) or media management layer (MML) 238 may be integrated as part of the flash management, which handles flash errors and interfaces with the host. In particular, the MML may be a module in flash management and may be responsible for the internals of NAND management. In particular, MML 238 may contain algorithms in memory device firmware that translate writes from the host into writes to memory structure 126 (eg, flash memory) of die 108 . MML 238 may be required because: 1) Flash memory may have limited endurance; 2) Flash memory may only be written in multiple pages; and/or 3) Flash memory may not be writable unless it acts as a Block is erased. The MML 238 understands these potential limitations of flash memory that may not be visible to the host. Accordingly, MML 238 attempts to convert writes from the host to writes into flash memory. Unstable bits can be identified and recorded using MML 238. This record of unstable bits can be used to assess the health of blocks and/or word lines (memory cells on word lines).

Controller 122 may interface with one or more memory dies 108 . In one example, the controller and multiple memory dies (together include the memory device 100) implement a solid state drive (SSD) that can emulate, replace, or be used in place of a hard drive in a host as a network attached storage (NAS) device, etc. Additionally, there is no need for the SSD to function as a hard drive.

3 is a perspective view of a memory device 600 including a block set of an exemplary 3D configuration of the memory structure 126 of FIG. 1A. On the substrate are exemplary blocks of memory cells (storage elements) BLK0, BLK1, BLK2, and BLK3, and a peripheral region 604 with circuitry used by the blocks. For example, the circuit may contain a voltage driver 605, which may be connected to the control gate layer of the block. In one approach, the control gate layers at a common height in a block are commonly driven. The substrate 601 may also carry the circuitry under the block, and one or more lower metal layers patterned as conductive paths to carry the circuitry's signals. The blocks are formed in the middle region 602 of the memory device. In the upper region 603 of the memory device, one or more upper metal layers are patterned as conductive paths to carry the signals of the circuit. Each block includes stacked regions of memory cells, with alternating levels of the stack representing word lines. In one possible approach, each block has opposing layered sides from which vertical contacts extend up to the upper metal layer to form connections to conductive paths. Although four blocks are shown as an example, two or more blocks extending in the x and/or y direction may be used.

In one possible approach, the block is in a plane, and the length of the plane in the x-direction represents the direction in which the signal path to the wordline extends in one or more upper metal layers (wordline or SGD line direction), And the width of the plane in the y direction represents the direction in which the signal path of the bit line extends in the one or more upper metal layers (bit line direction). The z-direction represents the height of the memory device. Blocks can also be arranged in multiple planes.

FIG. 4 depicts an exemplary cross-sectional view of a portion of a block of FIG. 3 . The block includes a stack 616 of alternating conductive and dielectric layers. In this example, in addition to the data word line layers (or word lines) WLL0-WLL10, the conductive layers include two SGD layers, two SGS layers, and four dummy word line layers (or word lines) WLD1, WLD2, WLD3 and WLD4. The dielectric layers are labeled DL0-DL19. In addition, the stack is shown where the stack includes the NAND strings NS1 and NS2. Each NAND string contains a memory hole 618 or 619 filled with the material that forms the memory cells adjacent to the word line. Region 622 of the stack is shown in more detail in FIG. 6 .

The stack includes a substrate 611 . In one approach, a portion of the source line SL includes an n-type source diffusion layer 611a in the substrate that is in contact with the source terminal of each string of memory cells in the block. In one possible implementation, the n-type source diffusion layer 611a is formed in the p-type well region 611b, the p-type well region 611b is further formed in the n-type well region 611c, and the n-type well region 611c is further formed in the p-type well region 611c. in the semiconductor substrate 611d. In one approach, the n-type source diffusion layer can be shared by all blocks in the plane.

NS1 has a source terminal 613 at the bottom 616b of the stack and a drain terminal 615 at the top 616a of the stack. Local interconnects such as local interconnect 617 may be provided periodically across the stack. The local interconnects may be metal-filled slits that extend through the stack, such as to connect source lines/substrates to lines above the stack. The slits may be used during the formation of the word lines and then filled with metal. The local interconnect includes conductive regions 617a (eg, metal) within insulating regions 617b. A portion of bit line BL0 is also depicted. Conductive via 621 connects the drain terminal 615 of NS1 to BL0.

In one approach, a block of memory cells includes a stack of alternating control gates and dielectric layers, and the memory cells are arranged in memory holes extending vertically in the stack.

In one approach, each block includes a stepped edge with vertical interconnects connected to each layer (including the SGS, WL, and SGD layers) and extending up to the horizontal path to the voltage source.

For example, this example includes two SGD transistors, two drain side dummy memory cells, two source side dummy memory cells, and two SGS transistors in each string. In general, the use of dummy memory cells is optional, and one or more dummy memory cells may be provided. Additionally, one or more SGD transistors and one or more SGS transistors may be provided in the memory string.

Insulating regions 620 may be provided to separate portions of the SGD layer from each other, thereby providing each sub-block with an independently driven SGD line. In this example, the word line layer is common to two adjacent sub-blocks. See also Figure 7B. In another possible implementation, the insulating region 620 extends down to the substrate to separate the word line layers. In this case, the word line layer is divided in each subblock. Although, in any case, the word line layers of a block may be joined to each other at their ends such that they are driven collectively within the block, as shown in Figure 7B.

FIG. 5 is an illustration of memory hole/pillar diameters in the stack of FIG. 4 . The vertical axis is aligned with the stack of FIG. 4 and depicts the width (wMH) (eg, diameter) of the posts formed from the material in the memory holes 618 and 619 . In such memory devices, the memory holes etched through the stack have a very high aspect ratio. For example, a depth to diameter ratio of about 25-30 is common. The memory hole may have a circular cross-section. Due to the etch process, the memory hole and resulting column width may vary along the length of the hole. Typically, the diameter tapers from the top to the bottom of the memory hole (solid line). That is, the memory holes are tapered, narrowing at the bottom of the stack. In some cases, a slight narrowing occurs at the top of the hole near the select gate, so that the diameter widens slightly (long broken line) before tapering from the top to the bottom of the memory hole. For example, in this example, the memory hole width is largest at the level of WL9 in the stack. The memory hole width is slightly smaller at the level of WL10, and gradually becomes smaller at the level of WL8 to WL0.

Due to the non-uniformity in the diameter of the memory holes and the resulting pillars, the programming and erasing speeds of memory cells may vary based on their location along the memory holes. With a relatively small diameter at the bottom of the memory hole, the electric field across the tunnel oxide is relatively strong, so that programming and erasing speeds are relatively slow for memory cells in word lines adjacent to the relatively small diameter portion of the memory hole higher. The amount of upward coupling and discharge of the word line is thus relatively greater than the memory cells in the word line adjacent to the relatively larger diameter portion of the memory hole.

In another possible embodiment, indicated by the short dashed line, the stack is manufactured in two levels. The bottom level is first formed with corresponding memory holes. The top level is then formed with corresponding memory holes that align with the memory holes in the bottom level. Each memory hole is tapered such that a double tapered memory hole is formed where the width increases, then decreases and increases again from the bottom to the top of the stack.

FIG. 6 shows a close-up view of region 622 of the stack of FIG. 4 . Memory cells are formed at different levels of the stack, at the intersections of word line layers and memory holes. In this example, SGD transistors 680 and 681 are provided over dummy memory cells 682 and 683 and data memory cell MC. Several layers may be deposited along the sidewalls (SW) of the memory holes 630 and/or within each word line layer, eg, using atomic layer deposition. For example, each pillar 699 or pillar formed from the material within the memory hole may contain a charge trapping layer 663 or a thin film such as silicon _nitride (Si3N4 ₎ or other nitrides, a tunneling layer 664 (tunnel oxide), Channel 665 (eg, comprising polysilicon), and dielectric core 666 . The word line layer may include a blocking oxide/blocking high-k material 660, a metal barrier 661, and a conductive metal 662 such as tungsten as a control gate. For example, control gates 690, 691, 692, 693 and 694 are provided. In this example, all layers except metal are provided in the memory holes. In other approaches, some of the layers may be in the control gate layer. Additional pillars are similarly formed in different memory holes. The pillars may form pillar-shaped active areas (AA) of the NAND strings.

When programming a memory cell, electrons are stored in the portion of the charge trapping layer associated with the memory cell. These electrons are introduced into the charge trapping layer from the channel and pass through the tunneling layer. The Vth of a memory cell increases proportionally to the amount of stored charge (eg, as the amount of stored charge increases). During the erase operation, electrons return to the channel.

Each of the memory holes may be filled with a plurality of annular layers including a blocking oxide layer, a charge trapping layer, a tunneling layer, and a channel layer. The core region of each of the memory holes is filled with a body material, and a plurality of annular layers are between the core region and the word lines in each memory hole.

A NAND string can be considered to have a floating body channel because the length of the channel is not formed on the substrate. Furthermore, the NAND strings are provided by a plurality of word line layers stacked on top of each other in the stack and separated from each other by a dielectric layer.

FIG. 7A illustrates an exemplary view of NAND strings in a sub-block according to the 3D configuration of FIG. 4 . Exemplary memory cells are depicted extending in the x-direction along word lines in each subblock. For simplicity, each memory cell is shown as a cube. SB0 contains NAND strings 700n, 701n, 702n and 703n. SB1 contains NAND strings 710n, 711n, 712n and 713n. SB2 contains NAND strings 720n, 721n, 722n and 723n. SB3 contains NAND strings 730n, 731n, 732n and 733n. The bit lines are connected to the NAND string sets. For example, bit line BL0 is connected to NAND strings 700n, 710n, 720n and 730n, bit line BL1 is connected to NAND strings 701n, 711n, 721n and 731n, bit line BL2 is connected to NAND strings 702n, 712n, 722n and 732n, and bit line BL3 is connected to NAND strings 703n, 713n, 723n and 733n. A sense circuit can be connected to each bit line. For example, sense circuits 400, 400a, 400b and 400c are connected to bit lines BL0, BL1, BL2 and BL3, respectively. A NAND string is an example of a vertical memory string (eg, a vertical string) that extends upward from the substrate.

For selected cells, programming and reading can occur one wordline and one subblock at a time. This allows each selected cell to be controlled by a corresponding bit line and/or source line. For example, an exemplary set 795 of memory cells in SBO is connected to WLL4. Similarly, sets 796, 797 and 798 comprising data memory cells in SB1, SB2 and SB3 are connected to WLL4.

FIG. 7B illustrates word lines and SGD layers in an exemplary block set according to FIG. 4 . Blocks BLK0, BLK1, BLK2 and BLK2 are depicted. The word line layer (WLL) in each block is depicted, along with exemplary SGD lines. One SGD line is provided in each subblock. BLK0 contains subblocks SB0, SB1, SB2 and SB3. Each circle represents a memory hole or string. In practice, a subblock extends in the x-direction and contains thousands of memory strings. Additionally, more blocks than those depicted are arranged in rows on the substrate. The word line layer and the SGD/SGS layer may receive voltages from the row decoder 2410 . See also Figures 24A and 24B.

8A depicts an exemplary Vth distribution for a memory cell at a first read condition compared to a second read condition, where eight data states are used. The eight data states are only an example, as other numbers, such as four, sixteen, or more, could also be used. For Er, A, B, C, D, E, F and G states, we know the Vth distributions 820, 821, 822, 823, 824, 825, 826 and 827 under the second read condition, respectively, and have 820a, 821a, 822a, 823a, 824a, 825a, 826a and 827a under the first read condition, respectively. For A, B, C, D, E, F and G states we have program verify voltages VvA, VvB, VvC, VvD, VvE, VvF and VvG respectively. Also shown are the read voltages VrAH, VrBH, VrCH, VrDH, VrEL, VrFL and VrGL under the second read condition, respectively, and the read voltages VrAL, VrBL, VrCL under the first read condition, respectively, VrDL, VrEH, VrFH and VrGH. Also depicted are exemplary encodings of bits of 111, 110, 100, 000, 010, 011, 001 and 101, respectively. The bit format is: UP/MP/LP. The erase verify voltage VvEr is used during the erase operation.

This example indicates that when the data state is relatively high or low, the shift on the Vth distribution for the first read condition is relatively larger than when the data state is in the middle range compared to the second read condition. The shift can be progressively larger for progressively lower or higher data states. In one example, under the first read condition, the read voltages of VrAL, VrBL, VrCL, and VrDL are optimal for the relatively low states of A, B, C, and D, respectively, and the VrEH, VrFH, and VrGH The read voltages are optimal for the relatively high states of E, F and G, respectively. Similarly, under the second read condition, the read voltages of VrAH, VrBH, VrCH and VrDH were optimal for the relatively low states of A, B, C and D, respectively, and the reads of VrEL, VrFL and VrGL The voltages are optimal for the relatively high states of E, F and G, respectively. Thus, in one possible implementation, at the first read condition for the lower state, the lower of the two read voltages per state is optimal, and at the first read condition for the higher state Under a read condition, the higher of the two read voltages per state is optimal.

The optimum read voltage is usually midway between the Vth distributions of adjacent data states. Accordingly, as the Vth distribution shifts, the optimum read voltage shifts.

The first read condition can occur when there is a long delay since the last program or read operation. An exemplary sequence is: program the block, wait an hour, then read the block. The first read condition can also occur when there is a power up/down. An exemplary sequence is: program the block, power up/down, then read the block. The first read condition can also occur when there is programming or reading of other blocks. An exemplary sequence is: program one block, program another block, then read the one block.

FIG. 8B illustrates exemplary bit sequences for lower, middle, and upper pages of data, and associated read voltages. In this case, the memory cells each store three bits of data in one of eight data states. Exemplary bit assignments for each state are depicted. The lower, middle, or upper bits can represent data for the lower, middle, or upper pages, respectively. In addition to the erased state Er, seven programmed data states A, B, C, D, E, F and G are used. Using these bit sequences, the data of the lower page can be determined by reading the memory cells using the read voltages of VrA and VrE (eg, control gate or word line voltages). Lower Page (LP) bit=1 if Vth<=VrA or Vth>VrE. LP=0 if VrA<Vth<=VrE. In general, the memory cells can be sensed by the sensing circuit while the read voltage is being applied. If the memory cell is in the conductive state at the sensing time, its threshold voltage (Vth) is less than the read voltage. If the memory cell is in a non-conducting state, its Vth is greater than the read voltage.

The read voltage used to read a page of data is determined by transitions from 0 to 1 or 1 to 0 in the encoded bits (codewords) of each state. For example, the LP bit transitions from 1 to 0 between Er and A, and from 0 to 1 between D and E. Accordingly, the read voltages of LP are VrA and VrE.

The data of the middle page can be determined by reading the memory cells using the read voltages VrB, VrD and VrF. If Vth<=VrB or VrD<Vth<=VrF, the middle page (MP) bit=1. MP=0 if VrB<Vth<=VrD or Vth>VrF. For example, the MP bit transitions from 1 to 0 between A and B, 0 to 1 between C and D, and 1 to 0 between E and F. Accordingly, the read voltages of MP are VrB, VrD and VrF.

The data of the upper page can be determined by reading the memory cells using the read voltages of VrC and VrG. If Vth<=VrC or Vth>VrG, the upper page (UP) bit=1. UP=0 if VrC<Vth<=VrG. For example, the UP bit transitions from 1 to 0 between B and C, and from 0 to 1 between F and G. Accordingly, the read voltages of UP are VrC and VrG. The read voltages are depicted as VrA, VrB, VrC, VrD, VrE, VrF and VrG, where each of these voltages can represent a first read value or a second read value, whichever is best.

FIG. 9 illustrates waveforms of an exemplary programming operation. The horizontal axis depicts the programming loop (PL) number, and the vertical axis depicts the control gate or word line voltage. In general, a programming operation may involve applying a pulse train to a selected word line, where the pulse train contains multiple programming loops or program-verify iterations. The program portion of the program-verify iteration includes program voltages, and the verify portion of the program-verify iteration includes one or more verify voltages.

In one approach, each programming voltage contains two steps. Additionally, Incremental Step Pulse Programming (ISPP) is used in this example, where the programming voltage is stepped up using a fixed or varying step size in each successive programming loop. This example uses ISPP in a single programming pass that completes programming. ISPP can also be used in each programming pass in a multi-pass operation.

Waveform 900 includes a series of programming voltages 901, 902, 903, 904, 905, ... 906 that are applied to word lines selected for programming and to associated sets of non-volatile memory cells. As an example, one or more verify voltages may be provided after each programming voltage based on the target data state being verified. 0V may be applied to the selected word line between program and verify voltages. For example, after each of the programming voltages 901 and 902, the A-state and B-state verify voltages (waveform 910) of VvA and VvB, respectively, may be applied. Following each of the programming voltages 903 and 904, the A-state, B-state and C-state verify voltages of VvA, VvB and VvC may be applied (waveform 911). After several additional programming loops (not shown), the E-state, F-state and G-state verify voltages of VvE, VvF and VvG (waveform 912 ) may be applied after the final programming voltage 906 .

10A depicts a graph of exemplary waveforms in a programming operation showing upward coupling of word line voltages. The time period shown represents one program-verify iteration. The horizontal axis plots time, and the vertical axis plots word line voltage Vwl. The programming voltage 1000 is applied to the selected word line from t0-t4 and reaches the magnitude of Vpgm. The programming voltage can be temporarily suspended at an intermediate level such as Vpass to avoid a single large transition that may have undesired coupling effects. A pass voltage 1005 is applied to the unselected word lines from t0-t19, and reaches a magnitude of Vpass, which is high enough to provide cells in a conductive state so that a sensing (eg, verify) operation can be performed for cells of the selected word lines occur. The pass voltage includes a rising portion, a fixed amplitude portion (eg, at Vpass), and a falling portion. Alternatively, the pass voltage may rise faster relative to the programming voltage to reach Vpass at t0.

A verify voltage 1010 is applied to the selected word line. In this example, all seven verification voltages are applied, one after the other. An eight-level memory device is used in this example. The verification voltages of VvA, VvB, VvC, VvD, VvE, VvF and VvG are applied at t8, t9, t10, t11, t12, t13 and t14, respectively. The sensing circuit may be activated during each verification voltage. From t15-t16, the waveform decreases from VvG to 0V or other steady state level.

For unselected word lines, a drop on Vpass will cause the cell to transition from a conducting state to a non-conducting state. In particular, when Vpass falls below the cutoff level Vcutoff (dotted line at t18), the channel of the cell will become cutoff, eg, the cell will become non-conductive. When the cell becomes non-conductive, it acts as a capacitor, where the control gate is one plate and the channel is the other plate. The cell becomes non-conductive when Vcg<Vcutoff or Vcg<(Vth+Vsl), where Vcg is the cell's control gate voltage (word line voltage), Vth is the cell's threshold voltage, and Vsl is the source line voltage, The source line voltage in turn is approximately the voltage at the source terminal of the cell. For cells in the highest programmed state (eg, G-state), Vth can be as low as VvG (or lower due to post-program charge loss), and is comparable to the upper portion of the G-state in Vth distribution 827 in Figure 8A or 827a The Vth at the tail is as high. Vcutoff can thus be as low as VVG+Vsl or as high as Vth+Vsl in the upper tail of the G state. As the pass voltage 1005 decreases from Vcutoff to 0V, the channel capacitively couples down a similar amount, as shown by curve 1015 in Figure 10B.

When Vsl is larger, the voltage swing will be larger when the channel is turned off. However, since Vch=Vsl, the minimum down-coupling level of Vch will be substantially independent of Vsl. For example, a 6V swing on the wordline voltage (eg, Vcutoff=6V) with Vsl=1V will result in approximately the same 5V swing on the wordline voltage (eg, Vcutoff=5V) with Vsl=0V Minimum down-coupling level for Vch.

Curve 1012 represents the upward coupling of word line voltages from t19-t20. The up-coupling is shown to occur relatively quickly, but this is not to scale. In practice, the verify operation (eg, from t5-t19) may consume about 100 microseconds, while the upward coupling of the word lines may be significantly longer, in the millisecond range, such as 10 milliseconds.

FIG. 10B shows a graph corresponding to the channel voltage (Vch) of FIG. 10A. For unselected memory strings (strings that do not have cells programmed in the current programming loop), Vch will be boosted to a level such as 8V (not shown) during the programming voltage, eg, from t0-t4. This boosting is accomplished by providing the SGD and SGS transistors of the unselected strings in a non-conducting state to float Vch. When Vpass and Vpgm are applied to the word line, Vch is coupled higher due to capacitive coupling. For the selected memory string (string with cells being programmed in the current programming loop), Vch is typically grounded, as shown during the programming voltage.

During the verify voltage, Vch may, for example, be initially at about 1V for the selected memory string. For the channel of the selected memory string, Vch is about the same as Vsl. Vsl is set based on the type of sensing used. Examples include negative sense where Vsl is about IV, and positive sense where Vsl is about 0V and uses a negative word line voltage. The techniques described herein apply regardless of the level of Vsl or the type of sensing used.

The channel is capacitively coupled down to the lowest level from t18-t19, and then returns to a final level, eg, 0V, starting from t19-t20. If the voltage of the word line is allowed to start to float at t19, the voltage (curve 1012) is capacitively coupled higher by the rise in Vch. The voltage of the word line is floated to the peak level Vwl_coupled_up, thereby reaching the second read condition. For example, Vcutoff may be 6V, such that there is a 6V change (eg, 6-0V) in the word line voltage, which is coupled to the channel. In the case where the initial value of Vch is 1V and the coupling ratio is 90%, the minimum Vch may be, for example, about 1-6×0.9=−4.4V. Accordingly, there is a 4.4V boost on Vch, which is coupled to the word line, eg, the control gate of the cell. Vwl_coupled_up may be about 4.4×0.9=4V. By disconnecting the word line from the word line driver, the voltage of the word line is floated.

10C depicts a graph of exemplary waveforms in a read operation showing upward coupling of word line voltages. The read operation is similar to the verify operation in that both are sense operations and can provide upward coupling of word line voltages. The horizontal axis plots time, and the vertical axis plots word line voltage Vwl. Pass voltages 1115, 1116 and 1117 are applied to unselected word lines from t0-t3, t4-t8 and t9-t12, respectively, and have a magnitude of Vpass. The pass voltage includes a rising portion, a Vpass portion, and a falling portion. For each of the lower, middle and upper pages, the read voltages contain separate waveforms 1120 (at the levels of VrAH and VrEL), 1121 (at the levels of VrBH, VrDH and VrFL) and 1122 (at the levels of VrCH), respectively and VrGL levels), consistent with Figures 8A and 8B. As an example, the read voltage is optimized for the second read condition and applied to the selected word line. An eight-level memory device is used in this example.

For unselected word lines, a drop on Vpass will cause the cell to transition from a conducting state to a non-conducting state, as discussed. The dotted line at t13 indicates when the G-state cell becomes non-conductive. As pass voltage 1117 decreases from Vcutoff to 0V, the channel capacitively couples down a similar amount, as represented by curve 1035 in Figure 10D. As the channel voltage rises after t14, the word line voltage floats and couples higher to Vwl_coupled_up.

FIG. 10D shows a graph corresponding to the channel voltage (Vch) of FIG. 10C. The channel is capacitively coupled down to the lowest level of Vch_min from t13-t14, and then returns to a final level, eg, 0V, starting from t14-t15. If the voltage of the word line is allowed to float starting at t14, the voltage (curve 1032) is capacitively coupled higher by the rise on Vch (curve 1035). The voltage of the word line is floated to the peak level of Vwl_coupled_up, as discussed.

FIG. 10E depicts the waveform of FIG. 10C showing the decay of the up-coupled voltage of the word line. The time scales are different from those in Figures 10A-10D and represent longer periods of time, such as one or more hours. Curve 1123 depicts the read voltage in time period t0-t1 (corresponding to waveforms 1120-1122 in FIG. 10C). Curve 1123a depicts the pass voltage (corresponding to waveforms 1115-1117 in Figure 10C). Curve 1125 depicts the rise of Vwl to the up-coupled level (Vwl_coupled_up) due to coupling (during time periods t1-t2), and the subsequent decay of Vwl over time periods t2-t3. Overall, the rise in Vwl occurs relatively quickly compared to the decaying time period.

Figure 10F shows a graph of the channel voltage according to Figure 10E. In the time period t1-t2, the decrease is followed by the increase (curve 1126). Vch is about 0V from t2-t3 (curve 1127).

Figure 10G depicts a graph of the Vth of a memory cell connected to an upwardly coupled word line, consistent with Figures 10E and 10F. For a cell in an exemplary data state such as the A state, from t0-t1, Vth is at the initial level Vth_initial. This represents the first read condition. Vth rises from t1-t2 (curve 1128) to the peak level of Vth_coupled_up due to the simultaneous coupling with the rise on Vch. This represents the second read condition. Vth then gradually decreases back to Vth_initial from t1-t3.

FIG. 11A depicts the control gate voltage and channel voltage on a memory cell that acts as a capacitor when the control gate voltage drops in a sensing operation. The first read problem is caused by the stacking of word line planes or layers in 3D, where the channels of the memory cells are floating and not coupled to the substrate as in 2D flash NAND architectures. Word line coupling and electron trapping in oxide-nitride-oxide (ONO) layers are the source of the first read problem.

As discussed, after a read/verify operation, when the read pass voltage (Vpass) applied to the word line ramps down, when Vpass drops to 5V, the G-state cell (eg, with a Vth of 5V) Turn off the channel. As Vpass drops further to Vss, the floating channel potential is pushed down to a negative value. Next, after the read operation ends, the negative voltage (about -4.5V) in the channel shown above rises by attracting positive charges. Since the data word lines are floating, the amount of holes required to charge the channel is relatively small, so selected and unselected word lines can quickly couple up to about 4V (assuming a 90% coupling ratio). The potential on the word line remains at about 4V for some time. This attracts and traps electrons in the tunnel ONO layer and results in an upward or downward shift in Vth for lower or higher data states, respectively. Since the word line is coupled to the floating channel potential, the word line voltage thus rises to about 4V after the read operation.

The top plate represents the control gate or word line, and the bottom plate represents the channel. Capacitor 1040 represents the memory cell when the word line voltage drops from 8V (Vpass) to 5V (Vcutoff, such as VvG or slightly higher) and Vch=0V. Capacitor 1042 represents the memory cell when the word line voltage reaches 0V, so that Vch is coupled down to about -4.5V. Capacitor 1044 represents the memory cell when the associated word line voltage begins to float. Capacitor 1046 represents the memory cell when the associated word line voltage reaches Vwl_coupled_up under the second read condition. If the Vth of the memory cell is less than 4V (eg, the cell is in an erased state or a less programmed state), the memory cell will be weakly programmed, causing its Vth to rise. If the Vth of the memory cell is greater than 4V (eg, the cell is in a higher programmed state), the memory cell will be weakly erased, causing its Vth to drop. Capacitor 1048 represents a memory cell after a long period of time (eg, an hour or more) has elapsed so that the word line has discharged to the first read condition.

When the data word line voltage is floating, the amount of holes required to charge the channel is relatively small. Thus, as an example, a selected word line may be coupled up to about 4V relatively quickly. The potential on the selected word line is maintained at about 4V for one end time, attracting trapped electrons in the tunnel oxide-nitride-oxide (ONO) layer and shifting Vth upward. If the wait is long enough before the next read operation, the up-coupled potential of the word line will discharge and the trapped electrons will be released. The first read condition will occur again.

FIG. 11B depicts a portion of the memory cell MC of FIG. 6 showing injection of electrons into the charge trapping region during weak programming. The memory cell includes control gate 694, metal barrier 661a, blocking oxide 660a, charge trapping layer 663, tunneling layer 664, channel 665, and dielectric core 666. Due to the elevated word line voltage, an electric field (E) is created, which attracts electrons (see example electron 1050) into the charge trapping layer, raising Vth. This weak programming can be caused by the Poole–Frenkel effect, where electrical insulators can conduct electricity. This is a kind of tunneling through trapped electrons. Weak erasing similarly involves an electric field, which repels electrons from the charge trapping layer, lowering Vth.

FIG. 12A illustrates the configuration of an example memory string 1200 just before the word lines are discharged at the end of the sensing operation. For example, this is just before the word line voltage starts to ramp down from Vpass, eg, at t17 in Figure 10A and t12 in Figure 10C. As mentioned, the first read problem is caused by high Vth cells (eg, G-state cells) turning off the channel during discharge of the word line. Vch is coupled down through the discharge word line. Then, holes enter the channel to neutralize the channel voltage, eg, Vch rises from a negative voltage to about 0V. For example, this boost couples the word line voltage up to about 4V. This elevated word line voltage eventually results in electron trapping in the interface between the tunnel oxide and polysilicon tunnel, and charge redistribution in the charge trapping layer of the memory cells, raising the Vth of some of the cells to the second read condition. After some time has elapsed, such as one or more hours, or if the word line is exposed to the steady state voltage for a period of time, the word line will eventually discharge back to about 0V. This discharge is due to current passing through the SGS transistor and leaking into the substrate. The unit then returns to the first read condition. The optimal read level varies based on whether the cell is in the first read condition or the second read condition (or somewhere in between). If the read level is optimized for the first read condition and the second read condition exists, or if the read level is optimized for the second read condition and the first read condition exists, this will result in a large number of reads Take error.

Memory string 1200 extends between p-well 1205 and bit line 1202 and includes memory cell control gates 1211, 1212, 1213, ..., 1214 and 1215 between SGS transistor control gate 1210 and SGD transistor control gate 1216 . The strings include channel regions 1204 within the memory thin film layer 1203 (eg, a tunneling layer within the charge trapping layer). A central dielectric core 1201 is also depicted. Strings are shown in cross-section with control gates and layers surrounding the memory holes. Also, as an example, the memory cells with control gates 1211 and 1215 are programmed to the G state (the highest state in this example), and the memory cells with control gates 1212-1214 are in any state.

The SGD control gates are at a voltage of Vsgd (eg, 3-4V), the memory cell control gates 1211-1215 are at a voltage of Vpass (eg, 8-10V), and the SGS control gates are at a voltage of Vsgs (eg, 3-4V) ), the p-well can be at 1V (Vsl) and the bit line can be at 1-2V. Exemplary electrons ("e-") enter the channel from the bit line as the sensing circuit is activated for the sensing operation. This results in a channel voltage of about 0V. During the discharge or ramp-down of the word line, the G-state cell turns off (becomes non-conductive), allowing the channel voltage to float and couple down, as mentioned.

Figure 12B illustrates the configuration of an example memory string just after the word lines are discharged at the end of the sensing operation. At this time, the channel voltage is negative (Vch<0V), as represented by the reduced number of electrons, and each of the control gates reaches 0V. The bit line voltage can also be set to 0V.

12C illustrates an example memory string configuration when word lines are coupled up through channels. The negative channel voltage causes a lateral field across the SGS transistor, which causes holes to gradually enter the channel from the p-well. The holes will neutralize and combine with the electrons across the field of the SGS transistor, gradually increasing the channel voltage towards 0V. At this point, the word line voltages are floating so that they couple up as Vch rises. This is indicated by the flag "float higher".

Figure 12D illustrates the configuration of an example memory string when the word lines have been coupled up. In this case, the channel is completely neutralized such that Vch=0V. As an example, the word line voltage is at an up-coupled level of about 4V.

Figure 13A illustrates an exemplary process according to block 10 in Figure 1C. This feature involves detecting the up-coupling state of the word line and setting the read voltage accordingly. Step 1300 includes receiving a read command for a selected memory cell in a block (eg, connected to a selected word line). For example, commands may be received at controller 122 from a host. In other cases, the read command is generated internally within memory device 100 (FIG. 1A). Step 1301 includes sensing the word line voltage in the block. In one approach, the sensed word line is predetermined in the block and does not have to be the same as the selected word line connected to the selected memory cell. Sensing of one or more word lines is possible. For example, a voltage detector may be configured to perform an evaluation of the voltage of one or more word lines. For further exemplary details, see Figure 24B. Step 1302 includes selecting a read voltage set based on the sensed word line level. The sensed word line level indicates whether the memory cell is in the first read condition or the second read condition, or somewhere in between. See, eg, Figures 13B-13D. Step 1303 includes performing a read operation in the block using the selected set of read voltages. In this method, the optimal set of read voltages that minimize read errors can be selected based on the current up-coupling state of the word lines.

Figure 13B shows a graph of the shift of Vth versus time for different data states. As mentioned, under the first read condition, a downward shift in Vth is seen for one or more lower states, substantially no change in Vth is seen for one or more mid-range states, and for One or more of the higher states can see an upward shift in Vth. These shifts are relative to the Vth level under the second read condition.

Time t=0 represents the time of the sensing operation when the cell is in the first read condition. The magnitude of the shift in the read voltage is greatest at this time because the word line is discharged and the Vth of the cell is relatively far from the Vth of the second read condition for each programmed data state. The shift gradually decreases in magnitude as time continues from 0 to tf. In one approach, a shift of 0V can be achieved at tf. Separate curves are provided for the programmed states labeled A, B, C, D, E, F and G, with the curves for A, B, C, D showing a downward shift, and the curves for E, F and G An upward shift is shown. This example shows eight data states, but similar trends can be seen for other numbers of data states.

13C depicts a graph showing the trend of read voltage versus detected word line voltage. The horizontal axis depicts the word line (WL) voltage, which can be sensed using a circuit such as that shown in Figure 24B. The vertical axis depicts the read voltages according to FIG. 8A, including lower and higher read voltages for each programmed data state. The graph shows that the read voltage increases with the sensed WL voltage for lower data states, and decreases with the sensed WL voltage for higher data states.

Figure 13D depicts a graph of read voltage versus detected word line voltage, where two sets of read voltages are used in the exemplary embodiment of Figure 13C. In a simplified embodiment, the sensed WL voltage is classified into one of two ranges: below a reference voltage (Vref) or above Vref. If the sensed WL voltage is higher than Vref, the read voltages VrAH, VrBH, VrCH, VrDH, VrEL, VrFL and VrGL are selected. If the sensed WL voltage is lower than Vref, the read voltages VrAL, VrBL, VrCL, VrDL, VrEH, VrFH and VrGH are selected. In one approach, Vref may be selected based on the maximum up-coupled word line voltage. For example, if the maximum up-coupled word line voltage is about 4V, then Vref can be about half that, or 2V.

Figure 13E illustrates another exemplary process in accordance with block 10 in Figure 1C. As an alternative to Figure 13A, this process involves periodic polling of blocks to determine their word line voltages. This process is useful because it can store data entries for word line voltages before receiving a read command. When a read command is received, the appropriate read voltage can be determined immediately without performing another word line voltage detection. It can be checked whether the detected word line voltage is recent enough to be reliable in selecting a read voltage.

Step 1310 includes sensing the word line voltage according to the timer. For example, this can be done periodically, eg every few minutes or hours. Step 1311 includes storing the data entry for the word line voltage. If no read command is received before the next sensed time, steps 1310 and 1311 are repeated. If a read command for the block is received at step 1312, decision step 1313 determines whether the data entry is recent, eg, not older than a specified amount of time. If decision step 1313 is true, step 1314 selects a read voltage set based on the data entry, and step 1315 performs a read operation on the block using the read voltage set. The process then continues at step 1310. If decision step 1313 is false, step 1316 repeats the sensing of the word line voltage, step 1317 stores a new data entry for the word line voltage, and step 1318 resets the timer. Steps 1314 and 1315 are then reached.

Optionally, decision step 1313 is omitted so that the most recent entry is always used to select the read voltage. The period of word line detection can be set short enough so that the latest entry is valid.

Figure 14A illustrates an exemplary process according to block 11 in Figure 1C. This feature involves applying a pre-read voltage pulse just before the read operation. Step 1400 includes receiving a read command for a selected memory cell in a selected block (eg, connected to a selected word line). Decision step 1401 determines whether the conditions for applying a pre-read voltage pulse to the selected word line are met. Various data inputs can be considered for this decision step. For example, block 1401a indicates whether the elapsed time since the last sensing of the block exceeds a threshold. The threshold may be long enough so that if the elapsed time exceeds the threshold, the cell will be in the first read condition. The condition may be satisfied if an input to block 1401a is received. Block 1401b indicates whether a previous read of the block resulted in one or more uncorrectable errors. This previous read may be associated with a read command other than the previous read command involved in step 1400 . A read recovery process may have been used to read the data in response to one or more uncorrectable errors in the previous read. The condition may be satisfied if an input to block 1401b is received.

The control circuit may be configured to cause the voltage detector to perform the evaluation in response to determining that a previous read of the memory cells in the block resulted in one or more uncorrectable errors.

Block 1401c indicates whether the word line voltage in the block is below a threshold. The threshold may be low enough that if the word line voltage is below the threshold, the cell will be in the first read condition. The word line voltage may be sensed using the techniques discussed with respect to Figures 13A and 24B. The condition may be satisfied if an input to block 1401c is received.

If decision step 1401 is true, step 1402 includes applying a pre-read voltage pulse to the selected word line, and step 1403 includes reading the selected memory cell. See Figures 15A and 15B. In one embodiment, the pre-read voltage pulse is applied to the selected word lines in the selected block but not to the remaining, unselected word lines. In another embodiment, the pre-read voltage pulses are also applied simultaneously to some or all of the unselected word lines. Pre-read voltage pulses provide weak or soft programming of cells, especially those in lower programmed states. The pulse creates an electric field across the cell which causes some charge trapping and thus some rise in Vth proportional to the duration and amplitude of the pulse. Depending on the pulse amplitude and duration, the pulse may not raise Vth for cells in the higher state.

In one option, step 1402a includes setting the duration of the pre-read voltage pulse to a fixed duration. The amplitude of the pre-read voltage pulse can also be set to a fixed amplitude. In another option, step 1402b includes setting the duration of the pre-read voltage pulse based on the elapsed time. The amplitude of the pre-read voltage pulse can also be set based on the elapsed time. See Figure 15C. Step 1402c includes setting the duration of the pre-read voltage pulse based on the detected word line voltage. The amplitude of the pre-read voltage pulse may also be set based on the detected word line voltage. See Figure 15D. Step 1402d includes setting the duration of the pre-read voltage pulse based on the temperature. The amplitude of the pre-read voltage pulses may also be set based on the sensed temperature. See Figure 15E.

If the read voltage is optimized for the second read condition, the pre-read voltage pulse helps to boost the Vth of the cell back to the second read condition before reading the cell.

Figure 14B illustrates another exemplary process according to block 11 in Figure 1C. In this case, no pre-read voltage pulses are applied unless there are one or more uncorrectable errors of the initial read. Step 1410 includes receiving a read command for the selected memory cell. Step 1411 includes reading the selected memory cells. In one approach, a default read level optimized for the second read condition is used. Decision step 1412 determines whether there are one or more uncorrectable errors, eg, whether the ECC process cannot correct all read errors. If the decision at step 1412 is false, then at step 1417 the reading process is performed. If decision step 1412 is true, step 1413 includes applying a pre-read voltage pulse to the selected word line. Step 1414 then reads the selected memory cells again, and decision step 1415 determines if one or more uncorrectable errors remain. If the decision at step 1415 is false, then at step 1417 the read process is performed. If decision step 1415 is true, step 1416 involves performing a read recovery process. This may involve repeated read attempts, where the read voltage is shifted higher and/or lower.

Optionally, if decision step 1415 is true, a second pre-read voltage pulse may be applied. The amplitude and/or duration of the second pre-read voltage pulse may be greater than the amplitude and/or duration of the first application of the pre-read voltage pulse.

If the word line voltage is floated long enough, an initial read that results in an uncorrectable error will have some effect on coupling the word line voltage up. However, this would unduly prolong the read operation time. Soft programming of the pre-read voltage pulse acts more rapidly than word line upward coupling on the rise of the cell's Vth. Additionally, the pre-read voltage pulses can be applied to selected word lines rather than all word lines in the block.

15A depicts a graph of exemplary waveforms in a read operation similar to that of FIG. 10C in which a pre-read voltage pulse is applied prior to the read operation. The waveforms 1115-1117 and 1120-1122 of Figure 1OC are repeated. A pre-read voltage pulse is applied just before the read waveform (curve 1500). As an example, the pre-read voltage pulse may have an amplitude of Vpass. In general, pulses of higher amplitude and/or longer duration will have a greater impact on the Vth rise of the cell. The pre-read voltage pulse begins to ramp up at t0a and begins to ramp down at t0b, for example in response to a read command, such that the duration is t0b-t0a. After it ramps down to 0V, for example, a read operation starts at t0. The delay between the pre-read voltage pulse and the read operation can be minimized to minimize the overall read time. The pre-read voltage pulse helps boost the Vth of the cell before reading the cell to reduce read errors. Up-coupling of the word lines after a read operation may also be performed, as indicated by curve 1032 .

Curve 1500a shows the option of pre-reading voltage pulses, which can reduce power consumption. In this example, the ramp-up rate of the pre-read voltage pulse may be less than the ramp-up rate of the subsequent pass voltage during the read operation.

FIG. 15B shows a graph corresponding to the channel voltage (Vch) of FIG. 15A. Curve 1035a corresponds to curve 1035 of Figure 1OC.

Figure 15C depicts a plot of pre-read voltage pulse duration and/or amplitude versus time since the last sensing operation according to step 1402b of the process of Figure 14A. This can be the time since the last read operation or program operation including a verify test. The duration and/or amplitude increases with time because the pre-read voltage pulses help increase the Vth of the memory cell, which decreases with time due to the discharge of the word line voltage. The effect of the pre-read voltage pulse is stronger when the duration is longer and/or the amplitude is stronger. As an example, the duration may be about 0.1 milliseconds to 200 milliseconds.

15D depicts a plot of pre-read voltage pulse duration and/or amplitude versus detected word line voltage according to step 1402c of the process of FIG. 14A. The duration and/or magnitude increases as the detected WL voltage decreases, as the lower WL voltage indicates that the word line voltage has discharged and the cell is at (or close to) the first read condition. A stronger (longer or larger amplitude) pre-read voltage is thus indicated to help the memory cell's Vth rise back to the second read condition.

Figure 15E depicts a graph of pre-read voltage pulse duration and/or amplitude versus temperature according to step 1402d of the process of Figure 14A. That is, pulse duration and/or amplitude is inversely proportional to temperature. The temperature sensor 115 of FIG. 1A may be used to determine temperature. In general, at lower temperatures we need longer pulse durations and/or amplitudes. In the case of pre-read (which occurs just before the read operation), we expect to use a pre-read pulse to trap electrons so that the memory cell enters the second read state. The time required to capture electrons and transition the memory cell from the first read state to the second read state increases at lower temperatures. One mechanism is thought to involve hopping between capture sites, which is slower at lower temperatures. Thus, longer pulse durations and/or amplitudes are preferred at lower temperatures.

Figure 15F plots error counts versus programming pulse width on a log-log scale according to the process of Figure 14A. The graph is obtained by reading the cells in the first reading condition. It can be seen that if the pulse duration is short (such as a few nanoseconds), it does not reduce the error count significantly, and the error count is expected to be as when the cell is in the first read condition. However, as the pulse duration increases (such as to a few milliseconds), the error count decreases significantly to the same level as when the cell is in the second read condition. In this example, the read voltage is optimized for the second read condition.

Figure 16A illustrates an exemplary process according to block 12 in Figure 1C. This feature includes periodically applying voltage pulses to all word lines in the block. This process can use voltage pulses similar to the pre-read voltage pulses. In one approach, this process may apply voltage pulses to all word lines in one or more blocks, rather than only to selected word lines. The process can be executed independently of the read command. Commands can be defined in the controller that cause pulses to be issued periodically. In one approach, when a command is executed, the voltage drivers and associated pass gates (FIGS. 24A and 24B) are configured to simultaneously apply voltage pulses to all word lines in one or more blocks. Another approach is to apply voltage pulses simultaneously to one or more word lines in one or more blocks.

It is also possible to stagger the voltage pulses within a die so that they are applied to different sets of blocks at different times. This reduces peak current consumption. For example, if the blocks are arranged in multiple planes (eg, different p-well regions of the substrate), the pulses may be applied to the blocks in one plane at a time. Alternatively, depending on the memory device architecture, the pulses may be applied to portions of blocks in one plane at a time. The pulses may be applied to one block set at a time, where each set includes one or more blocks.

In another option to reduce peak current consumption, as shown in Figure 25, the voltage pulses may be staggered across multiple dies in a multi-die memory device.

Furthermore, by setting Vbl=Vsource when the SGS and SGD transistors are in the conductive state, the current consumption can be reduced. This will tend to prevent current from flowing in the string since both ends of the string are at the same potential. Another approach is to turn off either the SGD or SGS transistors (but not both) so there is no current flow through them. One of the SGS or SGD transistors should be conductive so that the channel voltage is not floated.

The pulses may be issued periodically, such as about every few minutes or every hour. The term "periodic" is meant to encompass fixed intervals as well as varying intervals. With the word line already starting to discharge, the pulse returns the block to the second read condition. The pulses can be implemented without keeping track of whether the block is in the first read condition or the second read condition. In some cases, the block may already be in the second read condition when the pulse is applied due to recent sensing operations. In this case, the pulses may have little or no effect. In other cases, the block may be at or close to the first read condition. In this case, the pulse can have a significant effect on returning the block to the second read condition. In one approach, the periodic emitting of pulses may begin in response to a power-up event in the memory device. This event forces all word lines to 0V and enters the first read condition.

Step 1600 starts a timer. At step 1601, the timer continues to count. Decision step 1602 determines whether the timer has counted to the specified period. Block 1602a indicates that the period may be adjusted based on the temperature, eg, so that the period is shorter when the temperature is higher. See Figure 16D. If it is determined that step 1602 is false, step 1601 is repeated and the timer continues to count. If decision step 1602 is true, step 1603 resets the timer, and step 1604 includes using a voltage pulse to refresh the memory cells in one or more blocks. Refreshing involves raising the Vth of at least the lower state cells back to the second read condition. Block 1604a indicates that the duration and/or amplitude of the voltage pulse may be adjusted. For example, adjustments may be made based on time since last sensing, WL voltage, and temperature, as discussed with respect to Figures 15C-15E, respectively.

Figure 16B depicts a graph of periodic voltage pulses according to the process of Figure 16A. The vertical axis plots voltage and the horizontal axis plots time. Exemplary pulses 1610 , 1620 and 1630 have a duration represented by arrow 1625 and a period represented by arrow 1626 . Between pulses, the word line voltage can couple up and begin to decay, as shown by curves 1611, 1621 and 1631. Other operations involving the application of voltages to word lines, such as read and program operations, may occur between periodic voltage pulses. In the example provided, each voltage pulse has a common duration. In another approach, the duration can vary. Furthermore, in the examples provided, a common period (eg, time between pulses) is used to provide the voltage pulses. In another approach, the period can vary.

Figure 16C shows a graph of the channel voltage according to Figure 16B. The channel voltage can be coupled lower and then raised, resulting in upward coupling of the word lines, as discussed. For example, pulse 1610 ramps up at t0 and ramps down at t1 , resulting in a downward spike in Vch as shown by curve 1616 . Pulse 1620 ramps up at t3 and ramps down at t4, resulting in a downward spike in Vch as shown by curve 1627. Pulse 1630 ramps up at t6 and ramps down at t7, resulting in a downward spike in Vch as shown by curve 1636. The word line voltages start to couple up at t2, t5 and t8.

Figure 16D depicts a graph of pulse period versus temperature according to block 1602a of Figure 16A. As mentioned, the period can be shorter when the temperature is higher. High temperature represents the worst case, where the discharge rate of the word line is the largest. In one method, for example, the period is set to a few minutes (eg, 1-10 minutes) for temperatures above room temperature, and 1-2 hours for room temperature or lower temperatures.

Figure 17A illustrates an exemplary process according to block 13 in Figure 1C. This feature involves performing a soft erase just after a read or program operation (block 13). As mentioned, after a sensing operation (eg, a read or verify test), if the word line voltage is floated, the word line voltage is coupled up through the channel. Step 1700 includes receiving a read or program command for a selected memory cell in a block (eg, connected to a selected word line). Step 1701 includes performing a read or verify of the selected memory cells. A verify operation is performed with respect to, for example, a program operation as discussed with respect to FIG. 9 . Step 1702 includes performing a soft erase of the block.

Before receiving a read command, the block is subjected to a normal erase operation such as shown in FIGS. 17B and 17C, followed by a program operation such as that shown in FIG. 9 . Before receiving a program command, the block is subjected to a normal erase operation.

17B depicts a graph of exemplary erase voltages applied to a substrate in a normal erase operation. The vertical axis depicts Verase, and the horizontal axis depicts the erase loop number. Verase has an initial amplitude of Vinit and steps up in amplitude in each successive erase loop. In this example, a total of three loops are used to complete the erase operation. Erase voltages 1711, 1712 and 1713 are applied in erase loops 1, 2 and 3, respectively. As an example, Verase is the voltage applied to the substrate (p-well) via the local interconnect. As an example, Verase can have amplitudes as high as 20-25V.

Figure 17C shows a graph of verify voltages applied to word lines in a block according to Figure 17B. The vertical axis depicts Vwl (word line voltage), and the horizontal axis depicts the erase loop number. An example erase verify voltage 1714 is depicted. For example, this voltage (VvEr) may have a magnitude close to 0V. Typically, an erase verify voltage is applied after each erase voltage as part of the erase verify test of the block.

18A illustrates the configuration of the exemplary memory string 1200 of FIG. 12A when holes are introduced from the substrate into the channel and the channel undergoes initial neutralization in a soft erase operation, according to step 1702 of FIG. 17 . After the configuration of Figure 12A, the p-well voltage is raised to 5V, eg, allowing holes ("h+") from the substrate to enter the channel to begin neutralizing the channel voltage. See also Figures 19A-19D. The control gate of the SGS transistor may, for example, be set to 0V, so that the transistor is in a conductive state for holes.

Electrons begin to combine with holes, as indicated by the reduced number of electrons compared to Figure 12A. During this time, the word lines can be driven at 0V so that they are not coupled up. The control gate of the SGD transistor can also be driven at 0V. This process is called soft erase because it is similar to what happens in a normal erase operation, but to a lesser extent. For example, in a normal erase operation, such as shown in Figures 17B and 17C, the p-well can be raised to a much higher voltage of 20-25V, as an example. A normal erase operation provides a sufficiently high channel-to-gate voltage that drives electrons out of the cell's charge trapping layer and lowers the Vth of the programmed cell to the Vth level of the erased state. Typically, in a normal erase operation, cells are erased in multiple iterations. Each iteration involves applying a p-well voltage, followed by performing a verify test using the verify level VvEr (FIG. 8A). Soft erase differs in that the channel-to-gate voltage is not high enough to erase the cell. Furthermore, there is typically no validation test or use of multiple iterations. Furthermore, the duration of the erase voltage on the p-well may be less during soft erase than during normal erase. Soft erase provides a channel-to-gate voltage sufficient to neutralize the channel without erasing the memory cell.

In one approach, the magnitude of the soft erased p-well voltage is less than 25-50% of the magnitude of the normal erase, and/or the duration of the soft erased p-well voltage is less than 25-50% of the duration of the normal erase 50%.

Figure 18B illustrates the configuration of an exemplary memory string when the channel is fully neutralized in the soft erase operation according to step 1702 of Figures 17 and 18A. The channel is fully neutralized such that Vch=0V. The word line voltage is floated, but remains at about 0V because there is no upward coupling from the channel.

FIGS. 19A-19D illustrate exemplary waveforms in a read operation followed by a soft erase, consistent with FIG. 17 .

19A depicts a graph of exemplary waveforms in a read operation followed by a soft erase. FIG. 19B shows the channel voltage during soft erase. Figure 19C shows the SGS transistor voltage during soft erase. Figure 19D shows the p-well voltage during soft erase. The waveforms 1115-1117 and 1120-1122 of Figure 1OC are repeated. Soft erase occurs from t14-t16 as the p-well voltage Vp-well increases (curve 1930). For example, the word line is driven at 0V (a lower level than the pass voltage) during soft erase (curve 1033) so that the word line voltage does not float higher as Vch increases. Then, after t17, the word line voltage may float (curve 1034). Although the word line voltage is floating at this time, it does not float to a higher level because the channel voltage has reached an equilibrium condition (Vch=0V). Curve 1910 represents the channel voltage, which begins to couple down at t13 and gradually returns to 0V at t15. A time blank of t16-t15 is provided to ensure that the channel voltage has completed its transition before Vp-well ramps back to 0V from t16-t17. While sensing occurs, Vsgs (curve 1920) rises and ramps down to 0V at t12 when Vwl also ramps down.

Due to the relatively large capacitance of the p-well on the substrate, the time required to ramp up the Vp-well can be significant. Typically, the p-well extends below the block in the plane. Another type of soft erase, described next, uses gate-induced drain leakage (GIDL) from SGS and/or SGD transistors to introduce holes into the channel. This charges the channel faster to reduce the overall consumption of the soft erase process.

20A illustrates the configuration of an exemplary memory string just after the word line is discharged at the end of the sense operation, where the SGD and SGS transistor voltages are lowered using coupling in the soft erase operation according to step 1702 of FIG. 17 . In Figures 20A-20C, soft erase uses GIDL to shorten the soft erase time. GIDL soft erase involves biasing the SGS and/or SGD transistors of a string with negative gate-to-drain/source voltages. The magnitude of the GIDL hole current is larger when the magnitude of the negative gate-to-drain/source voltage is larger.

When negative voltages are not available to drive the SGS and/or SGD control gates directly with negative voltages in a memory device, adjacent word lines may be used to couple the SGS and/or SGD control gate voltages down to a negative level. In this case, the adjacent word lines may be non-data or dummy word lines. For example, control gate 1211 may represent a dummy word line such as WLD4, and control gate 1215 may represent a dummy word line such as WLD2 (see FIGS. 4 and 7A).

As depicted in Figures 21A-21D, the word line voltage may ramp down from its peak level of Vpass to an intermediate level VpassL before ramping down to a final level of 0V. As the word line voltage ramps down from Vpass to VpassL, the SGS and/or SGD control gate voltages ramp down from their peak levels to 0V. Subsequently, the SGS and/or SGD control gate voltages are floated (eg, disconnected from the voltage driver) so that when the word line voltage VpassL ramps down to 0V, they couple down to a negative level. For example, VpassL may be 4.5V, such that the SGS and/or SGD control gate voltages are coupled down to about -4V. See Figure 20B. The transition from VpassL to 0V provides a sufficient amount of down-coupling, while the transition from Vpass to 0V may provide excessive down-coupling to the SGS and/or SGD control gates. VpassL can be made relatively high to provide relatively more GIDL hole current.

Figure 20A shows how the SGS and/or SGD control gate voltages are floated lower from 0V while the dummy word line transitions from VpassL to 0V. The data word lines are driven at 0V to prevent changes due to coupling from the channel. The channel voltage is negative at this time.

20B illustrates the configuration of an exemplary memory string just after the word lines are discharged at the end of the sense operation, where a negative voltage driven is used to cause SGD and SGS in a soft erase operation according to step 1702 of FIG. 17 Transistor voltage drops. When negative voltages are available in the memory device, the SGS and/or SGD control gates can be driven directly with a negative voltage, such as -4V, rather than using the down-coupling process of Figure 20A.

As depicted in Figures 22A-22D, the word line voltage may ramp down from its peak level of Vpass to a final level of 0V. The SGS and/or SGD control gate voltage ramps down from its peak level to a negative level. The channel voltage is negative at this time.

20C illustrates an exemplary memory when holes are introduced into the channel from the SGD and SGS transistors using GIDL in step 1702 according to FIG. 17 and the soft erase operation according to FIG. 20A or 20B and the channel begins to neutralize String configuration. This configuration shows how holes are generated in the channel from the SGS and/or SGD transistors due to down-coupling or driving negative voltages with the proper biasing of these transistors. The channel voltage begins to neutralize, and then completely neutralizes, such as shown in Figure 18B.

Figures 21A-21D illustrate waveforms in a soft erase, where the SGS and/or SGD transistors are coupled down to a negative voltage to generate holes through GIDL, consistent with Figures 20A and 20C.

21A depicts a graph of exemplary waveforms in a read operation followed by a soft erase where the pass voltage ramps down to VpassL before ramping down to 0V, consistent with FIGS. 20A and 20C. Waveforms 1115 and 1116 and 1120-1122 of Figure 1OC are repeated. Waveform 1117a corresponds to waveform 1117, except that the word line voltage ramps down from t12-t14 to VpassL (intermediate level), between the peak level of Vpass and 0V. The word line voltage is held at VpassL from t14-t15 to ensure that the desired level is reached before t15 ramps down from VpassL to V. Curve 2110 indicates that the channel voltage couples down and then rises, as previously discussed.

This results in the down coupling of the SGS and/or SGD control gate voltages as shown when the word line voltage ramps down from VpassL to 0V at t15. The SGS and/or SGD transistors are now biased to generate holes in the channel due to GIDL so that the channel is charged and a soft erase of the memory cells in the block occurs from t15-t17. For example, the word line voltage is driven at 0V during soft erase (curve 2111). Then, after t18, the word line voltage can be floated (curve 2112).

FIG. 21B shows the channel voltage during one example of soft erase. Graph 2110 represents the channel voltage, which begins to couple down at t13 and gradually returns to 0V at t16. The time blank for t17-t16 is provided to ensure that the channel voltage has completed its transition before Vsgd/Vsgs is no longer floating but is driven back to 0V at t17.

21C illustrates SGS and/or SGD transistor voltages during one example of soft erase. The SGS and/or SGD control gate voltages (diagram 2120) ramp down to 0V from t13-t14a, and then float (as indicated by the broken line) from t14a-t17.

Figure 21D plots the p-well voltage during one example of soft erase. Vp-well (curve 2130) may remain at a level such as 1V before ramping down to 0V at t18 during soft erase.

Figures 22A-22D illustrate waveforms in a soft erase, where the SGS and/or SGD transistors are driven with negative voltages to bias the transistors to generate holes through the GIDL, consistent with Figures 20B and 20C.

22A depicts a graph of exemplary waveforms in a read operation followed by a soft erase. Compared to the soft erase of Figures 21A-21D, this soft erase process can be shortened in time because the pass voltage is not held at VpassL. The waveforms 1115-1117 and 1120-1122 of Figure 1OC are repeated. Waveform 2110 represents the channel voltage coupled down at t13 and then raised, as discussed previously.

From t13-t14, the SGS and/or SGD control gate voltage ramps down to a negative voltage, causing the SGS and/or SGD transistor to generate holes in the channel due to GIDL. The channel is charged and a soft erase of the memory cells in the block occurs from t14-t16. For example, during soft erase (curve 2211), the word line voltage is driven at 0V. Then, after t17, the word line voltage can be floated (curve 2212).

FIG. 22B depicts channel voltage during one example of soft erase. Curve 2210 represents the channel voltage starting to couple down at t13 and gradually returning to 0V at t15. A time margin of t16-t15 is provided to ensure that the channel voltage has completed its transition before Vsgd/Vsgs ramps back to 0V at t16.

22C illustrates SGS and/or SGD transistor voltages during one example of soft erase. The SGS and/or SGD control gate voltages (diagram 2220) ramp down to negative values from t13-t14 and then ramp up to 0V at t16.

22D depicts p-well voltages during one example of soft erase. Vp-well (curve 2230) may remain at a level such as 1V during soft erase before ramping down to 0V at t17.

FIG. 23 shows an exemplary block diagram of the sensing block 51 in the column control circuit of FIG. 1A . The column control circuit may include multiple sense blocks, where each sense block performs a sensing (eg, read) operation of multiple memory cells via a corresponding bit line.

In one approach, the sense block includes a plurality of sense circuits, also referred to as sense amplifiers. Each sense circuit is associated with a data latch and cache. For example, exemplary sensing circuits 2350a, 2351a, 2352a, and 2353a are associated with caches 2350c, 2351c, 2352c, and 2353c, respectively. In one approach, different corresponding sense blocks may be used to sense different subsets of bit lines. This allows the processing load associated with the sensing circuit to be divided and handled by the corresponding processor in each sensing block. For example, the sense circuit controller 2360 may communicate with a set (eg, sixteen) of sense circuits and latches. The sense circuit controller may include a precharge circuit 2361 that provides a voltage to each sense circuit to set the precharge voltage. The sensing circuit controller may also include a memory 2362 and a processor 2363.

Figure 24A illustrates an example circuit for providing voltage to a block of memory cells. In this example, row decoder 2401 provides voltages to the word lines and select gates of each block in block set 2410. A set may be in a plane and contain blocks BLK0 to BLK7. The row decoder provides control signals to pass gate 2422, which connects the block to the row decoder. Typically, operations (eg, program, read, or erase) are performed on one selected block at a time. A row decoder may connect global control lines 2402 to local control lines 2403 (word lines or select gate lines). Control lines represent conductive paths. Voltage is provided from voltage source 2420 on the global control line. The voltage source may provide the voltage to switch 2421, which is connected to the global control line. Control pass gate 2424 (also known as a pass transistor or pass transistor) passes the voltage from voltage source 2420 to switch 2421. As an example, voltage source 2420 may provide voltages on word lines (WLs), SGS control gates, and SGD control gates.

Various components including the row decoder may receive commands from a controller, such as state machine 112 or controller 122, to perform the functions described herein.

In normal erase or soft erase, the source line voltage source 2430 provides the erase voltage via control line 2432 to the source line/diffusion region (p-well) in the substrate. In one approach, the source diffusion regions 2433 are common to blocks. The set of bit lines 2442 is also shared by blocks. Bit line voltage source 2440 provides voltage to the bit lines. In one possible implementation, the voltage source 2420 is close to the bit line voltage source.

A word line voltage detector 2460 is connected to one of the word lines in each block. The voltage detector may include an operational amplifier comparator, such as shown in FIG. 24B, for example.

24B illustrates an exemplary circuit according to FIG. 24B for detecting word line voltages according to the process of FIG. 13A. The circuit includes a subset of the circuit of FIG. 24A as it relates to word line voltage detection in the exemplary block. The word line and select gate line (control line) of BLK0 are illustrated. connected to each control line through the gate. For example, through gate 2470 is connected to the SGD0 control line. The control gate through the gate is connected to common path 2471. When the voltage on the path is high enough, the control line is connected to the voltage driver via the row decoder 2401. When the voltage on the path is low enough, the control line is disconnected from the voltage driver and floats.

In this example, the word line voltage is obtained from WLL4 via conductive path 2473 connected to word line voltage detector 2460 when the control signal on line 2472 is high enough to conduct through gate 2412 . The word line voltage detector may include a comparator. The comparators respectively include a non-inverting input that receives the word line voltage Vwl, an inverting input that receives the reference voltage Vref, positive and negative power supplies +Vs and -Vs, and an output that provides Vout. If Vwl>Vref, then Vout=+Vs, and if Vwl<Vref, then Vout=-Vs. The analog output value can be provided to the controller, which converts the analog output value to 0 or 1 bits to indicate Vwl>Vref or Vwl<Vref, respectively. If bit = 0, the controller can select a read voltage set. If bit=1, the controller can select another set of read voltages. Furthermore, Vwl can be compared to different values of Vref to classify Vwl into more than two ranges. The corresponding set of read voltages may be selected based on the range into which Vwl is classified. See Figures 13C and 13D.

In one approach, a first comparison is made between Vwl and a reference voltage having a first level. Then, a second comparison is made between Vwl and a reference voltage having a second level based on the first comparison. For example, assume that Vref can be set to any of 1, 2, or 3V. The first comparison may use Vref=2V. If Vwl<2V, the second comparison can use Vref=1V. In this way, the detector can quickly classify Vwl into one of several ranges (eg, 0-1V or 1-2V) to allow a corresponding set of read voltages to be selected.

As an example, the voltage compared to Vref may be the full word line voltage Vwl or some portion of the word line voltage. The voltage detector can be in the peripheral area so that there is a considerable distance between the word line and the detector, resulting in RC delay. Another problem is that the word line in the floating state may have less capacitance than the conductive path 2473. These issues can be considered during the detection process. For example, a voltage of less than 2V at the detector may correspond to a voltage of 2V at the word line. The output of the detector may be taken at a specified time after the word line is connected to the detector via the pass gate 2412.

In general, it is sufficient to measure the voltage of one word line in a block. It helps to avoid the use of edge word lines (eg, WLL0 or WLL10), whose voltages may be affected by edge effects. In some cases, a block may be partially programmed such that some word lines at the bottom of the block (starting with WLL0) are programmed while other higher word lines are not. The programmed state of the cell should not significantly affect the word line voltage read.

Figure 25 illustrates a memory device 2500 in which voltage pulses are performed for a plurality of dies, one die at a time, according to the process of Figure 16A. Three memory dies 2510, 2520 and 2530 are provided as examples. Off-die control circuit 2502 determines that a voltage pulse is to be applied (such as as part of a pre-read operation), and in response, in one of the dies, such as die 2530, by providing a command to interface 2530d where the application of the voltage pulse is initiated. In response to the command, on-die control circuit 2530c instructs voltage driver 2531 to provide voltage pulses to row decoder 2530b, and instructs the row decoder to switch the voltage pulses from the voltage driver to word lines in array 2530a. As an example, the on-die control circuit may be the control circuit 110 of FIG. 1A . When the operation is complete for memory die 2530, it is reported back to the off-die control circuitry.

Off-die control circuitry may implement a short wait, such as 10 microseconds, before having the voltage pulse applied at die 2520. The off-die control circuitry provides commands to interface 2520d. In response to the command, on-die control circuit 2520c instructs voltage driver 2521 to provide voltage pulses to row decoder 2520b, and instructs the row decoder to switch the voltage pulses from the voltage driver to word lines in array 2520a. When the operation is complete for the memory die 2520, it reports back to the off-die control circuitry.

Ultimately, the off-die control circuitry provides commands to interface 2510d of die 2510. In response to the command, on-die control circuit 2510c instructs voltage driver 2511 to provide voltage pulses to row decoder 2510b, and instructs the row decoder to switch the voltage pulses from the voltage driver to word lines in array 2510a. When the operation is complete for the memory die 2510, it reports back to the off-die control circuitry.

As mentioned, the peak power consumption of the voltage driver is reduced because the voltage pulses are applied at one die at a time.

The foregoing detailed description of the present invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiment was chosen in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to optimize it in various embodiments and with various modifications as are suited to the particular use contemplated. The present invention is optimally utilized. The scope of the invention is intended to be defined by the appended claims.

Claims (9)

1. A device comprising: a block of memory cells (BLK0-BLK3); and A control circuit (110, 122) configured to, in response to a command to perform an operation involving sensing of selected memory cells of the bank, perform the operation, and after the operation, perform all of the memory cells soft erase of the block described above, where: the selected memory cells are arranged in a set (700n-703n, 710n-713n, 720n-723n, 730n-733n) of series-connected memory cells comprising unselected memory cells; each set of serially connected memory cells includes a channel (665); To perform the sensing of the selected memory cells, the control circuit is configured to sense voltages (VvA-VvG; VrA-VrG when a pass voltage is applied to unselected memory cells of the block ) applied to the selected memory cell; After the sensing of the selected memory cell, the control circuit is configured to drive the voltage of the unselected memory cell at a lower level than the pass voltage, resulting in down coupling of the channel ;and The control circuit is configured to perform the soft erase when the channel is coupled down. 2. The apparatus of claim 1, wherein: the memory cells are connected to a set of word lines (WLL0-WLL10) and are arranged in sets of memory cells connected in series (700n-703n, 710n-713n, 720n-723n, 730n-733n); each set of series-connected memory cells includes a channel (665), a source terminal (613), and a select gate transistor at the source terminal; the source terminal is in contact with the p-well (611b) of the substrate (611); and To perform the soft erase, the control circuit is configured to bias the p-well and the select gate transistors at the source terminals of the set of series-connected memory cells to divert holes from the p-well The well is passed into the channel. 3. The apparatus of claim 1 or 2, wherein: the memory cells are connected to a set of word lines (WLL0-WLL10) and are arranged in sets of memory cells connected in series (700n-703n, 710n-713n, 720n-723n, 730n-733n); each set of series-connected memory cells includes a channel (665), a source terminal (613), and a select gate transistor at the source terminal; the source terminal is in contact with the p-well (611b) of the substrate (611); and To perform the soft erase, the control circuit is configured to bias the select gate transistor with a negative gate-to-drain voltage. 4. The apparatus of claim 3, wherein: The control circuit is configured to perform normal erasing of the block of memory cells in response to an erase command of the block; To perform the normal erase, the control circuit is configured to bias the select gate transistor at the source terminal of the substrate and the set of series-connected memory cells for a first duration; and To perform the soft erase, the control circuit is configured for a second duration that is less than 25-50% of the first duration, and/or for a second duration that is less than that on the substrate during the normal erase 25-50% of the magnitude of the bias on the substrate during the soft erase to bias the substrate and the set of serially connected memory cells at the source terminals the select gate transistor. 5. The apparatus of claim 1 or 2, wherein: the memory cells are connected to a set of word lines and are arranged in sets (700n-703n, 710n-713n, 720n-723n, 730n-733n) of series-connected memory cells; each set of series-connected memory cells includes a channel (665), a source terminal (613), and a select gate transistor; and To perform the soft erase, the control circuit is configured to bias the control gates (1010, 1016) of the select gate transistors of the set of series-connected memory cells with a negative voltage to pass the gate Induced drain leakage creates holes in the channel. 6. The apparatus of claim 1 or 2, wherein: The operation includes a read operation in which the sensing includes reading a data state of the selected memory cell or a program operation in which the sensing includes the Verify test for selected memory cells. 7. The apparatus of claim 1 or 2, wherein: The control circuit is configured to perform normal erasing of the block of memory cells in response to an erase command of the block; performing the soft erase in a single iteration; and The normal erasing is performed in multiple iterations. 8. A method comprising: When a pass voltage is applied to unselected memory cells of the set of connected memory cells, a sense voltage is applied to the set of connected memory cells (700n-703n, 710n-713n, 720n-723n, 730n-733n ) in the selected memory cell; upon application of the sense voltage, sensing the selected memory cell; After the sensing, the control gate voltages of the unselected memory cells are driven from the pass voltage to a lower level, resulting in down coupling of the voltages of the channels of the connected set of memory cells ; generating a hole current in the channel to neutralize the voltage of the channel when the control gate voltage is driven at the lower level; and After the hole current is generated, the control gate voltage of the unselected memory cells is floated. 9. The method of claim 8, wherein: Generating the hole current includes biasing select gate transistors of the set of connected memory cells to cause gate-induced drain leakage.

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