CN107742647A - Gallium Oxide Field Effect Transistor - Google Patents

Abstract

The invention is applicable to the technical field of semiconductors and provides a gallium oxide field effect transistor. The gallium oxide field effect transistor includes: a substrate, a gallium oxide channel layer, a source, a drain, and a gate, the upper surface of the substrate is the gallium oxide channel layer, and the two sides of the gallium oxide channel layer They are the source and the drain respectively, the middle part of the gallium oxide channel layer is the gate, and the gate completely surrounds the gallium oxide channel layer. In the gallium oxide field effect transistor provided by the embodiment of the present invention, when the thickness of the gallium oxide channel layer is increased to increase the current density, the gate is designed to fully surround the gallium oxide channel layer, which will not cause gate control variation. Poor, good gating can be obtained.

Description

Gallium Oxide Field Effect Transistor

technical field

The invention belongs to the technical field of semiconductors, in particular to a gallium oxide field effect transistor.

Background technique

Gallium oxide (Ga ₂ O ₃ ) is an oxide of metal gallium (Ga). The bandgap of Ga ₂ O ₃ is 4.8eV, which is higher than that of the first-generation semiconductor silicon, and also higher than that of the third-generation wide bandgap semiconductors GaN and SiC. The breakdown electric field of Ga ₂ O ₃ is 8MV/cm, which is higher than 0.3MV/cm of silicon, 3.3MV/cm of GaN and 2.5MV/cm of SiC, which means that under the same device size, Ga ₂ The breakdown voltage of _O3 is theoretically 26.6 times that of silicon, 2.4 times that of GaN, and 3.2 times that of SiC. In the field of power device applications, Ga ₂ O ₃ field effect transistors (FETs) also have the advantages of stable chemical properties, high withstand voltage, low loss, low leakage, high temperature resistance, radiation resistance, high reliability and low cost.

However, the current density of Ga ₂ O ₃ FET is low, and a common method to increase the current density is to increase the thickness of the channel layer, but this method will lead to deterioration of gate control characteristics.

Contents of the invention

In view of this, an embodiment of the present invention provides a gallium oxide field effect transistor to solve the problem in the prior art that increasing the current density of the gallium oxide field effect transistor leads to deterioration of gate control characteristics.

The first aspect of the embodiments of the present invention provides a gallium oxide field effect transistor method, including: a substrate, a gallium oxide channel layer, a source, a drain, and a gate, and the upper surface of the substrate is the gallium oxide channel layer, the two sides of the gallium oxide channel layer are respectively the source and the drain, and the middle part of the gallium oxide channel layer is the gate; the gate completely surrounds the oxide gallium channel layer.

Optionally, the gate forms a Schottky contact with the gallium oxide channel layer.

Optionally, there is a dielectric layer between the gate and the gallium oxide channel layer, and the dielectric layer completely surrounds the gallium oxide channel layer.

Further, the thickness of the dielectric layer is less than or equal to 100 nanometers.

Further, the dielectric layer is a SiO ₂ layer, an AlN layer, a SiN layer, an Al ₂ O ₃ layer, an insulating high-resistance Ga ₂ O ₃ layer or a combination of two or more thereof.

Optionally, the thickness of the gallium oxide channel layer is greater than or equal to 10 nanometers and less than or equal to 2000 nanometers.

Optionally, the gallium oxide channel layer is n-type doped.

Further, the doping concentration of the gallium oxide channel layer is greater than 1×10 ¹⁶ cm ^-3 .

Optionally, the source forms an ohmic contact with the gallium oxide channel layer.

Optionally, the drain forms an ohmic contact with the gallium oxide channel layer.

The beneficial effect of the embodiment of the present invention compared with the prior art is: the gallium oxide field effect transistor provided by the embodiment of the present invention, when the thickness of the gallium oxide channel layer is increased to increase the current density, the gate is designed as Fully surrounding the gallium oxide channel layer will not lead to poor gate control, and can obtain good gate control.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the accompanying drawings that need to be used in the descriptions of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only of the present invention. For some embodiments, those of ordinary skill in the art can also obtain other drawings based on these drawings without paying creative efforts.

FIG. 1 is a schematic structural diagram of a gallium oxide field effect transistor provided by an embodiment of the present invention;

FIG. 2 is a schematic diagram of a gate structure provided by an embodiment of the present invention;

FIG. 3 is a schematic diagram of a gate structure provided by an embodiment of the present invention.

detailed description

In the following description, specific details such as specific system structures and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the embodiments of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

In order to illustrate the technical solutions of the present invention, specific examples are used below to illustrate.

Please refer to FIG. 1 . FIG. 1 is a schematic structural diagram of a gallium oxide field effect transistor provided by an embodiment of the present invention. The gallium oxide field effect transistor includes: a substrate 101 , a gallium oxide channel layer 102 , a source 103 , a drain 104 and a gate 105 . The upper surface of the substrate 101 is the gallium oxide channel layer 102, the two sides of the gallium oxide channel layer 102 are the source electrode 103 and the drain electrode 104 respectively, and the gallium oxide channel layer 102 The middle part of is the gate 105 . The gate 105 completely surrounds the gallium oxide channel layer 102 .

In the gallium oxide field effect transistor provided by the embodiment of the present invention, when the thickness of the gallium oxide channel layer is increased to increase the current density, the gate is designed to fully surround the gallium oxide channel layer, which will not cause gate control variation. Poor, good gating can be obtained.

Optionally, as shown in FIG. 2, the gate 201 is in direct contact with the gallium oxide channel layer 202 to form a Schottky contact, and the gate 201 and the gallium oxide channel layer 202 form an MES (metal-semiconductor) structure .

Optionally, as shown in FIG. 3 , there is a dielectric layer 302 between the gate 301 and the gallium oxide channel layer 303 , and the dielectric layer 302 completely surrounds the gallium oxide channel layer 301 . The gate 301, the dielectric layer 302 and the gallium oxide channel layer 303 form a MIS (metal-insulator-semiconductor) structure.

Further, the thickness of the dielectric layer 302 is less than or equal to 100 nanometers.

Further, the dielectric layer 302 is a SiO ₂ layer, an AlN layer, a SiN layer, an Al ₂ O ₃ layer, an insulating high-resistance Ga ₂ O ₃ layer, or a combination of two or more thereof, for example, the dielectric layer 302 can be It is AlN/SiN or AlN/SiN/SiO ₂ .

Optionally, the thickness of the gallium oxide channel layer 102 is greater than or equal to 10 nanometers and less than or equal to 2000 nanometers.

Optionally, the gallium oxide channel layer 102 is n-type doped, and doped impurities include but not limited to Sn, Si, C, F, Cl, Br or I.

Further, the doping concentration of the gallium oxide channel layer 102 is greater than 1×10 ¹⁶ cm ⁻³ .

Optionally, the source electrode 103 forms an ohmic contact with the gallium oxide channel layer 102, and the source electrode 103 can be made of metals Au, Al, Ti, Sn, Ge, In, Ni, Co, Pt, W, Mo, Cr, Cu, P or a combination of two or more thereof, for example, Ti/Au or Ti/Al/Ni/Au. Through ion implantation and rapid thermal annealing process, the source electrode 103 and the gallium oxide channel layer 102 form an ohmic contact.

Optionally, the drain 104 forms an ohmic contact with the gallium oxide channel layer 102 . The drain electrode 104 can be made of metal Au, Al, Ti, Sn, Ge, In, Ni, Co, Pt, W, Mo, Cr, Cu, P or a combination of two or more thereof, for example, Ti/Au or Ti/Al/Ni/Au. Through ion implantation and rapid thermal annealing process, the drain 104 forms an ohmic contact with the gallium oxide channel layer 102 .

The gate 105 can be made of metal Au, Al, Ti, Sn, Ge, In, Ni, Co, Pt, W, Mo, Cr, Cu, P or a combination of two or more thereof, for example, Ti/Au or Ti/Al/Ni/Au.

The above-described embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still implement the foregoing embodiments Modifications to the technical solutions recorded in the examples, or equivalent replacement of some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should be included in within the protection scope of the present invention.

Claims (10)

1. A gallium oxide field effect transistor is characterized in that, comprises, substrate, gallium oxide channel layer, source electrode, drain electrode and grid, and the upper surface of described substrate is described gallium oxide channel layer, so The two sides of the gallium oxide channel layer are respectively the source and the drain, the middle part of the gallium oxide channel layer is the gate, and the gate completely surrounds the gallium oxide channel layer. 2. The gallium oxide field effect transistor according to claim 1, wherein the gate forms a Schottky contact with the gallium oxide channel layer. 3. The gallium oxide field effect transistor according to claim 1, wherein a dielectric layer is provided between the gate and the gallium oxide channel layer, and the dielectric layer completely surrounds the gallium oxide channel layer . 4. The gallium oxide field effect transistor according to claim 3, wherein the thickness of the dielectric layer is less than or equal to 100 nanometers. 5. Gallium oxide field effect transistor as claimed in claim 3, is characterized in that, described dielectric layer is SiO ₂ layers, AlN layer, SiN layer, Al ₂ O ₃ layers, insulating high resistance Ga ₂ O ₃ layers or wherein A combination of two or more. 6 . The gallium oxide field effect transistor according to claim 1 , wherein the thickness of the gallium oxide channel layer is greater than or equal to 10 nanometers and less than or equal to 2000 nanometers. 7. The gallium oxide field effect transistor according to claim 1, wherein the gallium oxide channel layer is n-type doped. 8 . The gallium oxide field effect transistor according to claim 7 , wherein the doping concentration of the gallium oxide channel layer is greater than 1×10 ¹⁶ cm ⁻³ . 9. The gallium oxide field effect transistor according to claim 1, wherein the source forms an ohmic contact with the gallium oxide channel layer. 10 . The gallium oxide field effect transistor according to claim 1 , wherein the drain forms an ohmic contact with the gallium oxide channel layer. 11 .