CN107204299A - The manufacture method and semiconductor device of semiconductor device - Google Patents

Abstract

Embodiments of the present invention provide a method of manufacturing a semiconductor device and a semiconductor device capable of suppressing unnecessary deformation of leads. The manufacturing method of the semiconductor device according to the embodiment includes the step of pressing the pressing member against the lead frame from the other surface of the lead frame opposite to the surface on which the first recess is formed while pressing the first inner lead. Deform the wire part, cut the connection part between the end part of the first inner lead in the extending direction and the wiring part with the first concave part as the base point, and separate the wiring part from the end part. The lead frame includes the first 1 lead, the second lead, and the wiring portion connecting the second inner lead and the end of the first inner lead in the extending direction; and the end of the first inner lead in the extending direction and the wiring portion The connecting portion between them has a first concave portion in a region inner than the end portion in the width direction.

Description

Manufacturing method of semiconductor device and semiconductor device

[Related applications]

This application enjoys the priority of the basic application based on Japanese Patent Application No. 2016-53321 (filing date: March 17, 2016). This application incorporates all the contents of the basic application by referring to this basic application.

technical field

Embodiments of the present invention relate to a method of manufacturing a semiconductor device and the semiconductor device.

Background technique

In a semiconductor device including leads including outer leads and inner leads, and a semiconductor chip, electrode pads of the semiconductor chip and inner leads are electrically connected by bonding wires. Therefore, the longer the distance between the electrode pad and the outer lead, the longer the inner lead must be extended from the outer lead to the vicinity of the electrode pad.

Long inner leads are easily deformed during the manufacturing process of the semiconductor device. If the inner lead is deformed, for example, the semiconductor chip may be easily detached from the inner lead or poor connection may occur between the bonding wire and the inner lead during wire bonding.

Contents of the invention

Embodiments of the present invention provide a method of manufacturing a semiconductor device and a semiconductor device capable of suppressing unnecessary deformation of leads.

The manufacturing method of the semiconductor device according to the embodiment includes the step of pressing the pressing member against the lead frame from the other surface of the lead frame opposite to the surface on which the first recess is formed while pressing the first inner lead. Deform the wire part, cut the connection part between the end part of the first inner lead in the extending direction and the wiring part with the first concave part as the base point, and separate the wiring part from the end part, and the lead frame includes: The first lead includes the first outer lead and the first inner lead extending from the first outer lead; the second lead includes the second outer lead and the second inner lead extending from the second outer lead; the wiring part includes the second outer lead and the second inner lead extending from the second outer lead; 2 The connection between the inner lead and the end in the extending direction of the first inner lead; and the supporting part, which is connected to the first outer lead and the second outer lead; The connecting part between the parts has a first concave part in the area more inside than the end part in the width direction; the semiconductor chip including the first electrode pad and the second electrode pad is mounted on the other surface of the lead frame through the adhesive layer; A first bonding wire electrically connecting the first electrode pad to the first lead, and a second bonding wire electrically connecting the second electrode pad to the second lead; forming the first inner lead, the second inner lead, and the wiring portion 1. A sealing resin layer for sealing the semiconductor chip, the first bonding wire, and the second bonding wire; cutting the connecting portion between the support portion and the first outer lead and the second outer lead.

Description of drawings

FIG. 1 is a schematic plan view showing a structural example of a lead frame.

Fig. 2 is a schematic diagram showing a part of a lead frame.

FIG. 3 is a schematic cross-sectional view for explaining the lead frame processing steps.

FIG. 4 is a schematic cross-sectional view for explaining the lead frame processing steps.

Fig. 5 is a schematic view showing a part of the lead frame after the lead frame processing step.

6 is a schematic plan view showing a structural example of a semiconductor device.

FIG. 7 is a schematic plan view showing a part of the semiconductor device.

8 is a schematic cross-sectional view showing a structural example of a part of a semiconductor device.

detailed description

Embodiments will be described below with reference to the drawings. The relationship between the thickness of each constituent element and the plane size, the ratio of the thickness of each constituent element, and the like described in the drawings may be different from the actual ones. In addition, in the embodiment, substantially the same components are assigned the same reference numerals, and description thereof is appropriately omitted.

As an example of a method of manufacturing a semiconductor device, an example of a method of manufacturing a semiconductor device as a TSOP (Thin Small Outline Package) will be described with reference to FIGS. 1 to 8 . An example of a method for manufacturing a semiconductor device includes a lead frame preparation step, a lead frame processing step, a chip mounting step, a wire bonding step, a resin sealing step, an exterior plating step, and a trimming (T/F) step. The order of the steps is not limited to the listed order.

FIG. 1 is a schematic plan view showing a structural example of a lead frame. FIG. 1 shows an X-Y plane of a lead frame including an X axis and a Y axis perpendicular to the X axis.

In the lead frame preparing step, as shown in FIG. 1 , a lead frame 1 including a plurality of leads 11 and a support portion 12 supporting the plurality of leads 11 is prepared. The lead frame 1 is a metal plate on which elements such as semiconductor chips are mounted. As the lead frame 1 , for example, a lead frame using an alloy of iron and nickel such as copper, a copper alloy, or 42 alloy, or the like can be cited. The lead frame 1 is preliminarily processed by punching or the like.

Each of the plurality of leads 11 includes an outer lead and an inner lead extending from the outer lead. The inner lead is a portion supported by the sealing resin layer after the resin sealing step. Inner leads are plated with silver or the like on the upper surface side of the lead frame 1 where wire bonding is performed. The outer leads are portions protruding from the sealing resin layer after the resin sealing step. Each of the outer leads of the plurality of leads 11 is arranged in parallel on the X-Y plane along the Y axis, for example.

As the plurality of wires 11, for example, input/output signal (IO), data strobe signal (DQS), wire enable signal (RE), standby/busy signal (RB), chip enable signal (CE), address lock Store enable signal (ALE), write enable signal (WE), write protect signal (RP), or retailer signal (ZQ) and other signal leads, or power supply (VCC), power supply (VPP), power supply ( VSS) and other power supply leads, etc. As the signal, a differential signal may also be used. At least one of the plurality of leads 11 may also be a non-connected (NC) lead. The order of arrangement of various leads is set in accordance with the specifications or standards of semiconductor devices.

The support portion 12 is provided to surround the plurality of lead wires 11 . The supporting portion 12 is connected to each of one ends of the outer leads of the plurality of leads 11 . In addition, the support portion 12 may support a lead for another semiconductor device in addition to supporting the plurality of leads 11 .

FIG. 2 is a schematic diagram showing a part of the lead frame shown in FIG. 1 (a part of the region 100 ) viewed from the lower surface side of the lead frame 1 . In FIG. 2 , the lower surface of the lead frame 1 is shown on the upper surface side, and the upper surface of the lead frame 1 is shown on the lower surface side. The Z axis in FIG. 2 is perpendicular to the X axis and the Y axis, and corresponds to the thickness direction of the lead frame 1 . In FIG. 2 , an inner lead 111 , an inner lead 112 , an inner lead 113 , and an inner lead 114 are shown as the inner leads of the plurality of leads 11 .

The inner leads 111 and 112 are, for example, leads for input/output signals (IO) or data strobe signals (DQS). The inner leads 113 and 114 are, for example, leads for a power supply (VSS). In this case, the interference between the signal of the inner lead 111 and the signal of the inner lead 112 can be suppressed by providing the inner lead 113 between the inner lead 111 and the inner lead 112 .

The lead frame shown in FIG. 1 has a wiring portion 115 that connects end portions in the extending direction of the inner leads 111 to 113 and a part of the inner leads 114 . That is, the inner leads 111 to 113 are fixed by the supporting part 12 and the wiring part 115 . The shape of the wiring portion 115 is not particularly limited as long as it is a shape capable of connecting the inner leads 111 to 113 and the inner leads 114 . In addition, the wiring part 115 can also be regarded as a part of the inner lead 114 .

The inner leads 111 to 114 and the wiring portion 115 have the plating layer 20 provided on the upper surface side (the lower surface side in FIG. 2 ) of the lead frame 1 . The plated layer 20 is formed, for example, by a plating process using a plating material containing silver or the like. Plating layer 20 is provided in the region where wire bonding is performed in order to ensure bonding strength between inner leads 111 to 114 and bonding wires during wire bonding described later, or to reduce connection resistance with the semiconductor chip.

The connecting portion between the inner lead 111 and the end in the extending direction (Y-axis direction) of the inner lead 113 and the wiring portion 115 has a concave portion (groove) 116 a on the upper surface side of the lead frame 1 . The concave portion 116 a is provided in a region inside each of the inner leads 111 to 113 than the ends in the width direction (X-axis direction).

The connecting portion between the inner lead 114 and the wiring portion 115 has a concave portion (groove) 116 b on the upper surface side of the lead frame 1 . The concave portion 116b shown in FIG. 2 extends from one end to the other end of the inner lead 114 in the width direction, but it is not limited thereto, and may be provided at the connection portion between the inner lead 114 and the wiring portion 115 similarly to the concave portion 116a. The area on the inner side of the end in the width direction. In addition, a plurality of recesses 116b may be provided.

In FIG. 2, the concave portion 116a and the concave portion 116b have a V-shape in a cross section including the Y-Z plane, but other shapes may be used. In addition, the depth of the recess 116 b in the thickness direction of the lead frame 1 is preferably smaller than the depth of the recess 116 a in the thickness direction of the lead frame 1 .

The recessed part 116a and the recessed part 116b are formed by stamp processing, laser processing, or blade processing, etc., for example. The concave portion 116a and the concave portion 116b are preferably formed before the punching step. If the concave portion 116 a and the concave portion 116 b are formed after punching, the lead frame 1 may be deformed uselessly.

The concave portion 116 a and the concave portion 116 b are provided on the lower surface side of the lead frame 1 , that is, on the surface opposite to the surface having the plating layer 20 . The plating layer 20 is formed after forming the concave portion 116a and the concave portion 116b. Therefore, if the plating layer 20 is formed on the surface having the recess 116a and the recess 116b, the plating material may accumulate in the recess 116a and the recess 116b, and the reliability may be lowered due to electric field concentration or the like.

3 and 4 are schematic cross-sectional views for explaining the lead frame processing steps. 3 and 4 show a Y-Z cross-section of the lead frame 1 including the Y-axis and the Z-axis. In FIGS. 3 and 4 , as an example, a cross section including the inner lead 113 is shown.

In the lead frame processing step, the lead frame 1 is placed on the stage 51 including the recess 51 a so that the recess 116 a and the recess 116 b are located on the lower side (the stage 51 side), and both sides of the wiring portion 115 are pressed by the pressing member 52 . end. At this time, the wiring part 115 is made to overlap with the recessed part 51a.

Next, the pressing member 53 is lowered toward the platform 51 in the Z-axis direction, and the pressing member 53 is pressed against the wiring portion 115 from the other surface of the lead frame 1 opposite to the surface on which the recessed portion 116 a and the recessed portion 116 b are formed. At least a part of the wiring portion 115 is deformed, and the connection portion between the end portion in the extending direction of the inner lead 113 and the wiring portion 115 is cut with the concave portion 116 a as a base point. The portion with the recess 116a is more likely to be sheared than other areas. In addition, since the concave portion 116a is provided inside the widthwise end of the inner lead 113, burrs due to shearing are suppressed compared to the case where the concave portion 116a extends to the widthwise end of the inner lead 113.

The wiring portion 115 is bent so as to be separated from the end portion in the extending direction of the inner lead 113 with the concave portion 116 b as a base point. The portion having the concave portion 116b is easier to bend than other areas. Therefore, useless deformation can be suppressed.

FIG. 5 is a schematic diagram showing a structural example of the deformed region 100 viewed from the upper surface side of the lead frame 1 . In FIG. 5 , the upper surface of the lead frame 1 is shown on the upper surface side, and the lower surface of the lead frame 1 is shown on the lower surface side.

The wiring portion 115 after cutting the connecting portion includes: a first end portion connected to the inner lead 114; The ends of the lead wires 113 in the extending direction are adjacent to each other. The second end portion is bent in a predetermined direction based on the concave portion 116b so as to be separated from the inner leads 111 to 113 along the cross section of the inner lead 114 including the thickness direction when viewed from a direction perpendicular to the Y-Z cross section.

The ends in the extending direction of the inner leads 111 to 113 and the second end of the wiring portion 115 each have a recess 117 in a region inner than the end in the width direction by cutting out the recess 116 a. The shape of the deformed wiring portion 115 is not particularly limited. As shown in FIG. 5 , the wiring portion 115 may include a region parallel to the extending direction of the inner leads 111 to 113 . Through the above steps, a part of the inner lead 111 to a part of the inner lead 114 are separated from each other. Similarly, a part of the other connected inner leads is also separated from each other by this step.

The load required for shearing can be reduced by reducing the thickness of the inner lead wire 111 to the connecting portion between the inner lead wire 113 and the wiring portion 115 . Thereby, as the pressing member 53 , one of a plurality of bonding heads provided in a die bonding apparatus used when mounting a semiconductor chip in the chip mounting step can be applied.

In order to electrically separate the inner leads 111 to 114 , a method of removing a part of the connecting portion by punching may be considered. When a part of the connecting portion is removed by punching, two or more cutting locations are required for one of the inner leads 111 to 113 . Therefore, the load required for punching is greater than the load required for shearing of the connection portion. Therefore, in order to perform punching, it is necessary to provide a pressing mechanism capable of applying a higher load, which is different from the mechanism for cutting the connection portion. Therefore, the configuration of the processing apparatus becomes complicated. In addition, when punching is performed, chips (removed portions) are generated when a part of the lead frame is punched. The chippings of the lead wires become a source of contamination of the manufacturing environment, and a mechanism for discharging the chippings of the lead wires is required, so it is preferable not to generate the chippings.

In the case of processing the lead frame by punching, the lead frame is transported to a die bonding apparatus after processing to mount a semiconductor chip, and the thermal lead is easily deformed during transport. Therefore, it is necessary to provide a fixing tape for fixing a plurality of lead wires. Since the fixing tape easily absorbs moisture, it is easily peeled off from the leads or the resin that seals the semiconductor chip provided later. In addition, if there is a fixing tape, the lead frame becomes substantially thicker. Therefore, since the number of lead frames that can be accommodated in the housing case decreases, transportation costs increase. Furthermore, the fixing tape tends to undergo dendritic migration. Migration may cause a short circuit between leads or the like.

On the other hand, in the case of cutting the connecting portion and separating a part of each inner lead using a die bonding apparatus, the semiconductor chip can be mounted using the same die bonding apparatus after the lead frame processing step. Therefore, the conveyance of the lead frame can be reduced. Thereby, useless deformation|transformation of a lead wire can be suppressed even if a fixing tape is not provided. In addition, material cost and processing cost of the fixing band can be reduced, thereby reducing manufacturing cost. Furthermore, since a part of each inner lead can be separated while leaving the wiring portion, it is possible to reduce chippings of the lead compared to punching.

6 is a schematic plan view showing an example of the structure of a semiconductor device that can be manufactured using the example of the method for manufacturing a semiconductor device. FIG. 6 shows the X-Y plane of the semiconductor device. FIG. 7 is a schematic plan view showing a part of the semiconductor device shown in FIG. 6 (a part of the region 101 ) viewed from the upper surface side of the lead 11 . FIG. 8 is a schematic cross-sectional view of a part of the semiconductor device shown in FIG. 6 (a part of the region 101 ). FIG. 8 shows a cross section including the inner lead 113 as an example. In addition, in FIG.7 and FIG.8, the inside of the sealing resin layer 4 is shown transparently for convenience. The description of FIGS. 1 to 5 is appropriately referred to for parts common to FIGS. 1 to 5 .

In the chip mounting step, the semiconductor chip 2 is mounted on the inner leads 11 of the plurality of leads 11 including the inner leads 111 to 114 . As shown in FIG. 7 , the semiconductor chip 2 has a plurality of electrode pads 21 including electrode pads 211 to 215 . A plurality of electrode pads 21 are exposed on the surface of the semiconductor chip 2 . A plurality of electrode pads 21 may also be arranged along one side of the semiconductor chip 2 . By providing a plurality of electrode pads 21 along one side of the semiconductor chip 2, the chip size can be reduced. As the semiconductor chip 2 , for example, a memory element such as a NAND (Not AND, NAND) flash memory, or a semiconductor chip used for a memory controller or the like is exemplified.

The semiconductor chip 2 is mounted using, for example, a die bonding apparatus used for cutting the connection portion between the end portions in the extending direction of the inner leads 111 to 113 and the wiring portion 115 .

The semiconductor chip 2 is mounted on the inner leads 111 to 114 using another one of the plurality of bonding heads different from the pressing member 53 . The semiconductor chip 2 is mounted on a plurality of inner leads 11 such as the inner lead 111 to the inner lead 114 through an organic adhesive layer 6 having insulating properties such as a die attach film (die attach film). One side of the opposite side of the other side. At this time, the inner leads of the plurality of leads 11 are adhered to the organic adhesive layer 6 . Thus, since the inner leads of the plurality of leads 11 are fixed, useless deformation of the leads can be suppressed in subsequent steps.

The semiconductor chip 2 is preferably mounted after cutting the inner lead 111 to the connection portion between the inner lead 113 and the wiring portion 115 . If the connection portion is cut after mounting the semiconductor chip, the semiconductor chip may be damaged. For example, after the lead frame 1 is placed (loaded) in a die bonding apparatus, the connection portion is cut. Thereafter, the semiconductor chip 2 described below is mounted on the lead frame 1 without removing (unloading) the lead frame 1 from the die bonding apparatus. After mounting the semiconductor chip 2, the lead frame 1 is removed (unloaded) from the die bonding apparatus, and subsequent steps such as the following wire bonding step are performed.

In the wire bonding step, a plurality of bonding wires 3 electrically connecting the plurality of electrode pads 21 and the plurality of leads 11 is formed. 7 shows a bonding wire 31 electrically connecting the inner lead 111 and the electrode pad 211 through the plating layer 20, a bonding wire 32 electrically connecting the inner lead 112 and the electrode pad 212 through the plating layer 20, and connecting the inner lead 113 and the electrode pad 212 through the plating layer 20. The bonding wire 33 electrically connecting the electrode pad 213 through the plating layer 20 , the bonding wire 34 electrically connecting the inner lead 114 and the electrode pad 214 through the plating layer 20 , and the bonding wire electrically connecting the inner lead 114 and the electrode pad 215 through the plating layer 20 Line 35.

As the bonding wire 3, a gold wire, a silver wire, a copper wire, etc. are mentioned, for example. The surface of the copper wire may be covered with a palladium film. The bonding wire 3 is electrically connected to the lead and the electrode pad by wire bonding.

In the resin sealing step, the sealing resin layer 4 is formed to seal the inner leads 11 including the inner leads 111 to 114 , the semiconductor chip 2 , and the bonding wires 3 including the bonding wires 31 to 35 . The sealing resin layer 4 is provided so as to cover the upper surface and the lower surface of the inner lead of the plurality of leads. In addition, as shown in FIG. 8 , the sealing resin layer 4 is also filled between the end portions in the extending direction of the inner leads 111 to 113 and the wiring portion 115 .

The sealing resin layer 4 contains an inorganic filler such as SiO ₂ . In addition, the inorganic filler may contain, for example, aluminum hydroxide, calcium carbonate, aluminum oxide, boron nitride, titanium oxide, or barium titanate in addition to SiO ₂ . The inorganic filler is, for example, granular and has a function of adjusting the viscosity and hardness of the sealing resin layer 4 . The content of the inorganic filler in the sealing resin layer 4 is, for example, 60% or more and 90% or less. As the sealing resin layer 4 , for example, a mixture of an inorganic filler and an insulating organic resin material can be used. As an organic resin material, epoxy resin is mentioned, for example.

Examples of methods for forming the sealing resin layer 4 include transfer molding using a mixture of an inorganic filler and an organic resin, compression molding, injection molding, sheet molding, or resin drop coating.

In the plating step, a plating process is performed on the surfaces of the plurality of lead wires 11 . For example, plating processing such as electroplating is performed using a solder material containing tin or the like. By performing plating, for example, oxidation of the plurality of lead wires 11 can be suppressed.

The trimming (T/F) step includes a step of cutting the connection between the plurality of leads 11 and the support portion 12 to cut out the semiconductor device 10 (trimming step), and making the outer leads of the plurality of leads 11 according to the shape of the semiconductor device 10. A step of deforming to the final shape (molding step).

The semiconductor device 10 can be manufactured through the above steps. As shown in FIGS. 6 to 8 , the semiconductor device 10 includes: a plurality of leads 11 including outer leads and inner leads extending from the outer leads; a semiconductor chip 2 is mounted on the plurality of leads 11 via an organic adhesive layer 6 ( For example, on at least a part of the surface of the inner lead 114 that is opposite to the predetermined direction of bending), and has a plurality of electrode pads 21; a plurality of bonding wires 3 connect the plurality of electrode pads 21 to the plurality of lead wires 11; and The sealing resin layer 4 seals the inner leads of the plurality of leads 11 , the semiconductor chip 2 , and the plurality of bonding wires 3 . In addition, the ends in the extending direction of the inner leads 111 to 113 and the second end of the wiring portion 115 adjacent to the ends each include a recess 117 which is a part of the cut recess 116 a. In addition, the semiconductor chip 2 may be mounted on the surface of the plurality of leads 11 opposite to the mounting surface of the semiconductor chip 2 shown in FIG. 8 . In addition, the semiconductor device 10 shown in FIGS. 6 to 8 is a TSOP, and may have other package structures.

The above-described embodiments are presented as examples, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope or spirit of the invention, and are included in the invention described in the claims and their equivalents.

[explanation of the symbol]

1 lead frame

2 Semiconductor chips

3 bonding wire

4 sealing resin layer

6 organic adhesive layer

10 Semiconductor device

11 leads

12 Support

20 plating

21 electrode pads

31～35 Bonding wire

51 platforms

51a Recess

52 Press parts

53 Push parts

100 areas

101 area

111～114 Inner lead

115 Wiring Department

116a Recess

116b Recess

211～215 electrode pad

Claims (5)

1. a kind of manufacture method of semiconductor device, it is characterised in that possess following steps：For lead frame, while pressing the 1 lead, while will push against part pressure from the another side that the one side with forming the 1st recess of the lead frame is opposite side Arrive to wiring part and deform it, sheared by basic point of the 1st recess end on the bearing of trend of the 1st lead with The connecting portion of the wiring part, and the wiring part is separated from the end, the lead frame includes：1st lead, bag The 1st lead extended containing the 1st outer lead and from the 1st outer lead；2nd lead, comprising the 2nd outer lead and from described 2nd lead of the 2nd outer lead extension；The wiring part, by the 2nd lead and the bearing of trend of the 1st lead On end between connect；And supporting part, it is connected to the 1st outer lead and the 2nd outer lead；And the 1st lead Bearing of trend on end and the wiring part between connecting portion have in the region of the end inside than width 1st recess；

Semiconductor chip comprising the 1st electronic pads and the 2nd electronic pads is equipped on to the institute of the lead frame via adhesion coating State on another side；

Formed the 1st closing line that electrically connects the 1st electronic pads with the 1st lead and by the 2nd electronic pads with it is described 2nd closing line of the 2nd lead electrical connection；

Formed the 1st lead, the 2nd lead, the wiring part, the semiconductor chip, the 1st engagement Line and the sealed sealing resin layer of the 2nd closing line；

By the connecting portion cut-out between the supporting part and the 1st outer lead and the 2nd outer lead.

2. the manufacture method of semiconductor device according to claim 1, it is characterised in that：The push part is provided in By the semiconductor-chip-mounting in one of multiple engaging heads of the chip bonding device on the lead frame.

3. the manufacture method of semiconductor device according to claim 1 or 2, it is characterised in that：2nd lead and institute The second recesses that there is the connecting portion between wiring part depth to be less than the 1st recess are stated, and

In the separating step, the wiring part is so that the second recesses to be prolonged with the 1st lead as basic point The mode for stretching the separation of the end on direction is bent.

4. the manufacture method of semiconductor device according to claim 3, it is characterised in that：

1st lead includes the 1st coating for being arranged on another surface side,

2nd lead includes the 2nd coating for being arranged on another surface side,

The second recesses are arranged on a surface side,

1st closing line is electrically connected to the 1st lead via the 1st coating, and

2nd closing line is electrically connected to the 2nd lead via the 2nd coating.

5. a kind of semiconductor device, it is characterised in that including：

1st lead, the 1st lead extended comprising the 1st outer lead and from the 1st outer lead；

2nd lead, the 2nd lead extended comprising the 2nd outer lead and from the 2nd outer lead；

Wiring part, the 1st end comprising the part for being connected to the 2nd lead and the extension side with the 1st lead The 2nd adjacent end of upward end, and the 2nd end is with the section comprising thickness direction of the 2nd lead The mode separated with the end on the bearing of trend of the 1st lead is bent to prescribed direction；

Semiconductor chip, with the 1st electronic pads and the 2nd electronic pads, and is equipped on via adhesion coating the described 1st and the described 2nd On at least a portion with the prescribed direction for the face of opposite side of at least one of lead；

1st closing line, will be electrically connected between the 1st lead and the 1st electronic pads；

2nd closing line, will be electrically connected between the 2nd lead and the 2nd electronic pads；And

Sealing resin layer, by the 1st lead, the 2nd lead, the wiring part, the semiconductor chip, described 1 closing line and the 2nd engagement linear sealing；And

Each comfortable end than width in the 2nd end of end and the wiring part on the bearing of trend of 1st lead The region of portion inside has recess.