CN106783730B - Method for forming air gap/copper interconnection - Google Patents

Abstract

A method of forming an air gap/copper interconnect, which includes providing a semiconductor substrate, first completing a CMOS device front-end process on the semiconductor substrate, and then forming a conventional first dielectric/copper interconnect structure on the semiconductor substrate ; Surface treatment of the conventional first medium/copper interconnect structure in an oxygen-containing atmosphere to form a layer of copper oxide on the surface of the copper interconnect line; Etch the first medium in the middle of the copper interconnect line with an etching device ; wherein, in the process of etching the first medium, fluorine-based gas and oxygen-based gas are used for etching, and copper oxide protects the copper interconnection from being exposed to the etching gas atmosphere; restores the surface of the copper interconnection. Copper oxide, that is, the copper oxide on the surface of the copper interconnect is re-converted to metallic copper; the residual photoresist is removed and cleaned with a wet chemical solution; the second dielectric is deposited to form an air gap/copper interconnect structure.

Description

A method of forming an air gap/copper interconnect

technical field

The present invention relates to the field of semiconductor processing and manufacturing, and more particularly, to a method for forming air gap/copper interconnects.

Background technique

With the continuous development of Moore's Law, the characteristic line width of transistors is getting smaller and smaller, the integration density is getting higher and higher, and the performance is getting stronger and stronger. For Complementary Metal Oxide Semiconductor (Complementary Metal Oxide Semiconductor, CMOS for short) transistors, speed is an important indicator to characterize its performance.

It is clear to those skilled in the art that the speed of CMOS is related to the delay of CMOS, and the delay of CMOS can be subdivided into the delay of the front-end device and the delay of the back-end interconnect; The impact of CMOS delays has become larger and larger, and has become the most dominant delay in advanced processes. The delay of the rear interconnection line is mainly determined by the resistance R of the interconnection wire and the capacitance C (ie RC) between the interconnection wires.

In order to reduce the RC delay of the back-end interconnects, integrated circuit manufacturers have been looking for ways to reduce the interconnection wire resistance and the capacitance between interconnection wires, such as using copper wires with lower resistivity instead of aluminum wires, using lower dielectric constant. low-k media instead of silica media.

For the latter, it has undergone several technical updates in technology bands. During the improvement process of the inter-conductor dielectric from SiO ₂ →F dopedSiO ₂ (FSG)→BD I→BD II→BD III, the The dielectric constant continues to decrease in order to meet the need to reduce the RC of the rear interconnect.

As we all know, the relative permittivity of vacuum is 1, and the relative permittivity of air is also about 1, which is the most common medium with the smallest relative permittivity. Therefore, the use of air parts to replace the traditional medium between interconnect lines is also proposed, which is the air gap/copper interconnect structure technology.

The formation methods of air gaps can be roughly divided into the following two categories:

In the first type, a normal dielectric/copper interconnect structure is formed by a traditional process, then the dielectric between the copper interconnect lines is removed by an etching process, and finally an air gap is formed by a chemical vapor deposition process;

The second type uses a sacrificial layer, such as thermal degradable polymer, to remove the sacrificial layer after completing the copper interconnect structure to form an air gap.

Currently, for most IC manufacturers, the first type of approach is more process compatible and therefore easier to accept. The following briefly describes a process method for preparing an air gap/copper interconnect structure using the first type of method in the prior art with reference to accompanying drawings 1-3.

Step S01 : firstly forming a traditional first dielectric 102/copper 104 interconnect structure on the semiconductor substrate 101, this part of the process is exactly the same as the existing CMOS process, without additional process costs and risks (as shown in FIG. 1 ), I will not repeat them here;

Step S02 : removing the first dielectric between the copper interconnecting wires. For example, a dielectric etching process is used to remove part of the first dielectric to obtain the structure shown in FIG. 2 ; however, the surface of the copper 104 will be oxidized during the etching process. Obtain a certain thickness of copper oxide 105;

Step S03: use the subsequent cleaning liquid to remove the remaining photoresist and clean the silicon wafer; during the cleaning process, the copper oxide 105 is easily corroded by the subsequent cleaning liquid, and the subsequent cleaning liquid does not corrode and block The layer 103, therefore, leaves finally the barrier "ears" 103', as shown in FIG. 3 .

Due to the existence of the "ear" 103' of the barrier layer, this structure brings a series of negative effects on the subsequent process and device performance. For example, when chemical vapor deposition medium is used, there will be:

①, the step coverage performance around the "ear" 103' of the barrier layer becomes poor;

②, the mechanical strength of the barrier "ear" 103' is poor, resulting in collapse;

③. The electric field intensity at the tip of the barrier "ear" 103' changes, etc., which directly leads to the deterioration of the performance of the CMOS transistor.

SUMMARY OF THE INVENTION

In view of the deficiencies in the prior art, the purpose of the present invention is to provide a method for forming an air gap/copper interconnect, so as to solve the problem of the deterioration of transistor performance caused by the existence of barrier layer "ears" in the prior art, which avoids The creation of the "ears" of the barrier layer is not only conducive to the chemical vapor deposition process for depositing the medium and forming the air gap, but also improving the performance of the transistor.

For achieving the above object, technical scheme of the present invention is as follows:

A method of forming an air gap/copper interconnect, comprising:

Step S1: Provide a semiconductor substrate, first complete the front-end process of the CMOS device on the semiconductor substrate, and then continue to form the subsequent copper interconnect lines, that is, form a conventional first dielectric/copper interconnect on the semiconductor substrate structure;

Step S2: performing surface treatment on the conventional first dielectric/copper interconnect structure in an oxygen-containing atmosphere to form a layer of copper oxide on the surface of the copper interconnect wire;

Step S3: Etching the first medium in the middle of the copper interconnect lines by using an etching device; wherein, in the process of etching the first medium, fluorine-based gas and oxygen-based gas are used for etching, and the copper oxide protects the copper interconnects are not exposed to an etching gas atmosphere;

Step S4: reducing the copper oxide on the surface of the copper interconnection, even if the copper oxide on the surface of the copper interconnection is re-converted into metallic copper;

Step S5: removing the residual photoresist and cleaning with a wet chemical solution;

Step S6: depositing a second medium to form the air gap/copper interconnect structure.

Preferably, the step S1 specifically includes:

Step S11: depositing a first dielectric layer on the semiconductor substrate;

Step S12: using a photolithography etching process to form a Damascus groove or a double Damascus hole groove in the first dielectric layer;

Step S13: depositing the barrier layer material and the copper interconnect material respectively;

Step S14 : forming a barrier layer and a copper interconnection layer through a grinding process, that is, forming a conventional first dielectric/copper interconnection structure on the semiconductor substrate.

Preferably, the first dielectric material in the conventional first dielectric/copper interconnect structure is one of silicon oxide, fluorine-doped silicon oxide, carbon-doped silicon oxide, silicon nitride, and nitrogen-doped silicon carbide. one or more.

Preferably, the dielectric is a nitrogen-doped silicon carbide/carbon-doped silicon oxide/silicon oxide multilayer structure.

Preferably, in step S2, the thickness of a layer of copper oxide formed on the surface of the copper interconnection line is controllable and uniform, and the thickness of the copper oxide is 30-300 angstroms.

Preferably, in step S3, CF4/O2 mixed gas is used to etch the first dielectric layer.

Preferably, in step S4, the reducing substance used for reducing the copper oxide by-product on the surface of the copper wire is hydrogen gas and/or ammonia gas or plasma of hydrogen gas and/or ammonia gas.

Preferably, in step S5, the etching rate of the residual photoresist is selected to be greater than the etching rate of the copper oxide by the wet chemical solution for removing the residual photoresist.

Preferably, in step S6, the second dielectric layer is deposited by a chemical vapor deposition method or a plasma enhanced chemical vapor deposition device.

Preferably, the second dielectric layer is one or more of silicon oxide, fluorine-doped silicon oxide, carbon-doped silicon oxide, silicon nitride, and nitrogen-doped silicon carbide.

It can be seen from the above technical solutions that in the method for forming an air gap/copper interconnect provided by the present invention, a layer of uniform thickness is first formed on the copper surface of the conventional dielectric/copper interconnect structure by surface treatment technology. Copper oxide, and then after dielectric etching, the copper oxide on the copper surface is re-converted into metal copper by using a reducing substance, and finally the residual photoresist is removed and cleaned by the subsequent wet chemical solution, which avoids the occurrence of current problems. In the prior art, the "ear" structure of the barrier layer caused by the corrosion of copper oxide by the subsequent wet chemical solution is beneficial to the deposition of the subsequent medium and the formation of air gaps, and improves the performance of the transistor.

Description of drawings

FIG. 1 shows a typical schematic diagram of forming a conventional first dielectric/copper interconnect structure on a semiconductor substrate in the prior art

FIG. 2 is a schematic diagram showing the structure of the prior art after the first dielectric/copper interconnect structure is completed and the first dielectric between the copper interconnect wires is removed.

Figure 3 is a schematic diagram showing the structure of the barrier layer "ear" left after the post-cleaning step in the prior art

FIG. 4 is a schematic flowchart of a method for forming an air gap/copper interconnect according to the present invention

FIG. 5 is a schematic cross-sectional view of a method for forming an air gap/copper interconnect according to an embodiment of the present invention after step S1 is completed.

6 is a schematic cross-sectional view of a method for forming an air gap/copper interconnect according to an embodiment of the present invention after step S2 is completed

7 is a schematic cross-sectional view of the method for forming an air gap/copper interconnect according to an embodiment of the present invention after step S3 is completed

8 is a schematic cross-sectional view of the method for forming an air gap/copper interconnect according to an embodiment of the present invention after step S3 is completed

Detailed ways

The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the present invention is capable of various changes in different examples without departing from the scope of the present invention, and the descriptions and drawings therein are for illustrative purposes in nature, rather than limiting the present invention.

Now, a method for forming an air gap/copper interconnection of the present invention will be further described in detail through specific embodiments with reference to the accompanying drawings 4-8. It should be noted that, the accompanying drawings are all in a very simplified form and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

Please refer to FIG. 4 , which is a schematic flowchart of a preferred embodiment of a method for forming an air gap/copper interconnect according to the present invention. In this embodiment, a method for forming an air gap/copper interconnect includes the following steps:

Step S01 : providing a semiconductor substrate, first completing the front-end process of the CMOS device on the semiconductor substrate, and then continuing to form the subsequent copper interconnect lines, that is, forming a conventional first dielectric/copper interconnect on the semiconductor substrate structure. Specifically, please refer to FIG. 5 . FIG. 5 is a schematic cross-sectional view formed after step S1 is completed in an embodiment of the method for forming an air gap/copper interconnect according to the present invention.

As shown in the figure, this step first completes the front-end process of the CMOS device on the substrate silicon wafer 301, and then continues to form the back-end interconnect lines to form a conventional dielectric 302/copper interconnect 304 structure, wherein the reference numeral 303 is a barrier layer. .

Hereinafter, a 12-inch silicon wafer is used as an optional implementation manner to form a conventional front-channel CMOS device structure on the silicon wafer by using a well-known CMOS process, and then use a copper interconnect process to form the specific details of the interconnect lines. steps are explained.

Specifically, in this embodiment, step S1 may include the following steps:

Step S11: depositing a first dielectric layer 302 on the semiconductor substrate 301;

Step S12: forming a Damascus groove or a double Damascus hole groove in the first dielectric layer 302 by using a photolithography etching process;

Step S13: depositing the barrier layer material and the copper interconnect material respectively;

Step S14: The barrier layer 303 and the copper interconnection layer 304 are formed through a grinding process, that is, a conventional first dielectric/copper interconnection structure is formed on the semiconductor substrate.

Preferably, the deposited conventional first dielectric 302 may be one or more of silicon oxide, fluorine-doped silicon oxide, carbon-doped silicon oxide, silicon nitride, and nitrogen-doped silicon carbide, In the embodiment of the present invention, the first dielectric 302 adopts a nitrogen-doped silicon carbide/carbon-doped silicon oxide/silicon oxide multilayer structure.

Step S2: performing surface treatment on the conventional first dielectric/copper interconnect structure in an oxygen-containing atmosphere to form a layer of copper oxide on the surface of the copper interconnect wire. Please refer to FIG. 6 . FIG. 6 is a schematic cross-sectional view of a method for forming an air gap/copper interconnect according to an embodiment of the present invention after step S2 is completed.

As shown in FIG. 6 , in this embodiment, the conventional first dielectric/copper interconnect structure is placed in an oxygen-containing atmosphere for surface treatment, and a layer of controllable and uniform thickness is formed on the surface of the interconnect metal copper 304 The copper oxide 305, preferably, the thickness of the copper oxide can be 30-300 angstroms.

For example, in this embodiment, a conventional dielectric/copper interconnect structure is placed in a plasma chemical vapor deposition apparatus, and treated with oxygen plasma to obtain a copper oxide with a thickness of 100 angstroms on the surface of the copper interconnect 304 .

The copper oxide 305 is not easy to be etched by the gas containing fluorine, and the oxygen in the etching gas is not easy to oxidize the interconnect metal copper, so the copper oxide acts as a protective layer in the subsequent process.

Step S3: Etching the first medium in the middle of the copper interconnect lines by using an etching device; wherein, in the process of etching the first medium, fluorine-based gas and oxygen-based gas are used for etching, and copper oxides protect the copper interconnects. The wires are not exposed to the etching gas atmosphere. Please refer to FIG. 7 . FIG. 7 is a schematic cross-sectional view of a method for forming an air gap/copper interconnect according to an embodiment of the present invention after step S3 is completed.

Specifically, as shown in FIG. 7 , in this embodiment, photolithography and etching processes may be used to remove the first medium 302 between the copper interconnect lines 304 . In the process of etching the first medium 302, fluorine-based gas and oxygen-based gas are used for etching, but since there is a layer of copper oxide 305 on the surface of the copper interconnection line 304 as a protective layer, only the required removal is etched away. The first medium 302 .

In this embodiment, the first dielectric layer 302 can be etched by using a CF4/O ₂ mixed gas. Since there is a layer of copper oxide 305 on the surface of the copper interconnect 304, the metal copper 304 can be prevented from being oxidized. Therefore, the copper oxide 305 plays the role of an etching protection layer.

Step S4 : reducing the copper oxide on the surface of the copper interconnection, even if the copper oxide on the surface of the copper interconnection is re-converted to metallic copper.

Specifically, please refer to FIG. 8 . In this embodiment, the copper oxide 305 on the copper surface can be re-converted into metallic copper 306 by using a reducing substance. Preferably, the reducing substance is hydrogen gas, ammonia gas or hydrogen gas. , Ammonia plasma.

In this embodiment, in the etching chamber, hydrogen plasma is used to reduce the copper oxide 305 and re-convert it into metal copper. Since the thickness of the copper oxide 305 is known and uniform, it is convenient to set the reduction process conditions , improve process uniformity.

Step S5 : removing the residual photoresist with a wet chemical solution and cleaning.

Specifically, the photoresist remaining after etching is removed and the surface of the silicon wafer is cleaned by the subsequent wet chemical solution, and the corrosion rate of the remaining photoresist by the subsequent wet chemical solution is much higher than that of metal copper. Corrosion rate, therefore, no more barrier "ears" are formed.

Step S6: depositing a second dielectric material to form the air gap/copper interconnect structure.

Specifically, a chemical vapor deposition method can be used to deposit the second dielectric layer to form an air gap/copper interconnect structure. The second dielectric layer can be one or more of silicon oxide, fluorine-doped silicon oxide, carbon-doped silicon oxide, silicon nitride, and nitrogen-doped silicon carbide, and the formed air gap is located in the copper interconnection between the lines. In this embodiment, plasma-enhanced chemical vapor deposition equipment can be used to deposit nitrogen-doped silicon carbide and carbon-doped silicon oxide accordingly. When two dielectric materials are used, an air gap will be automatically formed between the metal copper interconnects, forming an air gap/copper interconnect structure.

To sum up, in a method for forming an air gap/copper interconnect provided by the present invention, a layer with a controllable and uniform thickness is formed on the copper surface of a conventional dielectric/copper interconnect structure by first using a surface treatment technology. Then, after dielectric etching, the copper oxide on the copper surface is re-converted into metallic copper by using a reducing substance, which greatly reduces the corrosion rate of the subsequent wet chemical solution, and improves the process controllability and efficiency. Consistency, avoid the formation of barrier layer "ear" structure, and can effectively improve the performance of transistor devices.

The above are only the embodiments of the present invention, and the embodiments are not intended to limit the scope of patent protection of the present invention. Therefore, any equivalent structural changes made by using the contents of the description and drawings of the present invention should be included in the protection of the present invention. within the range.

Claims (10)

1. A method of forming an air gap/copper interconnect, comprising:

step S1: providing a semiconductor substrate, firstly completing the previous process of a CMOS device on the semiconductor substrate, and then continuously forming a next copper interconnection line, thereby forming a first medium/copper interconnection structure on the semiconductor substrate;

step S2: carrying out surface treatment on the first dielectric/copper interconnection structure in an oxygen-containing atmosphere to form a layer of copper oxide on the surface of the copper interconnection line;

step S3: etching the first medium in the middle of the copper interconnection line by using etching equipment; etching by adopting fluorine-based gas and oxygen-based gas in the process of etching the first medium, wherein the copper interconnection line is protected from being exposed in the etching gas atmosphere by the copper oxide;

step S4: reducing the copper oxide on the surface of the copper interconnection line, so that the copper oxide on the surface of the copper interconnection line is converted into metal copper again;

step S5: removing residual photoresist by adopting wet-process liquid medicine and cleaning;

step S6: and depositing a second medium to form the air gap/copper interconnection structure.

2. The method for forming an air gap/copper interconnect as claimed in claim 1, wherein said step S1 specifically comprises:

step S11: depositing a first dielectric layer on a semiconductor substrate;

step S12: forming a Damascus groove or a dual Damascus hole groove in the first dielectric layer by adopting a photoetching process;

step S13: respectively depositing a barrier layer material and a copper interconnection material;

step S14: and forming a barrier layer and a copper interconnection layer through a grinding process, thereby forming a first medium/copper interconnection structure on the semiconductor substrate.

3. The method of claim 1 or 2, wherein the first dielectric material in the first dielectric/copper interconnect structure is one or more of silicon oxide, fluorine-doped silicon oxide, carbon-doped silicon oxide, silicon nitride, and nitrogen-doped silicon carbide.

4. A method of forming an air gap/copper interconnect as claimed in claim 3 wherein said first dielectric is a nitrogen doped silicon carbide/carbon doped silicon oxide/silicon oxide multilayer stack.

5. The method of claim 1, wherein in step S2, a layer of copper oxide with a controllable and uniform thickness is formed on the surface of the copper interconnect line, and the thickness of the copper oxide is 30-300 angstroms.

6. The method of claim 1, wherein in step S3, CF is used₄/O₂And etching the first dielectric layer by using the mixed gas.

7. The method of claim 1, wherein in step S4, the reducing substance used for reducing the copper oxide on the surface of the copper interconnect line is hydrogen and/or ammonia gas or a plasma of hydrogen and/or ammonia gas.

8. The method for forming an air gap/copper interconnect as claimed in claim 1, wherein in step S5, the wet chemical solution for removing the residual photoresist has a higher etching rate to the residual photoresist than to the copper oxide.

9. The method of claim 1, wherein in step S6, the second dielectric layer is deposited by a chemical vapor deposition apparatus.

10. The method of any of claims 1 or 9, wherein the second dielectric layer is one or more of silicon oxide, fluorine-doped silicon oxide, carbon-doped silicon oxide, silicon nitride, and nitrogen-doped silicon carbide.

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