CN106486363A - Group III-nitride enhancement mode HEMT based on p-type layer and preparation method thereof - Google Patents

Abstract

The invention discloses a group III nitride enhanced HEMT based on a p-type layer and a preparation method thereof. The HEMT includes a heterojunction mainly composed of the first half and the second semiconductor layer, and source, gate and drain electrodes connected to the heterojunction. The second semiconductor layer forms a third semiconductor layer of a heterojunction; an etch stop layer is also distributed between the third and second semiconductor layers, and the composition material of the etch stop layer is higher than that of the third semiconductor layer. Higher etching selectivity, or the composition material of the region adjacent to the third semiconductor layer in the second semiconductor layer has a higher etching selectivity than the composition material of the third semiconductor layer. The design of the present invention can greatly reduce the implementation difficulty of the p-type gate technology, and precisely control the etching depth of the p-type layer, ensuring the electrical characteristics of the device and the repeatability, uniformity and stability of the chip manufacturing process, and is suitable for mass production .

Description

Group III nitride-enhanced HEMT based on p-type layer and its preparation method

technical field

The invention relates to a preparation process of a HEMT device, in particular to a preparation method of a Group III nitride enhanced HEMT using an etching stop layer.

Background technique

Compared with traditional silicon-based MOSFETs, high electron mobility transistors (High Electron Mobility Transistors, HEMTs) based on AGaN/GaN heterojunctions have the advantages of low on-resistance, high breakdown voltage, and high switching frequency, so they can be used in various It is used as a core device in similar power conversion systems, and has important application prospects in energy saving and consumption reduction. However, due to the polarization effect of the III-nitride material system, generally speaking, HEMTs based on AlGaN/GaN heterojunctions are depletion mode (normally on). When this type of device is applied to a circuit-level system, it needs Designing a negative polarity gate drive circuit to realize switching control of the device greatly increases the complexity and cost of the circuit. In addition, depletion-mode devices are deficient in fail-safe capabilities, so they cannot be truly commercialized. To solve this problem, it is a feasible solution to prepare an enhanced HEMT based on p-type gate technology. Refer to Figure 1, that is, on the basis of the traditional HEMT epitaxial structure, epitaxial growth on the AlGaN barrier layer (unintentionally doped n-type) p-type layer, so as to form a pn junction in the whole epitaxial wafer, and carry out selective etching to realize the preparation of p-type gate, so as to deplete the two-dimensional electron gas under the p-type gate. In the selective etching process, it is necessary to etch a large area of the non-gate area, but if the etching uniformity cannot be effectively controlled, it is very easy to cause over-etching of the p-type layer in the local area, and local There may be under-etching in the region, and both of them will eventually lead to a decrease in the two-dimensional electron gas concentration in the region between the gate source and the gate drain of the device, and generate a large number of surface defect states, which will seriously affect the working of the device. When the on-resistance and dynamic characteristics. Therefore, the p-type gate technology based on selective etching requires precise and controllable etching depth of the p-type layer in the non-gate area, which greatly increases the difficulty of the p-type gate technology and makes the repeatability of the technology (piece to piece Between), uniformity (between different regions in the chip), and stability (between different rounds of processes) are difficult to guarantee.

Contents of the invention

The main purpose of the present invention is to provide a III-nitride enhanced HEMT and its preparation method, so as to overcome the deficiencies of the prior art.

In order to realize the aforementioned object of the invention, the technical solutions adopted in the present invention include:

In some embodiments there is provided a p-type layer based group III nitride enhanced HEMT comprising a heterojunction consisting essentially of a first semiconductor layer as a channel layer and a second semiconductor layer as a barrier layer And a source electrode, a gate electrode, and a drain electrode connected to the heterojunction, and a third semiconductor layer capable of forming a heterojunction with the second semiconductor layer is distributed between the gate electrode and the barrier layer; wherein:

An etch stop layer is also distributed between the third semiconductor layer and the second semiconductor layer, and, relative to the selected etching substance, the composition material of the etch stop layer is lower than the composition of the third semiconductor layer The material has higher etching resistance;

Alternatively, relative to the selected etching substance, the composition material of the region adjacent to the third semiconductor layer in the second semiconductor layer has higher etching resistance than the composition material of the third semiconductor layer.

In some preferred embodiments, a passivation layer is further provided on the etching stop layer or the second semiconductor layer, and the passivation layer includes at least a partial area of the surface layer of the etching stop layer or the second semiconductor layer. A natural passivation layer formed in situ by the local area of the surface layer reacting with the etching substance.

In some embodiments, there is also provided a method of preparing a p-type layer-based III-nitride-enhanced HEMT, which includes:

On the substrate, a first semiconductor layer body as a channel layer, a second semiconductor layer as a barrier layer, and a third semiconductor layer capable of forming a heterojunction with the second semiconductor layer are sequentially grown, wherein, relative to the selected A certain etching substance, the composition material of the region adjacent to the third semiconductor layer in the second semiconductor layer has higher etching resistance than the composition material of the third semiconductor layer,

Alternatively, the substrate is sequentially grown to form a first semiconductor layer as a channel layer, a second semiconductor layer as a barrier layer, an etching stop layer, and a third semiconductor layer capable of forming a heterojunction with the second semiconductor layer, Wherein, relative to the selected etching substance, the composition material of the etching stop layer has higher etching resistance than the composition material of the third semiconductor layer;

forming a gate electrode material layer on the third semiconductor layer, setting a patterned mask on the gate electrode material layer, and etching the gate electrode material layer and the third semiconductor layer to form a gate electrode, and exposing the second semiconductor layer or the etch stop layer;

And, a source electrode and a drain electrode are provided on the device formed by the aforementioned steps, thereby obtaining the HEMT.

In some preferred embodiments, the preparation method may further include: setting a patterned mask on the gate electrode material layer, and etching the third semiconductor layer with a selected etching substance until the The etching substance reacts with a local area of the surface layer of the second semiconductor layer or a local area of the surface layer of the etching stop layer to form a natural passivation layer in situ, and then stop etching.

In the present invention, before growing the third semiconductor layer (such as a p-type layer), a material having a relatively high etching selectivity ratio to the constituent materials of the third semiconductor layer is grown, and combined with etching technology, the third semiconductor layer can be effectively and reliably realized. The etching of the third semiconductor layer is terminated, so as to accurately control the etching depth of the third semiconductor layer, to ensure that the two-dimensional electron gas in the non-gate area is not affected by the etching process to the greatest extent, and to ensure the electrical characteristics of the device including output current, dynamic characteristics, etc. , greatly reducing the implementation difficulty of p-type gate technology, ensuring the repeatability, uniformity and stability of the device electrical chip process, and suitable for mass production. Especially preferably, under the action of the etching process, an in-situ passivation layer can be naturally formed on the semiconductor surface, and the passivation layer can play a key protective role, thereby effectively reducing the surface damage caused by the subsequent passivation layer deposition process. Problems such as damage and the resulting deterioration of electrical properties of materials (such as increased square resistance and significant current collapse effect) and other issues.

Description of drawings

FIG. 1 is a schematic diagram of the preparation of a p-type gate enhanced HEMT based on selective etching technology in the prior art;

2 is a schematic diagram of an epitaxial structure of a HEMT in Embodiment 1 of the present invention;

3 is a schematic diagram of forming an etching stop layer on the epitaxial structure shown in FIG. 1;

4 is a schematic diagram of forming a p-GaN layer on the etching stop layer shown in FIG. 3;

Fig. 5 is a schematic diagram of active region isolation of the device shown in Fig. 4;

6 is a schematic diagram of forming a gate electrode metal layer on the device shown in FIG. 5;

FIG. 7 is a schematic diagram of the device shown in FIG. 6 after the gate electrode metal layer and the p-GaN layer are etched;

Fig. 8 is a schematic diagram of forming a passivation layer on the device shown in Fig. 7;

Fig. 9 is a schematic diagram of the passivation layer of the device shown in Fig. 8 after windowing;

Fig. 10 is a schematic diagram of forming source, drain electrodes and field plates on the device shown in Fig. 9;

Fig. 11 is a schematic structural view of the HEMT obtained in Example 1;

Fig. 12a is a schematic diagram of the epitaxial structure of a HEMT in Embodiment 2 of the present invention;

Fig. 12b is a schematic diagram of the change of Al composition in the barrier layer in the epitaxial structure shown in Fig. 12a;

Fig. 13 is a schematic diagram of forming a p-GaN layer on the device shown in Fig. 12a;

Fig. 14 is a schematic structural view of the HEMT obtained in Example 2;

Fig. 15a is a schematic diagram of an epitaxial structure of a HEMT in Embodiment 3 of the present invention;

Fig. 15b is a schematic diagram of the change of Al composition in the barrier layer in the epitaxial structure shown in Fig. 15a;

Fig. 16 is a schematic diagram of forming a p-GaN layer on the device shown in Fig. 15a;

Figure 17 is a schematic structural view of the HEMT obtained in Example 3;

Fig. 18a is a schematic diagram of the epitaxial structure of a HEMT in Embodiment 4 of the present invention;

Fig. 18b is a schematic diagram of the change of Al composition in the barrier layer in the epitaxial structure shown in Fig. 18a;

Fig. 19 is a schematic diagram of forming a p-GaN layer on the device shown in Fig. 18a;

FIG. 20 is a schematic structural view of the HEMT obtained in Example 4.

detailed description

One aspect of the present invention provides a p-type layer-based Group III nitride enhanced HEMT comprising a heterojunction mainly composed of a first semiconductor layer as a channel layer and a second semiconductor layer as a barrier layer, and A source electrode, a gate electrode and a drain electrode connected to the heterojunction, and a third semiconductor layer capable of forming a heterojunction with the second semiconductor layer is distributed between the gate electrode and the barrier layer. In a more preferred embodiment, an etch stop layer is distributed between the third semiconductor layer and the second semiconductor layer, and the composition material of the etch stop layer has a relatively High etch selectivity.

That is, for the selected etching substance, the composition material of the etching stop layer has higher etching resistance than the composition material of the third semiconductor layer.

The composition material of the region adjacent to the third semiconductor layer in the second semiconductor layer has a relatively high etching selectivity ratio to the composition material of the third semiconductor layer.

That is, for the selected etching substance, the composition material of the region adjacent to the third semiconductor layer in the second semiconductor layer has higher etching resistance than the composition material of the third semiconductor layer.

In some embodiments, the third semiconductor layer is distributed under the gate electrode and located within the orthographic projection of the gate electrode on the barrier layer.

In some preferred embodiments, a passivation layer is further provided on the etching stop layer or the second semiconductor layer, and the passivation layer includes at least a partial area of the surface layer of the etching stop layer or the second semiconductor layer. A natural passivation layer formed in situ by reacting with the etching substance in a local area of the surface layer, for example, a natural passivation layer made of aluminum oxide.

Wherein, the composition material of the barrier layer can be at least selected from but not limited to AlxInyGazN (0<x≤1, 0≤y≤1, _x + _y + _z =1).

In some embodiments, the barrier layer can be used as an etching stop layer close to the third semiconductor layer, and on the premise of ensuring that the two-dimensional electron gas has excellent electrical properties, the Al component contained in it can also be epitaxial Grow various functions in the z direction.

In some preferred embodiments, the composition material of the barrier layer is selected from _AlxInyGazN (0<x≤1, 0≤y≤1, ( _x + _y +z)=1), Wherein, along the direction from the first semiconductor layer to the third semiconductor layer, x generally shows an increasing trend (wherein some layers may remain unchanged or slightly decrease). The increase method can be linear growth, step growth, super crystal growth, multi-layer super lattice structure growth and so on.

Wherein, the composition material of the channel layer may at least be selected from but not limited to GaN, InGaN, AlGaN, AlInN or AlInGaN.

Wherein, the composition material of the third semiconductor layer may be at least selected from but not limited to p-GaN, p-AlGaN, p-AlInN, p-InGaN, p-AlInGaN.

Wherein, the composition material of the etching stop layer can be at least selected from AlN, _SiNx (0<x≤3), AlxGa1 _{- xN} (0<x<1), etc., but can also be selected from other A material with a relatively high etch selectivity between the third semiconductor (such as a p-type layer).

In some embodiments, the heterojunction further includes an insertion layer distributed between the first semiconductor layer and the second semiconductor layer.

Wherein, the composition material of the insertion layer may at least be selected from but not limited to AlN, AlInN or AlInGaN.

In some embodiments, the passivation layer further includes a SiN _x layer (0<x≦3) formed on the natural passivation layer.

Wherein, the selected etching substance can be various substances commonly used in dry etching or wet etching, preferably using a dry etching process, such as IBE (Ion Beam Etch, ion beam etching), ICP (Inductive Coupled Plasma, inductively coupled plasma) and so on.

More preferably, the selected etching substance can be selected from an etching gas containing oxygen.

In some embodiments, the HEMT further includes a substrate, and a buffer layer is distributed between the substrate and the heterojunction.

Wherein, the substrate may be a substrate such as sapphire, silicon carbide, gallium nitride, aluminum nitride, etc., but is not limited thereto.

Wherein, the material of the buffer layer can be commonly used in the industry, such as GaN, AlGaN, etc.

Wherein, the source electrode and the drain electrode form ohmic contacts with the epitaxial structure of the HEMT.

In addition, the HEMT also has a field plate structure.

The materials of the aforementioned source electrode, drain electrode, gate electrode, etc. may be commonly used in the industry, for example, W, Ni, Au, etc. may be used.

One aspect of the present invention also provides a method for preparing a group III nitride-enhanced HEMT based on a p-type layer, which includes:

On the substrate, a first semiconductor layer body as a channel layer, a second semiconductor layer as a barrier layer, and a third semiconductor layer capable of forming a heterojunction with the second semiconductor layer are sequentially grown, wherein, relative to the selected A certain etching substance, the composition material of the region adjacent to the third semiconductor layer in the second semiconductor layer has higher etching resistance than the composition material of the third semiconductor layer,

Alternatively, the substrate is sequentially grown to form a first semiconductor layer as a channel layer, a second semiconductor layer as a barrier layer, an etching stop layer, and a third semiconductor capable of forming a heterojunction with the second semiconductor layer layer, wherein, relative to the selected etching substance, the composition material of the etching stop layer has higher etching resistance than the composition material of the third semiconductor layer;

forming a gate electrode material layer on the third semiconductor layer, setting a patterned mask on the gate electrode material layer, and etching the gate electrode material layer and the third semiconductor layer to form a gate electrode, and exposing the second semiconductor layer or the etch stop layer;

And, a source electrode and a drain electrode are provided on the device formed by the aforementioned steps, thereby obtaining the HEMT.

In some embodiments, the preparation method may further include: setting a patterned mask on the gate electrode material layer, and etching the third semiconductor layer with a selected etching substance until the etching substance The etching is stopped after reacting with a local area of the surface layer of the second semiconductor layer or a local area of the surface layer of the etching stop layer to form a natural passivation layer in situ.

Wherein, the constituent materials of the barrier layer, the channel layer, and the etch stop layer may be as described above.

More preferably, the preparation method may further include: after forming the gate electrode, disposing a passivation layer on the surface of the obtained device, processing and forming a window region on the passivation layer, and then disposing a source in the window region electrode and drain electrode, thereby obtaining the HEMT.

More preferably, the preparation method may further include: after growing and forming the third semiconductor layer, performing isolation treatment on the active region of the obtained device, and then disposing a gate electrode material layer on the third semiconductor layer.

In some embodiments, the preparation method may further include: growing and forming an insertion layer between the first semiconductor layer and the second semiconductor layer.

In some embodiments, the preparation method may further include: growing and forming a buffer layer between the substrate and the heterojunction.

Aiming at the existing p-type gate technology, the invention effectively solves the problems of precise etching and etching damage of the p-type layer in the chip process by epitaxially growing the etching stop layer on the epitaxial layer of the material, and effectively conducts the active region of the enhanced HEMT. protection and improve the performance of enhanced HEMT devices. On this basis, combined with a suitable etching process, the formation of a natural passivation layer on the semiconductor surface is completed in situ during the etching process. The surface damage caused by the process (mainly caused by plasma bombardment) and the resulting deterioration of the electrical properties of the material mainly include the increase in the square resistance and the significant current collapse effect.

The technical solution of the present invention will be explained in more detail below in conjunction with several embodiments and accompanying drawings. Also, the various product structure parameters, various reaction participants and process conditions adopted in the following examples are all typical examples, but through a large number of experiments by the inventor of the present case, other listed above Different structural parameters, other types of reaction participants and other process conditions are also applicable, and can also achieve the claimed technical effects of the present invention.

Embodiment 1 The structure of the HEMT is shown in Figure 11, which includes a buffer layer formed on the substrate, an AlxGa1 _{- xN} /GaN heterojunction (x=0.1-0.35), an AlN etch stop layer, Passivation layer, source electrode (referred to as source), drain electrode (referred to as drain), gate electrode (referred to as gate), etc. Wherein, the substrate may be a substrate such as sapphire, silicon carbide, gallium nitride, aluminum nitride, etc., but is not limited thereto. The material of the buffer layer can be commonly used in the industry, for example, GaN, AlGaN, etc. can be used.

A method for preparing the HEMT provided in this embodiment may include the following steps:

S1: MOCVD epitaxial growth of HEMT based on AlGaN/GaN heterojunction. Among them, the Al composition x of the AlGaN barrier layer is 10%-35%, and the thickness is 5-25nm; the AlN insertion layer is about 1nm; the GaN channel layer is 50-200nm, and the HEMT epitaxial structure is shown in Figure 2.

S2: An AlN etch stop layer grown by MOCVD with a thickness of 0.5-5 nm, as shown in FIG. 3 .

S3: MOCVD epitaxial growth of p-GaN with a thickness of 5-300nm and a magnesium doping concentration range of 10 ¹⁸ -10 ²¹ /cm ³ , as shown in FIG. 4 . However, it should be noted that the magnesium doping concentration is not limited to a single doping concentration, and may also be a function of the z-direction of the epitaxial growth.

S4: Active area isolation. N ion implantation technology is used for isolation, the ion implantation energy is 150-400KeV ion implantation, the implanted ion dose is 10 ¹² -10 ¹⁴ /cm ² , and the implantation depth is about 50-250nm beyond the buffer layer, as shown in Figure 5 .

S5: Gate metal deposition. Magnetron sputtering is used to deposit tungsten (W) metal with a thickness of 50-200 nm, as shown in FIG. 6 .

S6: gate metal and p-GaN etching. Use photoresist AZ5214 as a mask to perform plasma etching on the non-gate area: first, use IBE (Ion Beam Etch, ion beam etching) to etch tungsten metal; secondly, use ICP (Inductive Coupled Plasma, inductor Coupled plasma) etching technology to etch p-GaN, in the etching gas Cl ₂ /BCl ₃ /N ₂ /O ₂ , the volume ratio of oxygen content is 2%-70%, and the etching rate is controlled at 5-40nm /min. The etch depth of p-GaN is controlled by the AlN etch stop layer, the AlN etch stop layer can be etched within 0-5nm, and the oxide layer Al2O3 is formed with a thickness of about 0.5-5nm. As shown in Figure 7.

S7: Passivation layer deposition. By PECVD, ICP-CVD, LPCVD and other dielectric layer deposition techniques, the SiN _x (0<x≤3) passivation layer is deposited with a thickness of 50-500 nm, as shown in FIG. 8 .

S8: Opening windows by etching the passivation layer. SiN _x is etched by RIE (Reactive Ion Etch, Reactive Ion Etching) to realize ohmic contact opening, as shown in FIG. 9 .

S9: Preparation of source-drain ohmic contacts and source-field plates. Preparation conditions: metal Ti/Al/Ni/Au, thickness 20nm/130nm/50nm/150nm, annealing condition 890°C, 30s, nitrogen atmosphere, as shown in Figure 10.

S10: lead electrodes. Preparation conditions: metal Ni/Au, thickness 50nm/400nm, as shown in FIG. 11 .

Example 2 The structure of the HEMT is shown in Figure 14, which includes a buffer layer formed on the substrate, an AlxGa1 _{- xN} /GaN heterojunction (x=0.1-0.4), a passivation layer, and a source electrode (referred to as source), drain electrode (referred to as drain), gate electrode (referred to as gate) and so on. In the barrier layer, the Al composition changes stepwise with the growth z direction, and the high Al composition AlGaN is used as the etching stop layer (Al _0.4 Ga _0.6 N).

A method for preparing the HEMT provided in this embodiment may include the following steps:

S1: MOCVD epitaxial growth of HEMT based on AlGaN/GaN heterojunction. Among them, the Al composition x of the AlGaN barrier layer is 10%, 20%, 30%, and 40% along the epitaxial growth z direction, and the thickness of the barrier layer is 5-25nm; the AlN insertion layer is about 1nm; the GaN channel layer is 50-200nm, the HEMT epitaxial structure is shown in Figure 12a-Figure 12b.

S2: MOCVD epitaxial growth of p-GaN with a thickness of 5-300nm and a magnesium doping concentration range of 10 ¹⁸ -10 ²¹ /cm ³ , as shown in FIG. 13 .

S3-S9: Same as S4-S10 in Example 1. In "gate metal and p-GaN etching", AlGaN with high Al composition in the barrier layer, that is, Al _0.4 Ga _0.6 N is used as the etch stop layer, and the high etching selectivity ratio between it and p-GaN is used , to control the p-GaN etch depth. At the same time, the ICP etching is carried out by an etching gas containing oxygen Cl ₂ /BCl ₃ /N ₂ /O ₂ , the volume ratio of oxygen content is 2%-70%, and the thickness of the formed oxide layer Al2O3 is controlled at 0.5-5nm. The device after completing the entire chip process is shown in Figure 14.

The structure of Embodiment 3 HEMT is shown in Figure 17, which includes a buffer layer formed on the substrate, an AlxGa1 _{- xN} /GaN heterojunction (x=0.1-0.4), a passivation layer, and a source electrode (referred to as source), drain electrode (referred to as drain), gate electrode (referred to as gate) and so on. In the barrier layer, the Al composition changes linearly and stepwise with the growth z direction. The barrier layer has a high Al composition AlGaN as the etch stop layer (Al _0.4 Ga _0.6 N)

A method for preparing the HEMT provided in this embodiment may include the following steps:

S1: MOCVD epitaxial growth of HEMT based on AlGaN/GaN heterojunction. Wherein, the Al composition x of the AlGaN barrier layer changes linearly along the z-direction of epitaxial growth at first, and the variation range of the Al composition is 10% to 30%; then, the Al composition x remains at 40%. The thickness of the barrier layer is 5-25nm; the AlN insertion layer is about 1nm; the GaN channel layer is 50-200nm, and the HEMT epitaxial structure is shown in Figure 15a-Figure 15b.

S2: MOCVD epitaxial growth of p-GaN with a thickness of 5-300nm and a magnesium doping concentration range of 10 ¹⁸ -10 ²¹ /cm ³ , as shown in FIG. 16 .

S3: Same as S4-S10 in Example 1. In "gate metal and p-GaN etching", AlGaN with high Al composition in the barrier layer, that is, Al _0.4 Ga _0.6 N is used as the etch stop layer, and the high etching selectivity ratio between it and p-GaN is used , to control the p-GaN etch depth. Simultaneously, ICP etching is carried out by oxygen-containing etching gas Cl ₂ /BCl ₃ /N ₂ /O ₂ , the volume ratio of oxygen content is 2%-70%, and the thickness of the formed oxide layer Al ₂ O ₃ is controlled at 0.5-5nm. The device after completing the entire chip process is shown in Figure 17.

The structure of Embodiment 4 HEMT is shown in Figure 20, which includes a buffer layer formed on the substrate, an AlxGa1 _{- xN} /GaN heterojunction (x=0.1-0.5), a passivation layer, and a source electrode (referred to as source), drain electrode (referred to as drain), gate electrode (referred to as gate) and so on. Among them, the barrier layer is a multi-layer heterojunction structure, and the high Al composition AlGaN is used as the etching stop layer (Al _0.4 Ga _0.6 N/Al _0.5 Ga _0.5 N)

A method for preparing the HEMT provided in this embodiment may include the following steps:

S1: MOCVD epitaxial growth of HEMT based on AlGaN/GaN heterojunction. Wherein, the Al composition x of the AlGaN barrier layer changes along the epitaxial growth z direction as shown in Fig. 18a-Fig. 18b. The thickness of the barrier layer is 5-25nm; the AlN insertion layer is about 1nm; the GaN channel layer is 50-200nm.

S2: MOCVD epitaxial growth of p-GaN, with a thickness of 5-300 nm, and a magnesium doping concentration range of 10 ¹⁸ -10 ²¹ /cm ³ , as shown in FIG. 19 .

S3: Same as S4-S10 in Example 1. In "Gate Metal and p-GaN Etching", AlGaN with high Al composition in the barrier layer, that is, Al _0.4 Ga _0.6 N/Al _0.5 Ga _0.5 N is used as the etch stop layer, and the comparison between it and p-GaN High etching selectivity, control the etching depth of p-GaN. Simultaneously, ICP etching is carried out by oxygen-containing etching gas Cl ₂ /BCl ₃ /N ₂ /O ₂ , the volume ratio of oxygen content is 2%-70%, and the thickness of the formed oxide layer Al ₂ O ₃ is controlled at 0.5-5nm. The device after completing the entire chip process is shown in Figure 20.

It should be noted that, in this document, the terms "comprising", "comprising" or any other variation thereof are intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements, It also includes other elements not expressly listed, or elements inherent in the process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

The foregoing is only a specific embodiment of the present invention. It should be pointed out that for those of ordinary skill in the art, some improvements and modifications can also be made without departing from the principle of the present invention. It should be regarded as the protection scope of the present invention.

Claims (10)

1. a kind of group III-nitride enhancement mode HEMT based on p-type layer, comprise main by as channel layer the first semiconductor layer and Hetero-junctions as the second semiconductor layer composition of barrier layer and the source electrode, gate electrode and the drain electrode that are connected with described hetero-junctions, Threeth semiconductor layer that can with second semiconductor layer form hetero-junctions is also distributed with, its feature exists between described gate electrode and barrier layer In：

Etch stop layer is also distributed between described 3rd semiconductor layer and the second semiconductor layer, and, with respect to selected engraving Matter, the composition material of described etch stop layer has higher etch resistant performance than the composition material of described 3rd semiconductor layer；

Or, with respect to selected etching material, the group in the region closed on the 3rd semiconductor layer in described second semiconductor layer is become a useful person Material has higher etch resistant performance than the composition material of the 3rd semiconductor layer.

2. group III-nitride enhancement mode HEMT based on p-type layer according to claim 1 is it is characterised in that described etching is whole Only it is additionally provided with passivation layer on layer or the second semiconductor layer, described passivation layer includes the partial zones at least by described etch stop layer top layer The regional area on domain or the second semiconductor layer top layer and the described natural passivation layer etching substance reaction and being formed in situ.

3. group III-nitride enhancement mode HEMT based on p-type layer according to claim 1 it is characterised in that：

The composition material of described barrier layer is at least selected from Al_xIn_yGa_zN(0<X≤1,0≤y≤1, (x+y+z)=1)；

And/or, the composition material of described channel layer includes any one in GaN, InGaN, AlGaN, AlInN, AlInGaN Plant or two or more combinations；

And/or, the composition material of described 3rd semiconductor layer includes p-GaN, p-AlGaN, p-AlInN, p-InGaN, p-AlInGaN In any one or two or more combinations；

And/or, the composition material of described etch stop layer includes AlN, SiN_x(0<x≤3)、Al_xGa_1-xN(0<x<1) In any one or two or more combinations；

Preferably, the composition material of described barrier layer is selected from Al_xIn_yGa_zN(0<X≤1,0≤y≤1, (x+y+z)=1), its In along from first semiconductor layer point to the 3rd semiconductor layer direction, x totally be in increase trend.

4. group III-nitride enhancement mode HEMT based on p-type layer according to any one of claim 1-3 it is characterised in that Described selected etching material is at least selected from the etching gas containing aerobic.

5. group III-nitride enhancement mode HEMT based on p-type layer according to any one of claim 1-3 it is characterised in that Described hetero-junctions also includes the interposed layer being distributed between the first semiconductor layer and the second semiconductor layer；

Preferably, the composition material of described interposed layer include in AlN, AlInN, AlInGaN any one or two or more Combination.

6. a kind of preparation method of group III-nitride enhancement mode HEMT based on p-type layer is it is characterised in that include：

On substrate, growth is formed as the first semiconductive layer body of channel layer, the second semiconductor layer as barrier layer and energy successively Form the 3rd semiconductor layer of hetero-junctions with the second semiconductor layer, wherein, with respect to selected etching material, described second quasiconductor The composition material in the region closed on the 3rd semiconductor layer in layer has higher etch resistance than the composition material of the 3rd semiconductor layer Can,

Or, on substrate successively growth formed as the first semiconductive layer body of channel layer, the second semiconductor layer as barrier layer, Etch stop layer and the 3rd semiconductor layer that hetero-junctions can be formed with the second semiconductor layer, wherein, with respect to selected etching material, The composition material of described etch stop layer has higher etch resistant performance than the composition material of described 3rd semiconductor layer；

Described 3rd semiconductor layer forms layer of gate electrode material, then pattern mask is set in described layer of gate electrode material, And layer of gate electrode material and the 3rd semiconductor layer are performed etching, thus forming gate electrode, and make the second semiconductor layer or etching eventually Only layer exposes；

And, setting source electrode and drain electrode on the device being formed by abovementioned steps, thus obtain described HEMT.

7. preparation method according to claim 6 is it is characterised in that include：Figure is arranged on described layer of gate electrode material Change mask, and performed etching with selecting engraving confrontation the 3rd semiconductor layer, until described etching material and the second semiconductor layer table The regional area on the regional area of layer or etch stop layer top layer stops etching after reacting and being formed in situ nature passivation layer.

8. the preparation method according to any one of claim 6-7 it is characterised in that：The composition material of described barrier layer is at least Selected from Al_xIn_yGa_zN(0<X≤1,0≤y≤1, (x+y+z)=1)；

And/or, the composition material of described channel layer includes any one in GaN, InGaN, AlGaN, AlInN, AlInGaN Plant or two or more combinations；

And/or, the composition material of described 3rd semiconductor layer includes p-GaN, p-AlGaN, p-AlInN, p-InGaN, p-AlInGaN In any one or two or more combinations；

And/or, the composition material of described etch stop layer includes AlN, SiN_x(0<x≤3)、Al_xGa_1-xN(0<x<1) In any one or two or more combinations；

Preferably, the composition material of described barrier layer is selected from Al_xIn_yGa_zN(0<X≤1,0≤y≤1, (x+y+z)=1), its In along from first semiconductor layer point to the 3rd semiconductor layer direction, x totally be in increase trend.

9. the preparation method according to any one of claim 6-7 is it is characterised in that described selected etching material is at least selected from and contains The etching gas of aerobic.

10. preparation method according to claim 6 is it is characterised in that also include：After forming gate electrode, in obtained device Surface arranges passivation layer, and processing forms window region on described passivation layer, setting source electrode and leakage in described window region afterwards Electrode, thus obtain described HEMT.