CN106298677A - Semiconductor memory and manufacture method thereof - Google Patents

Abstract

A kind of semiconductor memory and manufacture method thereof.Described method includes: provide Semiconductor substrate, form tunnel oxide on the semiconductor substrate, after described tunnel oxide surface forms selection grid and floating grid, formed on described floating grid surface and between control gate, and described floating grid and control gate, be formed with dielectric layer between grid.The present invention by the dual polysilicon layers grid structure that formed by floating grid and control gate, the running voltage greatly reducing memorizer, the reaction rate accelerating memorizer, improves the data storage capacities of memorizer, is more beneficial for the miniaturization of device.

Description

Semiconductor memory and manufacturing method thereof

technical field

The present invention relates to the field of semiconductors, in particular to a semiconductor memory and a manufacturing method thereof, especially to an MTP (Multi-Time Programmable, multi-time programmable) memory.

Background technique

With the continuous improvement of performance requirements of electronic equipment, MTP memory is more and more widely used as a storage device of various electronic equipment. MTP memory has multiple data storage, reading and erasing operations. It can store data without continuously applying electric energy and the stored data will not disappear after power off, and the data can be realized by applying a certain voltage. erasure.

FIG. 1A is a top view of a conventional MTP memory, and FIG. 1B is a cross-sectional view of the structure along the direction A-A' in FIG. 1 . A traditional MTP memory is a dual-transistor device, including a semiconductor substrate 100; a device isolation structure 101 is formed in the semiconductor substrate 100, and the device isolation structure 101 defines an active region 103; the unit MTP memory 102 also includes a selection Gate 104 , floating gate 105 , tunnel oxide layer 106 , sidewall layer 107 , source region 109 and drain region 108 .

Taking the P-type traditional MTP memory as an example, when the MTP memory is programmed, the corresponding unit memory is selected by applying a certain voltage to the selection gate 104; 105 transitions from the conductive channel 110 under the tunnel oxide layer 106 to the floating gate 105, and then completes the data writing operation; a negative voltage is applied to the replica gate 105, and electrons are transferred from the floating gate 105 Tunneling into the conductive channel 110 through the tunneling oxide layer 106 to complete the data erasing work.

However, for the MTP memory under this process, the voltage is directly applied to the floating gate 105 , and the function of data storage is realized only through the channel vertical electric field. The applied voltage is more than 8 megavolts per square centimeter, and the reaction rate is relatively slow, which is more than 2-10 milliseconds, and the thicker the tunnel oxide layer 106, the greater the required applied voltage, and the slower the reaction rate of the memory. It affects the data reading ability of the memory; at the same time, there is no protective layer on the surface of the floating gate 105, and the stored charges are easily lost, thereby weakening the data storage ability of the memory.

Furthermore, devices in the logic area need to be connected to other circuits or external circuits through contact holes and metal layers. However, with the development of miniaturization of devices, the process of forming contact holes on the surface of the active region is also constantly challenged. The spacing control of the electrodes and whether the active area can completely cover the contact hole area have become technological issues that need to be broken through in the development of device miniaturization.

Contents of the invention

The problem solved by the present invention is to provide a semiconductor memory and its manufacturing method, which can effectively reduce the working voltage, speed up the reading and writing speed of the memory, improve the data storage capacity of the memory, and at the same time facilitate the miniaturization of devices.

To solve the above problems, the present invention provides a method for manufacturing a semiconductor memory. Including the following steps:

A semiconductor substrate is provided, the semiconductor substrate includes a plurality of memory cell regions, each memory cell region includes an isolation region and an active region;

forming a tunnel oxide layer on the semiconductor substrate in the active region of the memory cell region;

Corresponding selection gates and floating gates are formed on the surface of the tunnel oxide layer in each memory cell area, the selection gates are formed in the active area, and the floating gates are formed in the active area and the isolation area , and the selection gate and the floating gate are spaced apart from each other;

forming an inter-gate dielectric layer on the surface of the floating gate in the isolation region;

forming a control gate on the surface of the inter-gate dielectric layer;

Ions are implanted into the semiconductor substrate in the active region to form source and drain electrodes in the selection gate and the floating gate.

Optionally, the inter-gate dielectric layer is a single-layer structure or a stacked structure.

Optionally, the inter-gate dielectric layer has a single-layer structure, and the inter-gate dielectric layer is a silicon oxide layer.

Optionally, the inter-gate dielectric layer has a single-layer structure, and the silicon oxide layer is formed by chemical vapor deposition.

Optionally, the inter-gate dielectric layer is a stacked structure, the inter-gate dielectric layer is a double-layer structure composed of a silicon oxide layer and a silicon nitride layer, or the inter-gate dielectric layer is a silicon oxide layer and a silicon nitride layer A three-layer structure consisting of a silicon oxide layer and a silicon oxide layer.

Optionally, the inter-gate dielectric layer has a stacked structure, and the process for forming the silicon oxide layer and the silicon nitride layer is a chemical vapor deposition method.

Optionally, the selection gate, the floating gate and the control gate are made of polysilicon.

Optionally, the process for forming the selection gate and the floating gate is as follows:

forming a polysilicon layer on the surface of the tunnel oxide layer;

forming a mask layer on the surface of the polysilicon layer;

Patterning the mask layer to expose part of the surface of the polysilicon layer, the shape, size and position of the patterned mask layer are the same as those of the subsequently formed selection gate and floating gate;

Using the patterned mask layer as a mask, etching the polysilicon layer along the exposed area of the polysilicon layer until the surface of the semiconductor substrate is exposed, forming a selection gate and a floating gate on the same plane.

Optionally, the process for forming the control gate is:

forming an inter-gate dielectric layer on the semiconductor substrate, the inter-gate dielectric layer covering the selection gate and the floating gate;

forming a polysilicon layer on the surface of the inter-gate dielectric layer;

forming a mask layer on the surface of the polysilicon layer;

Patterning the mask layer to expose part of the surface of the polysilicon layer, the shape, size and position of the patterned mask layer being the same as the shape, size and position of the subsequently formed control gate;

Using the patterned mask layer as a mask, sequentially etch the polysilicon layer and the intergate dielectric layer along the exposed polysilicon layer region until the surface of the floating gate is exposed, forming the floating gate located in the isolation region. Place the control gate on the gate surface.

Optionally, the process of forming the polysilicon layer of the control gate is a furnace tube growth method.

Optionally, the process temperature for forming the polysilicon layer of the control gate is 500°C-700°C.

Optionally, the process of etching the polysilicon layer is a plasma dry etching process.

Optionally, the ratio of the thickness of the selection gate to the thickness of the control gate is 2:1 to 1:1, and the ratio of the thickness of the floating gate to the thickness of the control gate is 2:1. to 1:1.

Optionally, the method further includes: forming a sidewall layer on the sidewalls of the floating gate, the control gate and the selection gate.

Optionally, the method further includes: after forming the source and drain, forming a salicide layer in a part of the active region other than the control gate.

The present invention also provides a semiconductor memory, comprising:

a semiconductor substrate, the semiconductor substrate comprising a plurality of memory cell regions, each memory cell region including an isolation region and an active region;

a tunnel oxide layer located on the active region of each memory cell region;

a select gate on the surface of the tunnel oxide layer in the active region;

The floating gate is located on the surface of the tunnel oxide layer in the active region and the isolation region, and the selection gate and the floating gate are spaced apart from each other;

an inter-gate dielectric layer located on the surface of the floating gate in the isolation region;

a control gate located on the surface of the inter-gate dielectric layer;

The source and drain are located in the semiconductor substrate below the select gate and the floating gate of the active region.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the technical solution of the present invention, the control gate is formed on the surface of the floating gate. Through the channel hot hole induced hot electron (CHHIHE) process, the channel transverse electric field and vertical electric field act at the same time, and more hot electrons are generated after ion collision, and the hot electrons pass through the vertical electric field and pass through the tunnel oxidation faster layer into the floating gate to realize the data storage function, which greatly reduces the operating voltage of the memory and accelerates the reaction rate of the memory, which is only 10 microseconds to 20 microseconds. In addition, if the control gate is located on the surface of the floating gate in the active region, once a voltage is applied to the control gate, it will cause all devices to be connected, including devices that should not be connected, thereby causing damage to the electrical performance of the device. offset, and even cause device damage, so the control gate is only formed in the isolation region of the memory cell region.

Further, an inter-gate dielectric layer of a single-layer structure or a stacked structure is formed between the floating gate and the control gate. When the inter-gate dielectric layer is a single-layer structure, the inter-gate dielectric layer is a silicon oxide layer; when the inter-gate dielectric layer is a stacked structure, the inter-gate dielectric layer is a silicon oxide layer and a nitride A double-layer structure composed of a silicon layer or a three-layer structure composed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. Both the silicon oxide layer and the silicon nitride layer can be used as an insulating layer to prevent the loss of charge stored in the floating gate and cause the data storage capacity of the memory to be weakened, and can also form capacitance with the floating gate and the control gate; At the same time, the silicon nitride layer has a higher electronic permittivity. Under the same physical thickness, the typical thickness of the silicon nitride layer is close to twice that of the silicon oxide layer. Compared with the silicon oxide layer, electrons must pass through the silicon nitride layer More energy is required, and the silicon nitride layer has greater stress, and it needs to be matched with a silicon oxide layer to reduce the stress, so that it is easier to match with the floating gate and the control gate to form a capacitor structure with better performance.

Furthermore, the control gate is not only formed on the surface of the floating gate in the memory region, but also formed on the sidewall of the gate of the device in the logic region, the surface of the active region and the surface of the shallow trench isolation region. In the traditional process, the contact hole and the first metal layer are used as the intermediary layer between the device active area and the device gate or between the device and the device. The distance between the contact hole and the gate and whether the contact hole is completely located in the device active area The area becomes an important factor affecting the electrical performance and yield of the device, and the size of the contact hole directly limits the miniaturization of the active area of the device; and in the solution of the present invention, the control gate is used as the active area of the connected device The intermediary layer between the gate of the device and between the device and the device does not need to consider the position of the contact hole in the active area, which is beneficial to the reduction of the size of the active area of the device, thereby promoting the miniaturization of the device.

Description of drawings

FIG. 1A is a top view of a conventional semiconductor memory.

Fig. 1B is a structural sectional view along line A-A' in Fig. 1A.

FIG. 2A is a top view of a semiconductor memory according to an embodiment of the present invention.

Fig. 2B is a cross-sectional view of the structure along line A-A' in Fig. 2A.

Fig. 2C is a structural sectional view along line B-B' in Fig. 2A.

3 to 4 are structural sectional views along line A-A' of each step of the semiconductor memory manufacturing method according to the embodiment of the present invention.

5 to 7 are structural sectional views along line B-B' of each step of the semiconductor memory manufacturing method according to the embodiment of the present invention.

detailed description

The working principle of traditional semiconductor memory is to directly apply a voltage on the floating gate, and inject the charge in the channel into the floating gate through the tunnel oxide layer through the vertical electric field of the channel, which has the defects of high working voltage and slow reaction rate. ; At the same time, there is no protective layer on the surface of the floating gate, and the injected charges are easily lost through the surface of the floating gate, thereby weakening the data storage capacity of the memory.

After research and analysis by the inventors of the present invention, it is found that sequentially forming an inter-gate dielectric layer and a control gate on the surface of the floating gate can solve the performance defects of the traditional semiconductor memory. Taking a P-type device as an example, a negative voltage of -0.7 volts to -2.3 volts is applied to the control gate. Under the voltage range, more hot electrons can be generated, and through the channel hot hole induced hot electron (CHHIHE) process, The lateral electric field and vertical electric field of the channel act at the same time, and more hot electrons are generated after ion collision, which promotes hot electrons to enter the floating gate faster through the tunnel oxide layer to realize the data storage function, which greatly reduces the working time of the memory. The voltage speeds up the reaction rate of the memory; and the inter-gate dielectric layer formed between the surface of the floating gate and the control gate acts as a protective layer for the floating gate to prevent damage caused by the loss of charge in the floating gate. Memory data storage capacity is weakened. In addition, when the control gate is located on the surface of the floating gate in the active region, once a voltage is applied to the control gate, it will cause all devices to be connected, including devices that should not be connected, thereby causing the electrical performance of the device to deteriorate. offset, and even cause device damage, so the control gate is located on the surface of the floating gate in the isolation region.

After further research by the inventors of the present invention, the control gate required to be formed in the technical solution of the present invention is also formed on the sidewall of the gate of the device in the logic region, the surface of the active region and the surface of the shallow trench isolation region. The control gate is used as the connection intermediary layer between the active area of the device in the logic area and the gate of the device, and between the device and the device. Limitations, which in turn promote the development trend of device miniaturization.

FIG. 2A is a top view of a semiconductor memory according to an embodiment of the present invention. Fig. 2B is a cross-sectional view of the structure along line A-A' in Fig. 2A. Fig. 2C is a structural sectional view along line B-B' in Fig. 2A.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

3 to 4 are structural sectional views along line A-A' of each step of the semiconductor memory manufacturing method according to the embodiment of the present invention.

5 to 7 are structural sectional views along line B-B' of each step of the semiconductor memory manufacturing method according to the embodiment of the present invention.

Referring to FIG. 3 , a semiconductor substrate 200 is provided, the semiconductor substrate 200 contains silicon, the semiconductor substrate includes several memory cell regions, each memory cell region includes an isolation region and an active region. An ion implantation process is performed on the semiconductor substrate 200 to form an N-type well or a P-type well 205 (refer to FIG. 2A ) in the semiconductor substrate 200; After the trench is filled with the isolation dielectric layer, an isolation region 211 is formed (refer to FIG. 2C ), and the shallow trench isolation structure defines the active region 201 of the device (refer to FIG. 2A ). A tunnel oxide layer 209 and a polysilicon layer 214 are sequentially formed on the semiconductor substrate 200 in the memory cell region.

In this embodiment, the tunnel oxide layer 209 may be a silicon oxide layer, the process of forming the tunnel oxide layer 209 is a thermal oxidation growth method, and the reaction gas may be nitrous oxide or a mixed gas of nitrous oxide and oxygen. Or a mixture of nitrous oxide, oxygen and inert gases. In this embodiment, the reaction gas is nitrous oxide, and the specific process for forming the tunneling oxide layer 209 may be: oxidize the semiconductor substrate 200 with nitrous oxide in a hot oxygen environment, and on the semiconductor substrate 200 Forming the tunneling oxide layer 209, the temperature of the thermal oxidation environment is 700°C-1100°C, the pressure is 5 Torr-780 Torr, the reaction time is 5 seconds-60 seconds, and the gas flow rate of the reaction gas nitrous oxide is 5slm-15slm .

In this embodiment, the process of forming the polysilicon layer 214 is a furnace tube growth method, and the reaction gas is a silicon source gas. In this embodiment, silane is used as the reaction gas to form the polysilicon layer 214, the flow rate of the reaction gas is 100 sccm-500 sccm, the reaction time is 10 milliseconds-60 milliseconds, the reaction temperature is 500° C.-700° C., and the pressure is 0.1 Torr-300 Torr.

Referring to FIG. 4 , a patterned mask layer 215 is formed on the surface of the polysilicon layer 214 (as shown in FIG. 3 ), and the patterned mask layer 215 is used as a mask to sequentially etch the polysilicon layer along the exposed polysilicon layer region. The polysilicon layer 214 (as shown in FIG. 3 ) and the tunnel oxide layer 209 (as shown in FIG. 3 ) form the select gate 202 and the floating gate 203 on the same plane.

In this embodiment, the process of forming the selection gate 202 and the floating gate 203 may specifically be: forming a mask layer 215 on the surface of the polysilicon layer 214 (as shown in FIG. 3 ), and patterning the mask layer 215 to expose Part of the surface of the polysilicon layer 214, the shape, size and position of the patterned mask layer are the same as those of the subsequently formed select gate and floating gate; the patterned mask layer 215 is mask, along the exposed polysilicon layer region, the polysilicon layer 214 and the tunnel oxide layer 209 are sequentially etched by a plasma dry etching process until the surface of the semiconductor substrate 200 is exposed, forming a selection gate located on the same plane 202 and floating gate 203; the selection gate is formed in the active region, the floating gate is formed in the active region 201 (refer to FIG. 2A ) and the isolation region 211 (refer to FIG. 2C ), and the selection The gate 202 and the floating gate 203 are spaced apart from each other. After the selection gate 202 and the floating gate 203 are formed, the patterned mask layer 215 is removed by a wet or ion ashing process.

In this embodiment, the main etching gases used in the plasma dry etching process are chlorine and hydrogen bromide, and a mixed gas of helium and oxygen is used as an auxiliary gas. The flow rate of chlorine gas is 45 sccm-50 sccm, and hydrogen bromide The gas flow rate is 120sccm-150sccm, the total gas flow rate of helium and oxygen is 4sccm-8sccm, and the flow ratio of helium and oxygen in the mixed gas of helium and oxygen is 7:3.

Referring to FIG. 5 , an inter-gate dielectric layer 212 is formed on the surface of the floating gate 203 in the isolation region 211 (refer to FIG. 2C ), and a control gate 204 is formed on the surface of the inter-gate dielectric layer 212 .

In this embodiment, the process of forming the control gate 204 may specifically be: forming an inter-gate dielectric layer 212 on the semiconductor substrate 200, and the inter-gate dielectric layer 212 covers the selection gate 202 (such as 4) and floating gate 203; form a polysilicon layer on the surface of the inter-gate dielectric layer 212, and then form a mask layer on the surface of the polysilicon layer; pattern the mask layer to expose part of the polysilicon layer , the shape, size and position of the patterned mask layer are the same as those of the subsequently formed control gate 204; using the patterned mask layer as a mask, along the exposed polysilicon layer region The polysilicon layer and the intergate dielectric layer 212 are sequentially etched by a plasma dry etching process until the surface of the floating gate 203 is exposed to form the floating gate located in the isolation region 211 (refer to FIG. 2C ). 203 surface of the control grid 204 .

In this embodiment, the inter-gate dielectric layer 212 and the control gate 204 are located on the surface of the floating gate 203 in the isolation region 211 (refer to FIG. 2C ). When the control gate 204 is located on the surface of the floating gate 203 in the active region 201 (refer to FIG. 2A ), once a voltage is applied to the control gate 204, it will cause all devices to be connected, including those that should not be connected. The device, which will cause the deviation of the electrical performance of the device, and even cause the damage of the device.

Since the control gate 204 is not only formed on the surface of the floating gate 203 in the memory area, but also on the gate sidewall of the device in the logic region, the surface of the active region, and the surface of the isolation region, the control gate 204 is used as a connecting device The intermediary layer between the active area and the device gate, and between the device and the device, for the device in the logic area, it is not necessary to consider the position of the contact hole in the active area, which is beneficial to the reduction of the size of the active area of the device, thereby promoting development of device miniaturization.

In this embodiment, the inter-gate dielectric layer 212 may have a single-layer structure or a stacked-layer structure. When the inter-gate dielectric layer 212 has a single-layer structure, the inter-gate dielectric layer 212 is a silicon oxide layer; when the inter-gate dielectric layer 212 has a stacked structure, the inter-gate dielectric layer 212 is a silicon oxide layer. A double-layer structure consisting of a silicon nitride layer and a silicon nitride layer or a three-layer structure consisting of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.

The silicon oxide layer or the silicon nitride layer can be used as an insulating layer to prevent the loss of charge stored in the floating gate and cause the data storage capacity of the memory to be weakened. The silicon oxide layer or the silicon nitride layer can also be combined with the The floating gate and the control gate form capacitance, and the silicon nitride layer has a higher electronic permittivity. Under the same physical thickness, the typical thickness of the silicon nitride layer is close to twice that of the silicon oxide layer. Compared with the silicon oxide layer Layer, electrons need more energy to pass through the silicon nitride layer; however, the silicon nitride layer has greater stress, and it needs to be matched with a silicon oxide layer to reduce the stress, making it easier to match the floating gate and the control gate To form a capacitor structure with better performance.

In this embodiment, the processes for forming the silicon oxide layer and the silicon nitride layer are both chemical vapor deposition methods. The process for forming the silicon oxide layer may specifically be: using tetraethoxysilane and oxygen as the main reaction source, the reaction temperature of this process is 400°C-600°C, the pressure is 0.5Torr-3Torr, and the oxygen flow rate is 50sccm-1000sccm. The process for forming the silicon nitride layer may specifically include: heating the reaction chamber to a certain temperature and then introducing methane and ammonia gas into the reaction chamber, and methane and ammonia react to form a silicon nitride layer. The gas ratio of methane to ammonia is 1:3-1:4, the reaction temperature is 250°C-350°C, the reaction pressure is 90Pa-130Pa, and the deposition time is 90 seconds-110 seconds.

In this embodiment, the control grid 204 is a polysilicon layer, the process of forming the control grid 204 is a furnace tube growth method, and the reaction gas is a silicon source gas. In this embodiment, silane is used as the reaction gas, the flow rate of the reaction gas is 100 sccm-500 sccm, the reaction time is 10 milliseconds-60 milliseconds, the reaction temperature is 500° C.-700° C., and the pressure is 0.1 Torr-300 Torr. Wherein, the control gate 204 can not be too thick, the ratio of the thickness of the selection gate 202 to the thickness of the control gate 204 is 2:1 to 1:1, and the thickness of the floating gate 203 and The ratio of the thickness of the control gate 204 is 2:1 to 1:1; if the control gate is too thick, it is not easy to carry out metallization and interconnection on the active area, and it will cause overlapping of the floating gate and the control gate. If the layer structure is too high, it will greatly affect the photolithography process.

In this embodiment, the main etching gases used in the plasma dry etching process are chlorine and hydrogen bromide, and a mixed gas of helium and oxygen is used as an auxiliary gas. The flow rate of chlorine gas is 45 sccm-50 sccm, and hydrogen bromide The gas flow rate is 120sccm-150sccm, the total gas flow rate of helium and oxygen is 4sccm-8sccm, and the flow ratio of helium and oxygen in the mixed gas of helium and oxygen is 7:3.

Referring to FIG. 6, a sidewall layer 210 is formed on the sidewalls of the select gate 202 (refer to FIG. 4), the floating gate 203, and the control gate 204. After forming the sidewall layer 210, the active region 201 (refer to FIG. 2A ) of the selection gate 202 (refer to FIG. 4 ) and the floating gate 203 and the semiconductor substrate 200 under the gate and implant ions to form the selection gate 202 (refer to FIG. 4 ) and the floating gate Source 206 (refer to FIG. 2B ) and drain 207 (refer to FIG. 2B ) of 203 .

The sidewall layer 210 may have a single layer structure or a stacked layer structure. When the side wall layer 210 is a single-layer structure, the side wall layer 210 is a silicon oxide layer; when the side wall layer 210 is a stacked structure, the side wall layer 210 is a silicon oxide layer and a nitride A double-layer structure composed of a silicon layer, a three-layer structure composed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. In this embodiment, the sidewall layer 210 is a silicon oxide layer with a single-layer structure, and the specific process of formation may be: forming a silicon oxide layer on the surface 200 of the semiconductor substrate, the silicon oxide layer covering the semiconductor substrate 200, selecting Gate 202 (refer to FIG. 4 ), floating gate 203, inter-gate dielectric layer 212 and control gate 204, etch the silicon oxide layer to form tunnel oxide layer 209, select gate 202, floating gate electrode 203 , intergate dielectric layer 212 and sidewall layer 210 of the sidewall of control gate 204 .

In this embodiment, the process of etching the silicon oxide layer to form the sidewall layer 210 is a plasma dry etching process, and the specific process may be: using a mixture of CHF ₃ , CH ₂ F ₂ , CH ₃ F and oxygen Gas is used as the main etching gas, wherein the CH ₃ F gas flow rate is 40sccm-80sccm, the CH ₂ F ₂ gas flow rate is 60sccm-120sccm, the CH ₃ F gas flow rate is 20sccm-40sccm, the oxygen flow rate is 80sccm-160sccm, and the reaction chamber pressure is 40mtorr-80mtorr, the response time is 10 seconds-40 seconds.

In this embodiment, the source 206 (refer to FIG. 2B ) and the drain 207 (refer to FIG. 2B ) are P-type source-drain electrodes, and the ions implanted in the source-drain region can be B or BF, and the implanted ions The energy is 1kev-30Kev, and the implanted ion dose is 5E16-5E22 atoms per square centimeter.

Referring to FIG. 7, a salicide region barrier layer 215 is formed on the surface of the control gate 204, and the semiconductor substrate 200, the salicide region barrier layer 215, the selection gate 202 (refer to FIG. 4) and the floating gate A metal layer 216 is sequentially formed on the surface of the pole 203 .

In this embodiment, since the thickness of the polysilicon layer of the control gate 204 is relatively thin, the ratio of the thickness of the polysilicon layer of the select gate 202 (refer to FIG. 4 ) to the thickness of the polysilicon layer of the control gate 204 is 2:1 to 1. :1, the ratio of the thickness of the polysilicon layer of the floating gate 203 to the thickness of the polysilicon layer of the control gate 204 is 2:1 to 1:1, and the subsequent formation of salicide needs to consume polysilicon, if in The formation of salicide on the surface of the control gate 204 will lead to thinner polysilicon layer of the control gate 204, thereby affecting the data storage and erasing performance of the memory, so the surface of the control gate 204 needs to be formed by a self-aligned silicide region The barrier layer 215 covers.

In this embodiment, the specific process for forming the barrier layer of the salicide region may be: by chemical vapor deposition, on the semiconductor substrate 200, the selection gate 202 (refer to FIG. 4 ), the floating gate 203 and the control gate A salicide region barrier layer 215 is formed on the surface of the pole 204, and the salicide region barrier layer 215 is a silicon nitride layer. The reaction gas is silane and ammonia, the flow rate of the silane is 30sccm-40sccm, the flow rate of the ammonia gas is 70sccm-90sccm, the pressure in the reaction chamber is 6Torr-10Torr, and the temperature is 350°C-450°C.

The salicide barrier layer 215 is etched to remove the silicon nitride layer in the region where the salicide layer needs to be formed, and the remaining salicide barrier layer 215 covers the surface of the control gate 204 .

In this embodiment, the process of etching the salicide region barrier layer 215 is a plasma etching process. The main etching gases are CF ₄ , CHF ₃ and CH ₃ F, and the auxiliary gases are argon and oxygen, wherein the flow rate of CF ₄ is 0sccm-100sccm, the flow rate of CHF ₃ is 0sccm-100sccm, and the flow rate of CH ₃ F is 0sccm- 100 sccm, the flow rate of argon gas is 0 sccm-200 sccm, the flow rate of oxygen gas is 0 sccm-150 sccm, the etching energy is 50 watts-800 watts, and the pressure in the etching chamber is 10 mtorr-200 mtorr.

In this embodiment, the material of the metal layer 216 is cobalt, and the process of forming the metal layer 216 is physical vapor deposition. The gas used to form the metal layer 216 is argon, the flow rate of the argon is 10 sccm-60 sccm, and the power used in this process is 500W-5000W.

Referring again to FIG. 2C, a salicide layer 213 is formed in the floating gate 203 through a 2-step annealing process.

In this embodiment, the specific process for forming the self-aligned metal silicide layer 213 may be: performing the first thermal annealing process, the temperature of the first thermal annealing process is 200°C-350°C, and the process time is 3 Seconds to 2 minutes, the gas used is one or more mixed gases of helium, argon or nitrogen. Through the first thermal annealing process, the nickel-platinum alloy of the first metal layer 216 (shown in FIG. 7 ) and the source electrode 206 (refer to FIG. 2B ) and the drain electrode 207 (refer to FIG. 2B ) in the semiconductor substrate 200 are formed. The silicon on the surface and the polysilicon on the top of part of the selection gate other than the control gate and the polysilicon on the top of part of the floating gate react to form a first metal silicide layer (not marked), and the first metal silicide is an intermediate reaction products, and the unexposed surface of silicon or polysilicon does not react with the first metal layer 216 , and the unreacted metal layer on the surface can be removed in a subsequent process.

The unreacted part of the first metal layer is removed by wet etching, and the solutions used are sulfuric acid-hydrogen peroxide mixed solution and ammonia-hydrogen peroxide mixed solution, wherein the volume ratio of sulfuric acid to hydrogen peroxide in the solution is 1:1 to 4:1, the volume ratio of ammonia to hydrogen peroxide is 2:3 to 1:1, and the solution does not react with other film layers when removing the unreacted first metal layer.

After removing the unreacted first metal layer, a second thermal annealing process is performed. The temperature of the thermal annealing process is 300°C-650°C, the process time is 3 seconds-2 minutes, and the gas used is one or more mixed gases of helium, argon or nitrogen. Through the second thermal annealing process, the first metal silicide layer is transformed into a desired salicide layer 213 , and the salicide layer 213 has characteristics of low resistivity and high thermal stability.

In addition, referring to FIG. 2A, FIG. 2B and FIG. 2C, the present invention also provides a semiconductor memory, including:

A semiconductor substrate 200, the semiconductor substrate includes several memory cell regions, each memory cell region includes an isolation region 211 and an active region 201;

a tunnel oxide layer 209, the tunnel oxide layer 209 is located on the active region 201 of each memory cell region;

a selection gate 202 located on the surface of the tunnel oxide layer 209 in the active region 201;

The floating gate 203 is located on the surface of the tunnel oxide layer 209 in the active region 201 and the isolation region 211, and the selection gate 202 and the floating gate 203 are spaced apart from each other;

an inter-gate dielectric layer 212 located on the surface of the floating gate 203 in the isolation region 211;

The control gate 204 is located on the surface of the inter-gate dielectric layer 212;

The source 206 and the drain 207 are located in the semiconductor substrate below the select gate and the floating gate.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (16)

1. A method for manufacturing a semiconductor memory, comprising: providing a semiconductor substrate comprising a plurality of memory cell regions, each memory cell region including an isolation region and an active region; forming a tunnel oxide layer on the semiconductor substrate in the active region of the memory cell region; Corresponding selection gates and floating gates are formed on the surface of the tunnel oxide layer in each memory cell area, the selection gates are formed in the active area, and the floating gates are formed in the active area and the isolation area , and the selection gate and the floating gate are spaced apart from each other; forming an inter-gate dielectric layer on the surface of the floating gate in the isolation region; forming a control gate on the surface of the inter-gate dielectric layer; Ions are implanted into the semiconductor substrate in the active region to form source and drain electrodes in the selection gate and the floating gate. 2. The method for manufacturing a semiconductor memory according to claim 1, wherein the inter-gate dielectric layer is a single-layer structure or a stacked-layer structure. 3. The method for manufacturing a semiconductor memory according to claim 2, wherein the inter-gate dielectric layer is a single-layer structure, and the inter-gate dielectric layer is a silicon oxide layer. 4. The manufacturing method of a semiconductor memory as claimed in claim 2, wherein the inter-gate dielectric layer is a stacked structure, and the inter-gate dielectric layer is a double-layer structure composed of a silicon oxide layer and a silicon nitride layer Or the inter-gate dielectric layer is a three-layer structure composed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. 5. The method for manufacturing a semiconductor memory according to claim 3, wherein the process for forming the silicon oxide layer is a chemical vapor deposition method. 6. The method for manufacturing a semiconductor memory according to claim 4, wherein the process for forming the silicon oxide layer and the silicon nitride layer is a chemical vapor deposition method. 7. The method for manufacturing a semiconductor memory according to claim 1, wherein the material of the selection gate, the floating gate and the control gate is polysilicon. 8. The method for manufacturing a semiconductor memory as claimed in claim 1, wherein the process of forming the selection gate and the floating gate is as follows: forming a polysilicon layer on the surface of the tunnel oxide layer; forming a mask layer on the surface of the polysilicon layer; Patterning the mask layer to expose part of the surface of the polysilicon layer, the shape, size and position of the patterned mask layer are the same as those of the subsequently formed selection gate and floating gate; Using the patterned mask layer as a mask, etching the polysilicon layer along the exposed area of the polysilicon layer until the surface of the semiconductor substrate is exposed, forming a selection gate and a floating gate on the same plane. 9. The method for manufacturing a semiconductor memory as claimed in claim 1, wherein the process of forming the control gate is: forming an inter-gate dielectric layer on the semiconductor substrate, the inter-gate dielectric layer covering the selection gate and the floating gate; forming a polysilicon layer on the surface of the inter-gate dielectric layer; forming a mask layer on the surface of the polysilicon layer; Patterning the mask layer to expose part of the surface of the polysilicon layer, the shape, size and position of the patterned mask layer being the same as the shape, size and position of the subsequently formed control gate; Using the patterned mask layer as a mask, sequentially etch the polysilicon layer and the intergate dielectric layer along the exposed polysilicon layer region until the surface of the floating gate is exposed, forming the floating gate located in the isolation region. Place the control gate on the gate surface. 10. The method for manufacturing a semiconductor memory according to claim 9, wherein the process for forming the polysilicon layer is a furnace tube growth method. 11. The method for manufacturing a semiconductor memory according to claim 10, wherein the process temperature for forming the polysilicon layer is 500°C-700°C. 12. The method for manufacturing a semiconductor memory according to claim 8 or 9, wherein the process of etching the polysilicon layer is a plasma dry etching process. 13. The method for manufacturing a semiconductor memory according to claim 1, wherein the ratio of the thickness of the selection gate to the thickness of the control gate is 2:1 to 1:1, and the floating gate The ratio of the thickness of the control grid to the thickness of the control grid is 2:1 to 1:1. 14 . The method for manufacturing a semiconductor memory according to claim 1 , further comprising: forming sidewall layers on sidewalls of the floating gate, the control gate and the selection gate. 15. The manufacturing method of a semiconductor memory according to claim 1, further comprising: after forming the source and drain, on the top of part of the select gate other than the control gate, part of the floating gate The top and active areas form a salicide layer. 16. A semiconductor memory formed by the method according to claims 1-15, characterized in that it comprises: a semiconductor substrate, the semiconductor substrate comprising a plurality of memory cell regions, each memory cell region including an isolation region and an active region; a tunnel oxide layer located on the active region of each memory cell region; a select gate on the surface of the tunnel oxide layer in the active region; The floating gate is located on the surface of the tunnel oxide layer in the active region and the isolation region, and the selection gate and the floating gate are spaced apart from each other; an inter-gate dielectric layer located on the surface of the floating gate in the isolation region; a control gate located on the surface of the inter-gate dielectric layer; The source and drain are located in the semiconductor substrate below the select gate and the floating gate of the active region.