CN105990119B - Manufacturing method of semiconductor device, semiconductor devices and electronic device - Google Patents

Abstract

The present invention provides a method for fabricating a semiconductor device, comprising: a: providing a semiconductor substrate, forming a dummy gate oxide layer and a dummy gate on the semiconductor substrate, and forming a dummy gate oxide layer and a dummy gate on the semiconductor substrate The dielectric layer formed on both sides of the gate, the dummy gate oxide layer and the dummy gate are removed to form a trench; b: a gate dielectric layer is formed on the bottom and sidewalls of the trench; c: toward the The trench is filled with metal material to form a metal gate, wherein the dielectric constant of the gate dielectric layer located at the bottom of the trench is higher than the dielectric constant of the gate dielectric layer located on the sidewall of the trench. The fabrication method of the semiconductor device proposed by the present invention, on the one hand, can reduce the parasitic capacitance between the source/drain and the metal gate due to the small dielectric constant of the gate dielectric layer covering the gate sidewall, on the other hand, The leakage current can still be effectively reduced due to the relatively high dielectric constant of the gate dielectric layer under the gate.

Description

Semiconductor device manufacturing method, semiconductor device and electronic device

technical field

The present invention relates to the technical field of semiconductors, and in particular, to a method for fabricating a semiconductor device, a semiconductor device and an electronic device.

Background technique

With the development of semiconductor technology, the geometric size of the metal-oxide-semiconductor field-effect transistor (MOSFET), the main device in integrated circuits, especially VLSI, has been shrinking continuously, and the critical dimension of the device has been reduced to the feature of 0.1μm Below the size, the equivalent oxide thickness of the gate dielectric has been reduced to the order of nanometers, and the process of using a silicon dioxide (SiO2) layer as the gate dielectric has reached the limit of its physical and electrical characteristics, and the silicon dioxide layer in the transistor of the 65nm process It has been shrunk to a thickness of 5 oxygen atoms. As an insulator that blocks the gate and the underlying layer, the silicon dioxide layer cannot be shrunk any further, or the resulting leakage current will make the transistor unable to function properly. To this end, a solution proposed in the prior art is to use a metal gate and a high dielectric constant (K) gate dielectric to replace the traditional heavily doped polysilicon gate and SiO2 (or SiON) gate dielectric.

There are many methods of forming metal gates and high-K dielectrics. They are mainly divided into gate first and gate last. The last gate is further divided into high K first and high K first. K (high K last). The gate-before process is characterized in that the metal gate is formed after the drain/source ion implantation of the silicon wafer and the subsequent high-temperature annealing process; the gate-last process, on the other hand, is characterized in that the drain/source is performed on the silicon wafer. The metal gate is formed before the ion implantation operation and subsequent annealing process is completed.

Currently, high-K and gate-last processes are widely used at 32/28nm and below technology nodes, however, although the use of metal gates and high-K dielectrics instead of traditional heavily doped polysilicon gates and SiO2 (or SiON) gate dielectrics can solve the leakage problem , but it was found that the high-K dielectric covering the gate spacers increases the parasitic capacitance between the source/drain and the metal gate, which in turn affects the device on/off speed and performance.

Therefore, it is necessary to propose a new manufacturing method to solve the above-mentioned problems.

SUMMARY OF THE INVENTION

A series of concepts in simplified form have been introduced in the Summary section, which are described in further detail in the Detailed Description section. The Summary of the Invention section of the present invention is not intended to attempt to limit the key features and essential technical features of the claimed technical solution, nor is it intended to attempt to determine the protection scope of the claimed technical solution.

In order to overcome the existing problems, one aspect of the present invention provides a method for fabricating a semiconductor device, comprising: a: providing a semiconductor substrate, forming a dummy gate oxide layer and a dummy gate on the semiconductor substrate, and The dummy gate oxide layer and the dielectric layer formed on both sides of the dummy gate are removed, and the dummy gate oxide layer and the dummy gate are removed to form a trench; b: a gate is formed on the bottom and sidewalls of the trench Dielectric layer; c: Fill the trench with a metal material to form a metal gate, wherein the dielectric constant of the gate dielectric layer at the bottom of the trench is higher than that of the gate dielectric at the sidewall of the trench The dielectric constant of the layer.

In the manufacturing method of the semiconductor device proposed by the present invention, since the dielectric constant of the gate dielectric layer covering the gate sidewall is relatively small, and the dielectric constant of the gate dielectric layer under the gate is relatively high, on the one hand, the dielectric constant is relatively high. Since the dielectric constant of the gate dielectric layer covering the gate spacers is small, the parasitic capacitance between the source/drain and the metal gate can be reduced. A relatively high electrical constant can still effectively reduce leakage current.

Another aspect of the present invention provides a semiconductor device, comprising: a semiconductor substrate, a dielectric layer with a trench on the semiconductor substrate, a gate dielectric layer on sidewalls and bottoms of the trench, and a dielectric layer on the trench The metal gate on the gate dielectric layer, wherein the dielectric constant of the gate dielectric layer located at the bottom of the trench is higher than the dielectric constant of the gate dielectric layer located on the sidewall of the trench.

In the semiconductor device proposed by the present invention, the dielectric constant of the gate dielectric layer covering the gate spacer is relatively small, while the dielectric constant of the gate dielectric layer under the gate is relatively high. The gate dielectric layer of the spacers has a small dielectric constant, which can reduce the parasitic capacitance between the source/drain and the metal gate. On the other hand, due to the relatively high dielectric constant of the gate dielectric layer under the gate High can still effectively reduce leakage current.

Another aspect of the present invention provides an electronic device, which includes the above-mentioned semiconductor device provided by the present invention.

The electronic device proposed by the present invention has similar advantages because it has the above-mentioned semiconductor device.

Description of drawings

The following drawings of the present invention are incorporated herein as a part of the present invention for understanding of the present invention. The accompanying drawings illustrate embodiments of the present invention and their description, which serve to explain the principles of the present invention.

In the attached picture:

1 shows a process flow diagram of a manufacturing method according to an embodiment of the present invention;

2A to 2J are schematic cross-sectional views of devices obtained by sequentially implementing the steps of a manufacturing method according to an embodiment of the present invention;

FIG. 3 shows a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;

FIG. 4 shows a schematic diagram of an electronic device according to an embodiment of the present invention.

Detailed ways

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other instances, some technical features known in the art have not been described in order to avoid obscuring the present invention.

It should be understood that the present invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. The same reference numbers refer to the same elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, or to, the other elements or layers. adjacent, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under", "below", "below", "under", "above", "above", etc., may be used herein for convenience of description This describes the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "compose" and/or "include", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or components, but do not exclude one or more other The presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

The present invention provides a method for fabricating a semiconductor device for forming a high-K gate dielectric layer and a metal gate. The specific steps include: providing a semiconductor substrate, and forming a dielectric layer with trenches on the semiconductor substrate; forming a gate dielectric layer on the bottom and sidewalls of the trench; filling the trench with a metal material to form a metal gate, and the dielectric constant of the gate dielectric layer at the bottom of the trench is higher than that at the trench bottom The dielectric constant of the gate dielectric layer on the sidewall of the trench, so that since the dielectric constant of the gate dielectric layer covering the gate sidewall spacer is relatively small, the dielectric constant of the gate dielectric layer under the gate is relatively Higher, on the one hand, due to the smaller dielectric constant of the gate dielectric layer covering the gate spacer, the parasitic capacitance between the source/drain and the metal gate can be reduced; A relatively high dielectric constant of the gate dielectric layer can still effectively reduce leakage current.

It can be understood that, in order to facilitate the formation of the metal gate, a dummy gate can be formed first before forming the metal gate, and after the dummy gate is removed, the required metal gate can be formed by filling the metal material according to the pattern of the dummy gate. pole. Therefore, the manufacturing method of the semiconductor device provided by the present invention also includes the steps of forming and removing a dummy gate, which adopts a method commonly used in the art, which is briefly described here. For example, the dummy gate is formed and removed by the following steps: providing a semiconductor substrate; forming a dummy gate oxide layer and a dummy gate on the semiconductor; forming a dielectric layer on both sides of the dummy gate oxide layer and the dummy gate; removing the dummy gate oxide and dummy gate to form groove.

Further, in the manufacturing method of the semiconductor device provided by the present invention, HfO2 is preferably used as the high-K dielectric material, and the HfO2 dielectric material has a simple CaF2 cubic crystal structure, a high dielectric constant (~25), and a large forbidden band. Width (~5.8eV), high barrier height (~1.5eV), stable chemical properties, and good lattice matching with silicon and other excellent properties, and doping an appropriate amount of Al, Si or N elements can Has better thermal stability, higher crystallization temperature, and reduced boron penetration to increase mobility.

For a thorough understanding of the present invention, detailed structures and steps will be presented in the following description, so as to explain the technical solutions proposed by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.

Example 1

The manufacturing method of the semiconductor device of the present invention will be described in detail below with reference to FIG. 1 and FIGS. 2A to 2J .

First, step S101 is performed, a semiconductor substrate is provided, a dielectric layer is formed on the semiconductor substrate, a dummy gate oxide layer and a dummy gate are formed in the dielectric layer, and the dummy gate oxide layer and the dummy gate are removed to form grooves. For example, the formation and removal of the dummy gate oxide layer and the dummy gate use methods commonly used in the art, which will not be repeated here.

As shown in FIG. 2A , a semiconductor substrate 200 is provided, which forms a dielectric layer 202 having trenches 201 . As mentioned above, this step also includes the steps of forming a dummy gate oxide layer and a dummy gate, and removing the dummy gate oxide layer and the dummy gate. To simplify the description, FIG. 2A shows that the dummy gate oxide layer and the dummy gate have been removed. Cross-sectional view of the resulting semiconductor device behind the gate.

The semiconductor substrate 200 may be at least one of the following mentioned materials: silicon, germanium. In addition, other devices, such as PMOS and NMOS transistors, may be formed on the semiconductor substrate. An isolation structure may be formed in the semiconductor substrate, and the isolation structure may be a shallow trench isolation (STI) structure or a localized silicon oxide (LOCOS) isolation structure. CMOS devices, such as transistors (eg, NMOS and/or PMOS), etc., may also be formed in the semiconductor substrate. Likewise, a conductive member may also be formed in the semiconductor substrate, and the conductive member may be a gate electrode, a source electrode or a drain electrode of a transistor, or a metal interconnection structure electrically connected to the transistor, and the like.

As an example, in this embodiment, a shallow trench isolation (STI) structure 203 is formed in the semiconductor substrate 200 , and spacers 204 are formed on the sidewalls of the trenches 201 . An etch stop layer 205 is formed therebetween. The dielectric layer 202 is, for example, silicon nitride, silicon oxide, or a combination of the two, or other commonly used materials. The spacer 204 is made of silicon nitride, silicon oxide or a combination of the two, and the etch stop layer 205 is made of silicon nitride, silicon oxide or a combination of the two.

Next, step S102 is performed to form a gate dielectric layer covering the sidewall, bottom and surface of the dielectric layer of the trench.

As shown in FIG. 2B , a gate dielectric layer 206 is formed on the sidewall, bottom and surface of the dielectric layer 202 of the trench 201 . The gate dielectric layer 206 is made of less hafnium HfSiO, and the formation method adopts physical vapor deposition, chemical vapor deposition or Atomic Layer Deposition.

Next, step S103 is performed to perform Hf ion implantation into the gate dielectric layer.

As shown in FIG. 2C , Hf ions are implanted into the gate dielectric layer 206 to increase the Hf content in the dielectric material HfSiO at the bottom of the trench 201 and the surface of the dielectric layer 202 .

As an example, in this embodiment, the implantation dose of Hf ions is 1E16˜1E17/cm ² , and the implantation energy is 1kev˜10kev.

Next, step S104 is performed to perform Hf ion implantation into the gate dielectric layer.

As shown in FIG. 2D , nitrogen ions are implanted into the gate dielectric layer 206 to increase the nitrogen content in the dielectric material HfSiO at the bottom of the trench 201 and the surface of the dielectric layer 202 , so that the gate at the bottom of the trench 201 and the surface of the dielectric layer 202 is The dielectric layer material is converted to HfSiON.

As an example, in this embodiment, the implantation dose of nitrogen ions is 1E16˜1E17/cm ² , and the implantation energy is 1kev˜10kev.

Next, step S105 is performed to form a cover layer on the bottom of the trench and the surface of the dielectric layer.

As shown in FIG. 2E , a capping layer 207 is formed on the gate dielectric layer 206 at the bottom of the trench 201 and the gate dielectric layer 206 on the surface of the dielectric layer 202 . The capping layer 207 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD).

As an example, in this embodiment, the capping layer 207 is made of TiN material, which is formed by physical vapor deposition.

Next, step S106 is performed to form an amorphous silicon layer on the sidewall of the trench and the capping layer.

As shown in FIG. 2F, an amorphous silicon layer 208 is formed on the sidewalls of the trench 201 and the capping layer. As an example, in this embodiment, the amorphous silicon layer 208 is formed by the atomic layer deposition method, and the thickness is 5 nm˜10 nm.

Next, step S107 is performed to remove the amorphous silicon layer on the bottom of the trench and the surface of the capping layer, and retain the amorphous silicon layer on the sidewall of the trench.

As shown in FIG. 2G , the amorphous silicon layer on the bottom of the trench 201 and the surface of the cover layer 207 is removed, and the amorphous silicon layer on the sidewall of the trench 201 is retained. The specific removal method can be a blank etch method. It is a common method and will not be repeated here.

Next, step S108 is performed, and an annealing process is performed to react the gate dielectric layer and the amorphous silicon layer on the sidewalls of the trenches.

As shown in FIG. 2H , an annealing process is performed to react the gate dielectric layer 206 and the amorphous silicon layer 208 on the sidewalls of the trench 201 to convert the HfSiO into SiHfSiO rich. In this embodiment, a rapid thermal annealing process may be used, specifically, rapid thermal annealing in an N ₂ environment, the annealing temperature is 400-600° C., and the time is 5s-60s.

Next, step S109 is performed to fill the trench with a metal material to form a metal gate.

As shown in FIG. 2I, the trench 201 is filled with metal material to form a metal gate.

It can be understood that when the metal material is filled into the trench 201 to form a metal gate, a metal material layer will inevitably be formed on the surface of the dielectric layer, which can be processed by chemical mechanical planarization (CMP) after the metal material is filled. The gate dielectric layer, capping layer and metal material layer above the dielectric layer 202 are removed, as shown in FIG. 2J .

Embodiment 2

The present invention also provides a semiconductor device fabricated by the method described in the first embodiment, the semiconductor substrate 200 , the dielectric layer 202 having the trench 210 on the semiconductor substrate 200 , the gate dielectric layer located on the sidewall of the trench 202 . The electrical layer 206A and the gate dielectric layer 206B at the bottom of the trench, and the metal gate 210 on the gate dielectric layer 206B at the bottom of the trench, wherein the dielectric of the gate dielectric layer 206B The constant is higher than the dielectric constant of the gate dielectric layer 206A.

In this embodiment, the gate dielectric layer 206A is HfSiO, and the gate dielectric layer 206B is HfSiON.

In this embodiment, a spacer 204 is formed between the gate dielectric layer 206A and the dielectric layer 202 on the sidewall of the trench 201 .

In this embodiment, a capping layer 207 is formed between the metal gate 210 and the gate dielectric layer 206B, and the capping layer 207 is a TiN layer formed by physical vapor deposition.

Embodiment 3

The present invention further provides an electronic device including the aforementioned semiconductor device.

Since the included semiconductor device is packaged at the wafer level, it has the advantages brought by the process, and because the packaging method is used, the yield is high and the cost is relatively reduced, so the electronic device also has the above advantages.

The electronic device can be any electronic product or device such as a mobile phone, tablet computer, notebook computer, netbook, game console, TV, VCD, DVD, navigator, camera, video camera, voice recorder, MP3, MP4, PSP, etc. It is an intermediate product with the above semiconductor devices, such as a mobile phone motherboard with the integrated circuit. In this implementation, a PDA is taken as an example for an example, as shown in Figure 4 .

The present invention has been described by the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can also be made according to the teachings of the present invention, and these variations and modifications all fall within the protection claimed in the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalents.

Claims (8)

1. a kind of production method of semiconductor devices, which is characterized in that include the following steps:

A: providing semiconductor substrate, forms dummy gate oxide layer and dummy gate on the semiconductor substrate, and in institute State the dielectric layer that dummy gate oxide layer and dummy gate two sides are formed, remove the dummy gate oxide layer and dummy gate with Form groove；

B: gate dielectric is formed on the channel bottom and side wall；

C: Xiang Suoshu trench fill metal material forms metal gates,

Wherein, the gate dielectric positioned at the trenched side-wall is higher than positioned at the dielectric constant of the gate dielectric of channel bottom Dielectric constant,

Wherein, forming the gate dielectric includes:

The gate dielectric for covering the trenched side-wall, bottom and the dielectric layer surface is formed, the gate dielectric is Few hafnium HfSiO；

Hf ion implanting is executed to the gate dielectric；

N~+ implantation is executed to the gate dielectric, makes the gate dielectric of the channel bottom and the dielectric layer surface It is changed into HfSiON；

Coating is formed in the channel bottom and dielectric layer surface；

The amorphous silicon layer formed on the trenched side-wall and the coating；

The amorphous silicon for removing the channel bottom and the cover surface retains the amorphous silicon layer on the trenched side-wall；

Execute annealing process, on the trenched side-wall gate dielectric and amorphous silicon layer reaction, make on the trenched side-wall Gate dielectric be changed into Silicon-rich HfSiO.

2. manufacturing method according to claim 1, which is characterized in that the implantation dosage of the Hf ion be 1E16~ 1E17/cm², Implantation Energy is 1kev~10kev.

3. manufacturing method according to claim 1, which is characterized in that the implantation dosage of the Nitrogen ion be 1E16~ 1E17/cm², Implantation Energy is 1kev~10kev.

4. manufacturing method according to claim 1, which is characterized in that the coating is to be formed by physical vapour deposition (PVD) TiN layer.

5. manufacturing method according to claim 1, which is characterized in that the amorphous silicon layer is formed for atomic layer deposition.

6. manufacturing method according to claim 1, which is characterized in that the amorphous silicon layer is with a thickness of 5nm~10nm.

7. manufacturing method according to claim 1, which is characterized in that be formed with clearance wall on the trenched side-wall.

8. manufacturing method according to claim 1, which is characterized in that be also formed with etch stop below the dielectric layer Layer.