CN104813390A - Method and system for driving an active matrix display circuit - Google Patents

Abstract

This invention provides a system and method for driving an active matrix display. The system includes driving circuitry for pixels having light-emitting devices. The driving circuitry includes driving transistors for driving the light-emitting devices. The system includes a mechanism for adjusting the gate voltage of the driving transistors.

Description

Systems and methods for driving active matrix display circuits

technical field

The present invention relates to light emitting devices, and more particularly, to systems and methods for driving pixel circuits with light emitting devices.

Background technique

Electroluminescent displays have been developed and widely used in various devices such as mobile phones. In particular, active-matrix organic light-emitting diode (AMOLED) displays with amorphous silicon (a-Si), polysilicon, organic or other driven backplanes have been widely used due to their feasible flexible display, low manufacturing cost, high resolution and wide viewing angle, etc. and other advantages become more attractive.

An AMOLED display includes an array of rows and columns of pixels, each pixel having an organic light emitting diode (OLED), and backplane electronics arranged in the array of rows and columns. Because OLED is a current-driven device, the pixel circuit of AMOLED should be able to provide accurate and constant driving current.

There is a need to provide systems and methods that can provide constant brightness with high precision and that can reduce aging effects of pixel circuits and instability of backplanes and light emitting devices.

Contents of the invention

It is an object of the present invention to provide methods and systems that eliminate or mitigate at least one of the above-mentioned disadvantages of existing systems.

According to one aspect of the present invention, a system is proposed, a display system comprising a driving circuit for a pixel having a light emitting device. The driving circuit includes a driving transistor connected to the light emitting device. The driving transistor includes a gate terminal, a first terminal and a second terminal. The driving circuit includes a first transistor having a gate terminal, a first terminal and a second terminal, the gate terminal of the first transistor is connected to a selection line, the first terminal of the first transistor is connected to a data line and the second terminal is connected to the gate terminal of the drive transistor. The drive circuit includes circuitry for regulating the gate voltage of the drive transistor, the circuitry for regulating including a discharge transistor having a gate terminal, a first terminal and a second terminal, the gate terminal of the discharge transistor being at node Connected to the gate terminal of the drive transistor, the voltage at the node is discharged through the discharge transistor. The drive circuit includes a storage capacitor having a first terminal and a second terminal, the first terminal of the storage capacitor being connected to the gate terminal of the drive transistor at the node.

The display system may include a display array and a driver for driving the display array. The display array has a plurality of pixel circuits arranged in rows and columns, and each pixel circuit includes a driving circuit. The gate terminal of the second transistor is connected to the bias line. The bias line may be shared by more than one pixel circuit among the plurality of pixel circuits.

According to yet another aspect of the present invention, a method for a display system is proposed. The display system includes a driver that provides a programming cycle, a compensation cycle, and a driving cycle for each row. The method includes the following steps: during the programming period of the first row, selecting the address line of the first row and providing the programming data to the first row; during the compensation period of the first row, selecting the The adjacent address lines of the second row and the address lines of the first row are disabled; and during the drive cycle of the first row, the adjacent address lines are disabled.

According to still another aspect of the present invention, a display system is provided, which includes one or more pixel circuits, each pixel circuit includes a light emitting device and a driving circuit. The drive circuit includes a drive transistor having a gate terminal, a first terminal and a second terminal, the drive transistor being located between the light emitting device and a first power source. The drive circuit includes a switching transistor having a gate terminal, a first terminal and a second terminal, the gate terminal of the switching transistor is connected to a first address line, the first terminal of the switching transistor is connected to a data line and the second terminal of the switching transistor is connected to a data line. terminal is connected to the gate terminal of the drive transistor. The drive circuit includes circuitry for regulating the gate voltage of the drive transistor, the circuitry for regulating including a sensor for sensing energy transfer from the pixel circuit and a discharge transistor, the sensor having A first terminal and a second terminal, the characteristic of the sensor changes according to a sensing result, the discharge transistor has a gate terminal, a first terminal and a second terminal, the gate terminal of the discharge transistor is connected to a second address line, the first terminal of the discharge transistor is connected at a node to the gate terminal of the drive transistor and the second terminal of the discharge transistor is connected to the first terminal of the sensor. The drive circuit includes a storage capacitor having a first terminal and a second terminal, the first terminal of the storage capacitor being connected to the gate terminal of the drive transistor at the node.

According to yet another aspect of the invention, a method for a display system is proposed, said method comprising the step of implementing intra-pixel compensation.

According to yet another aspect of the invention, a method for a display system is proposed, said method comprising the step of implementing in-panel compensation.

According to yet another aspect of the invention, a method for a display system comprising a pixel circuit with a sensor is presented, the method comprising the step of reading back the aging of the sensor.

According to still another aspect of the present invention, a display system is proposed, which includes: a display array, the display array includes a plurality of pixel circuits arranged in rows and columns, each pixel circuit includes a light emitting device and a driving circuit; and A drive system for driving a display array. The drive circuit includes a drive transistor having a gate terminal, a first terminal and a second terminal, the drive transistor being located between the light emitting device and a first power source. The drive circuit includes a first transistor having a gate terminal, a first terminal and a second terminal, the gate terminal of the first transistor is connected to an address line, the first terminal of the first transistor is connected to a data line and The second terminal of the first transistor is connected to the gate terminal of the drive transistor. The drive circuit includes a circuit for regulating the voltage of the drive transistor, the circuit for regulating includes a second transistor having a gate terminal, a first terminal and a second terminal, the The gate terminal of the second transistor is connected to the control line, and the first terminal of the second transistor is connected to the gate terminal of the driving transistor. The drive circuit includes a storage capacitor having a first terminal and a second terminal, the first terminal of the storage capacitor being connected to the gate terminal of the drive transistor. The driving system drives the pixel circuit such that the pixel circuit is turned off for a portion of a frame time.

According to yet another aspect of the present invention, a method for a display system having a display array and a driving system is presented. The drive system provides a frame time for each row with a programming period, a discharging period, a light emitting period, a reset period and a relaxation period. The method comprises the steps of: programming the pixel circuits of a row by activating an address line for the row during a programming period; The voltage on the gate terminal of the LED is partially discharged; during the light emitting period, the control line for the row is deactivated, and the light emitting device is controlled through the drive transistor; during the reset period, the drive is activated by the control line for the row The voltage on the gate terminal of the transistor is discharged; and during the relaxation period, the control line for the row is deactivated.

Description of drawings

These and other features of the present invention will become more apparent from the following description with reference to the accompanying drawings.

FIG. 1 illustrates an example of a pixel circuit to which a pixel driving scheme according to an embodiment of the present invention is applied.

FIG. 2 illustrates another example of a pixel circuit having the driving circuit of FIG. 1 .

FIG. 3 is a timing chart of an example of a driving method of a pixel circuit according to an embodiment of the present invention.

FIG. 4 illustrates an example of a display system of the driving circuit of FIGS. 1 and 2 .

FIG. 5 illustrates an example of a pixel circuit to which a pixel driving scheme according to another embodiment of the present invention is applied.

FIG. 6 illustrates another example of the driving circuit of FIG. 5 .

FIG. 7 illustrates still another example of the driving circuit of FIG. 5 .

FIG. 8 illustrates another example of a pixel circuit having the driving circuit of FIG. 5 .

FIG. 9 is a timing diagram of an example of a driving method of a pixel circuit according to another embodiment of the present invention.

FIG. 10 illustrates an example of a display system for the driving circuits of FIGS. 5 and 8 .

FIG. 11 illustrates an example of a display system for the driving circuits of FIGS. 6 and 7 .

FIG. 12 is a graph illustrating simulation results of the pixel circuit of FIG. 1 .

FIG. 13 illustrates an example of a pixel circuit to which a pixel driving scheme according to yet another embodiment of the present invention is applied.

FIG. 14 illustrates another example of a pixel circuit having the driving circuit of FIG. 13 .

FIG. 15 is a timing diagram of an example of a driving method of a pixel circuit according to still another embodiment of the present invention.

FIG. 16 illustrates an example of a display system for the driving circuits of FIGS. 13 and 14 .

FIG. 17 is a graph illustrating simulation results of the pixel circuit of FIG. 5 .

FIG. 18 is a graph illustrating simulation results of the pixel circuit of FIG. 5 .

FIG. 19 is a timing diagram of the operation of the display system of FIG. 16 .

FIG. 20 illustrates an example of a pixel circuit to which a pixel driving scheme according to yet another embodiment of the present invention is applied.

FIG. 21 illustrates another example of a pixel circuit having the driving circuit of FIG. 20 .

FIG. 22 is a timing chart illustrating an example of a driving method of a pixel circuit according to still another embodiment of the present invention.

FIG. 23 illustrates an example of a display system for the driving circuits of FIGS. 20 and 21 .

FIG. 24 illustrates another example of a display system for the driving circuits of FIGS. 20 and 21 .

Figure 25 illustrates an example of a pixel system according to an embodiment of the present invention.

FIG. 26 illustrates an example of a display system with the readback circuit of FIG. 25 .

FIG. 27 illustrates another example of a display system with the readback circuit of FIG. 25 .

FIG. 28 is a timing chart illustrating an example of a driving method of a pixel circuit according to still another embodiment of the present invention.

FIG. 29 illustrates an example of an extraction method of aging of the sensor of FIG. 25 .

FIG. 30 illustrates an example of a pixel system according to another embodiment of the present invention.

FIG. 31 illustrates an example of a display system having the readback circuit of FIG. 30 .

FIG. 32 illustrates another example of a display system with the readback circuit of FIG. 30 .

FIG. 33 is a timing chart illustrating an example of a driving method of a pixel circuit according to still another embodiment of the present invention.

FIG. 34 is a sequence diagram illustrating another example of an extraction method of aging of the sensor of FIG. 30 .

FIG. 35 is a diagram illustrating an example of a pixel circuit to which a pixel driving scheme according to still another embodiment of the present invention is applied.

FIG. 36 is a timing chart of an example of a driving method of a pixel circuit according to still another embodiment of the present invention.

FIG. 37 illustrates an example of a display system having the pixel circuit of FIG. 35 .

FIG. 38 illustrates another example of a display system having the pixel circuit of FIG. 35 .

FIG. 39 illustrates an example of a pixel circuit to which a pixel driving scheme according to another embodiment of the present invention is applied.

FIG. 40 illustrates an example of a pixel circuit to which a pixel driving scheme according to yet another embodiment of the present invention is applied.

FIG. 41 illustrates an example of a pixel circuit to which a pixel driving scheme according to another embodiment of the present invention is applied.

Detailed ways

FIG. 1 illustrates an example of a pixel circuit to which a pixel driving scheme according to an embodiment of the present invention is applied. The pixel circuit 100 of FIG. 1 includes an OLED 102 and a driving circuit 104 for driving the OLED 102. The drive circuit 104 includes a drive transistor 106 , a discharge transistor 108 , a switch transistor 110 and a storage capacitor 112 . OLED 102 includes, for example, an anode, a cathode, and a light emitting layer between the anode and the cathode.

In the following description, "pixel circuit" and "pixel" are used interchangeably. In the following description, "signal" and "line" may be used interchangeably. In the following description, the terms "line" and "node" may be used interchangeably. In the description, the terms "select line" and "address line" may be used interchangeably. In the following descriptions, "connect (or be connected)" and "join (or be engaged)" may be used interchangeably, and they may be used to indicate that two or more elements are in direct or indirect physical contact or electrical contact with each other. touch.

In one example, transistors 106, 108, and 110 are n-type transistors. In another example, transistors 106, 108, and 110 are p-type transistors, or a combination of n-type and p-type transistors. In one example, transistors 106, 108, and 110 each include a gate terminal, a source terminal, and a drain terminal.

Transistors 106, 108, and 110 may be fabricated using amorphous silicon, nano/microcrystalline silicon, polysilicon, organic semiconductor technology (eg, organic TFT), NMOS/PMOS technology, or CMOS technology (eg, MOSFET).

The drive transistor 106 is provided between the voltage supply line VDD and the OLED 102. One terminal of the drive transistor 106 is connected to VDD. The other terminal of the drive transistor 106 is connected to one electrode of the OLED 102 (eg, the anode electrode). One terminal of the discharge transistor 108 and the gate terminal of the discharge transistor 108 are connected to the gate terminal of the drive transistor 106 at node A1 . The other terminal of discharge transistor 108 is connected to OLED 102. The gate terminal of the switching transistor 110 is connected to a selection line SEL. One terminal of the switching transistor 110 is connected to the data line VDATA. The other terminal of the switching transistor 110 is connected to the node A1. One terminal of the storage capacitor 112 is connected to the node A1. The other terminal of the storage capacitor 112 is connected to the OLED 102. The other electrode (eg, cathode electrode) of OLED 102 is connected to power line (eg, common ground) 114 .

As described below, the pixel circuit 100 provides a constant average current over a frame time by adjusting the gate voltage of the drive transistor 106 .

FIG. 2 illustrates another example of a pixel circuit having the driving circuit 104 of FIG. 1 . The pixel circuit 130 is similar to the pixel circuit 100 of FIG. 1 . Pixel circuit 130 includes OLED 132. OLED 132 may be the same as or similar to OLED 102 of FIG. 1 . In the pixel circuit 130, the drive transistor 106 is disposed between one electrode (eg, cathode electrode) of the OLED 132 and a power supply line (eg, common ground) 134. One terminal of the discharge transistor 138 and one terminal of the storage capacitor 112 are connected to the power supply line 134 . The other electrode (eg, the anode electrode) of OLED 132 is connected to VDD.

In a similar manner to pixel circuit 100 of FIG. 1 , pixel circuit 130 provides a constant average current over a frame time.

FIG. 3 illustrates an example of a driving method of a pixel circuit according to an embodiment of the present invention. The waveforms of FIG. 3 are applied to a pixel circuit (eg, 100 of FIG. 1 , 130 of FIG. 2 ) having the driving circuit 104 of FIGS. 1 and 2 .

The operation cycle of FIG. 3 includes a programming cycle 140 and a driving cycle 142 . Referring to FIGS. 1 to 3 , during the programming period 140 , when the selection line SEL is at a high level, the node A1 is charged to a programming voltage through the switching transistor 110 . During drive cycle 142 , node A1 is discharged through discharge transistor 108 . Because the drive transistor 106 and the discharge transistor 108 have the same bias conditions, they experience the same threshold voltage shift. Considering that the discharge time is a function of the transconductance of the discharge transistor 108, the discharge time increases as the threshold voltage of the drive transistor 106/discharge transistor 108 increases. Therefore, the average current of the pixel (100 in FIG. 1, 130 in FIG. 2) remains constant during the frame time. In an example, the discharge transistor is a very weak transistor with a short width (W) and a long channel length (L). The ratio of width (W) to length (L) can vary from case to case.

Furthermore, in the pixel circuit 130 of FIG. 2, an increase in the OLED voltage of the OLED 132 results in a longer discharge time. Therefore, the average pixel current will remain constant even after the OLED is degraded.

FIG. 4 illustrates an example of a display system for the driving circuits of FIGS. 1 and 2 . Display system 1000 of FIG. 4 includes a display array 1002 having a plurality of pixels 1004 . The pixel 1004 includes the driving circuit 104 of FIG. 1 and FIG. 2 , and may be the pixel circuit 100 of FIG. 1 or the pixel circuit 130 of FIG. 2 .

Display array 1002 is an active matrix light emitting display. In one example, display array 1002 is an AMOLED display array. Display array 1002 can be a monochrome, multicolor, or full-color display, and can include one or more electroluminescent (EL) elements (eg, organic EL). Display array 1002 may be used in a mobile device, personal digital assistant (PDA), computer monitor, or cell phone.

The display array 1002 is provided with selection lines SELi, SELi+1 and data lines VDATAj, VDATAj+1. The respective selection lines SELi, SELi+1 correspond to SEL in FIGS. 1 and 2 . Each data line VDATAj, VDATAj+1 corresponds to VDATA in FIG. 1 and FIG. 2 . Pixels 1004 are arranged in rows and columns. Pixels in the same row in the display array 1002 share the selection line (SELi, SELi+1). Pixels in the same column in the display array 1002 share data lines (VDATAj, VDATAj+1).

In FIG. 4, four pixels 1004 are shown. However, the number of pixels 1004 may vary according to system design and is not limited to four. In FIG. 4, two select lines and two data lines are shown. However, the number of selection lines and data lines can vary according to system design and is not limited to two.

Gate driver 1006 drives SELi and SELi-1-1. The gate driver 1006 may be an address driver for supplying address signals to address lines (eg, select lines). Data driver 1008 generates programming data and drives VDATAj and DATAj+1. Controller 1010 controls drivers 1006 and 1008 so that they drive pixel 1004 as described above.

FIG. 5 illustrates an example of a pixel circuit to which a pixel driving scheme according to another embodiment of the present invention is applied. The pixel circuit 160 of FIG. 5 includes an OLED 162 and a driving circuit 164 for driving the OLED 162. The drive circuit 164 includes a drive transistor 166 , a discharge transistor 168 , a first switching transistor 170 and a second switching transistor 172 , and a storage capacitor 174 .

The pixel circuit 160 is similar to the pixel circuit 130 of FIG. 2 . The driver circuit 164 is similar to the driver circuit 104 of FIGS. 1 and 2 . Transistors 166, 168, and 170 correspond to transistors 106, 108, and 110 of FIGS. 1 and 2, respectively. Transistors 166 , 168 and 170 may be the same as or similar to transistors 106 , 108 and 110 of FIGS. 1 and 2 . The storage capacitor 174 corresponds to the storage capacitor 112 of FIGS. 1 and 2 . Storage capacitor 174 may be the same as or similar to storage capacitor 112 of FIGS. 1 and 2 . OLED 162 corresponds to OLED 132 of FIG. 2 . OLED 162 may be the same as or similar to OLED 132 of FIG. 2 .

In one example, switch transistor 172 is an n-type transistor. In another example, switch transistor 172 is a p-type transistor. In one example, transistors 166, 168, 170, and 172 each include a gate terminal, a source terminal, and a drain terminal.

Transistors 166, 168, 170, and 172 may be fabricated using amorphous silicon, nano/microcrystalline silicon, polysilicon, organic semiconductor technology (eg, organic TFT), NMOS/PMOS technology, or CMOS technology (eg, MOSFET).

In the pixel circuit 160 , a switch transistor 172 and a discharge transistor 168 are connected in series between the gate terminal of the drive transistor 166 and a power supply line (eg, common ground) 176 . The gate terminal of the switching transistor 172 is connected to the bias voltage line VB. The gate terminal of the discharge transistor 168 is connected to the gate terminal of the drive transistor at node AZ. The drive transistor 166 is disposed between one electrode (eg, a cathode electrode) of the OLED 162 and the power line 176. The gate terminal of the switching transistor 170 is connected to SEL. One terminal of the switching transistor 170 is connected to VDATA. The other terminal of the switching transistor 170 is connected to node A2. One terminal of the storage capacitor 174 is connected to node A2. The other terminal of the storage capacitor 174 is connected to a power line 176 .

As described below, pixel circuit 160 provides a constant average current over the frame time by adjusting the gate voltage of drive transistor 166 .

In one example, the bias voltage line VB of FIG. 5 may be shared by pixels of the entire panel. In another example, as shown in FIG. 6, the bias voltage line VB may be connected to node A2. Pixel circuit 160A of FIG. 6 includes a driver circuit 164A. The driving circuit 164A is similar to the driving circuit 164 of FIG. 5 . However, in the drive circuit 164A, the gate terminal of the switching transistor 172 is connected to the node A2. In yet another example, as shown in FIG. 7 , the switching transistor 172 of FIG. 5 can be replaced with a resistor. The pixel circuit 160B of FIG. 7 includes a driver circuit 164B. The driving circuit 164B is similar to the driving circuit 164 of FIG. 5 . However, in the drive circuit 164B, the resistor 178 and the discharge transistor 168 are connected in series between the node A2 and the power supply line 176 .

FIG. 8 illustrates another example of a pixel circuit having the driving circuit 164 of FIG. 5 . The pixel circuit 190 is similar to the pixel circuit 160 of FIG. 5 . Pixel circuit 190 includes OLED 192. OLED 192 may be the same as or similar to OLED 162 of FIG. 5 . In the pixel circuit 190, the drive transistor 166 is disposed between one electrode (eg, an anode electrode) of the OLED 192 and VDD. One terminal of the discharge transistor 168 and one terminal of the storage capacitor 174 are connected to the OLED 192. The other electrode (eg, cathode electrode) of OLED 192 is connected to power line (eg, common ground) 194 .

In one example, the pixels of the entire panel share the bias voltage line VB of FIG. 8 . In another example, the bias voltage line VB of FIG. 8 is connected to node A2 as similar to FIG. 6 . In yet another example, the switching transistor 172 of FIG. 8 is replaced by a resistor, similar to FIG. 7 .

In a similar manner to pixel circuit 160 of FIG. 5, pixel circuit 190 provides a constant average current over a frame time.

FIG. 9 illustrates an example of a driving method of a pixel circuit according to another embodiment of the present invention. The waveform of FIG. 9 is applied to the pixel circuit (eg, 160 of FIG. 5 , 190 of FIG. 8 ) having the driving circuit 164 of FIGS. 5 and 8 .

The operating cycle of FIG. 9 includes a programming cycle 200 and a driving cycle 202 . Referring to FIG. 5 , FIG. 8 and FIG. 9 , during the programming cycle 200 , when SEL is high, the node A2 is charged to the programming voltage (Vp) through the switching transistor 170 . During drive cycle 202 , node A2 is discharged through discharge transistor 168 . Because drive transistor 166 and discharge transistor 168 have the same bias conditions, they experience the same threshold voltage shift. Considering that the discharge time is a function of the transconductance of the discharge transistor 168, the discharge time increases as the threshold voltage of the drive transistor 166/discharge transistor 168 increases. Therefore, the average current of the pixel (160 in FIG. 5, 190 in FIG. 8) remains constant during the frame time. Here, switching transistor 172 forces discharge transistor 168 into a linear region of operation and thereby reduces the feedback gain. Therefore, the discharge transistor 168 may be a unity transistor with a minimum channel length and width. The width and length of a unit transistor are the minimum allowed by the technology.

Furthermore, in the pixel circuit 190 of FIG. 8, an increase in the OLED voltage of the OLED 192 results in a longer discharge time. Therefore, the average pixel current will remain constant even after the OLED is degraded.

FIG. 10 illustrates an example of a display system for the driving circuits of FIGS. 5 and 8 . Display system 1020 of FIG. 10 includes a display array 1022 having a plurality of pixels 1024 . The pixel 1024 includes the driving circuit 164 of FIGS. 5 and 8 , and may be the pixel circuit 130 of FIG. 5 or the pixel circuit 190 of FIG. 8 .

Display array 1022 is an active matrix light emitting display. In one example, display array 1022 is an AMOLED display array. Display array 1022 may be a monochrome, multicolor, or full-color display, and may include one or more EL elements (eg, organic EL). Display array 1022 can be used in mobile devices, PDAs, computer monitors or cell phones.

The respective selection lines SELi and SELi+1 correspond to SEL of FIGS. 5 and 8 . VB corresponds to VB in FIGS. 5 and 8 . The respective data lines VDATAj and VDATAj+1 correspond to VDATA of FIGS. 5 and 8 . The pixels 1024 are arranged in rows and columns. The pixels in a row in the display array 1022 share a selection line (SELi, SEL1+1). Pixels in the same column in the display array 1022 share data lines (VDATAj, VDATAj+1). The i-th row and the (i+1)th row of pixels share the bias voltage line VB. In another example, VB can be shared by the entire array 1022 .

In FIG. 10, four pixels 1024 are shown. However, the number of pixels 1024 may vary according to system design and is not limited to four. In FIG. 10, two select lines and two data lines are shown. However, the number of selection lines and data lines can vary according to system design and is not limited to two.

Gate driver 1026 drives SELi and SELi+1 and VB. The gate driver 1026 may include an address driver for providing address signals to the display array 1022 . The data driver 1028 generates programming data and drives VDATAj and VDATAj+1. Controller 1030 controls drivers 1026 and 1028 so that they drive pixel 1024 as described above.

FIG. 11 illustrates an example of a display system for the driving circuits of FIGS. 6 and 7 . Display system 1040 of FIG. 11 includes a display array 1042 having a plurality of pixels 1044 . The pixel 1044 includes the driving circuit 164A of FIG. 6 or the driving circuit 164B of FIG. 7 , and may be the pixel circuit 160A of FIG. 6 or the pixel circuit 160B of FIG. 7 .

Display array 1042 is an active matrix light emitting display. In one example, display array 1042 is an AMOLED display array. Display array 1042 may be a monochrome, multicolor, or full-color display, and may include one or more EL elements (eg, organic EL). Display array 1042 can be used in mobile devices, PDAs, computer monitors or cell phones.

The respective selection lines SELi and SELi+1 correspond to SEL of FIGS. 6 and 7 . The respective data lines VDATAj and VX)ATAj+1 correspond to VDATA of FIGS. 6 and 7 . The pixels 1044 are arranged in rows and columns. Pixels in the same row in the display array 1042 share the select line (SELL, SELi+1). Pixels in the same column in the display array 1042 share data lines (VDATAj, VDATAj+1).

In FIG. 11, four pixels 1044 are shown. However, the number of pixels 1044 may vary according to system design and is not limited to four. In FIG. 11, two select lines and two data lines are shown. However, the number of selection lines and data lines can vary according to system design and is not limited to two.

Gate driver 1046 drives SELi and SELi±1. The gate driver 1046 may be an address driver for supplying address signals to address lines (eg, selection lines). The data driver 1048 generates programming data and drives VDATAj and VDATAj+1. Controller 1040 controls drivers 1046 and 1048 so that they drive pixel 1044 as described above.

FIG. 12 illustrates simulation results of the pixel circuit 100 of FIG. 1 . In FIG. 12, "g1" represents the current of the pixel circuit 100 shown in FIG. 1 for different drifts of the threshold voltage of the driving transistor 106 and the initial current is 500nA; "g2" represents the threshold voltage of the driving transistor 106 The current of the pixel circuit 100 in the case of different drifts and the initial current is 150nA. In FIG. 12, "g3" represents the current of the conventional 2-TFT pixel circuit for different shifts of the threshold voltage of the driving transistor and the initial current is 500nA; "g4" represents the different shifts of the threshold voltage of the driving transistor and The current of the traditional 2-TFT pixel circuit when the initial current is 150nA. Clearly, the average pixel current is stable for the new driving scheme, whereas it drops significantly if the discharge transistor (eg, 106 of FIG. 1 ) is removed from the pixel circuit (conventional 2-TFT pixel circuit).

FIG. 13 illustrates an example of a pixel circuit to which a pixel driving scheme according to yet another embodiment of the present invention is applied. The pixel circuit 210 of FIG. 13 includes an OLED 212 and a driving circuit 214 for driving the OLED 212. The drive circuit 214 includes a drive transistor 216 , a discharge transistor 218 , a first switch transistor 220 and a second switch transistor 222 , and a storage capacitor 224 .

The pixel circuit 210 is similar to the pixel circuit 190 of FIG. 8 . The driver circuit 214 is similar to the driver circuit 164 of FIGS. 5 and 8 . Transistors 216, 218, and 220 correspond to transistors 166, 168, and 170 of FIGS. 5 and 8, respectively. Transistors 216 , 218 and 220 may be the same as or similar to transistors 166 , 168 and 170 of FIGS. 5 and 8 . Transistor 222 may be the same as or similar to transistor 172 of FIG. 5 or transistor 178 of FIG. 8 . In one example, transistors 216, 218, 220, and 222 each include a gate terminal, a source terminal, and a drain terminal. The storage capacitor 224 corresponds to the storage capacitor 174 of FIGS. 5 to 8 . Storage capacitor 224 may be the same as or similar to storage capacitor 174 of FIGS. 5-8 . OLED 212 corresponds to OLED 192 of FIG. 8 . OLED 212 may be the same as or similar to OLED 192 of FIG. 8 .

Transistors 216, 218, 220, and 222 may be fabricated using amorphous silicon, nano/microcrystalline silicon, polysilicon, organic semiconductor technology (eg, organic TF1), NMOS/PMOS technology, or CMOS technology (eg, MOSFET).

In the pixel circuit 210, a drive transistor 216 is disposed between VDD and one electrode (eg, an anode electrode) of the OLED 212. Switching transistor 222 and discharge transistor 218 are connected in series between the gate terminal of drive transistor 216 and OLED 212. One terminal of the switching transistor 222 is connected to the gate terminal of the drive transistor at node A3. The gate terminal of discharge transistor 218 is connected to node M. Storage capacitor 224 is disposed between node A3 and OLED 212. Switching transistor 220 is disposed between VDATA and node A3. The gate terminal of the switching transistor 220 is connected to a select line SEL[n]. The gate terminal of the switching transistor 222 is connected to the selection line SEL[n+1]. The other electrode (eg, cathode electrode) of OLED 212 is connected to power line (eg, common ground) 226 . In one example, SEL[n] is the nth row address line in the display array, and SEL[n+1] is the (n+1)th row address line in the display array.

As described below, pixel circuit 210 provides a constant average current over a frame time by adjusting the gate voltage of drive transistor 216 .

FIG. 14 illustrates another example of a pixel circuit having the driving circuit 214 of FIG. 13 . The pixel circuit 240 of FIG. 14 is similar to the pixel circuit 160 of FIG. 5 . Pixel circuit 240 includes OLED 242. OLED 242 may be the same as or similar to OLED 162 of FIG. 5 . In the pixel circuit 240, the drive transistor 216 is disposed between one electrode (eg, a cathode electrode) of the OLED 242 and a power supply line (eg, a common ground) 246. One terminal of the discharge transistor 218 and one terminal of the storage capacitor 224 are connected to a power supply line 246 . The other electrode (eg, the anode electrode) of OLED 242 is connected to VDD. The gate terminal of the switching transistor 220 is connected to a select line SEL[n]. The gate terminal of the switching transistor 222 is connected to the selection line SEL[n+1].

In a similar manner to pixel circuit 210 of FIG. 13, pixel circuit 240 provides a constant average current over a frame time.

FIG. 15 illustrates an example of a driving method of a pixel circuit according to an embodiment of the present invention. The waveform of FIG. 15 is applied to the pixel circuit (eg, 210 of FIG. 13 , 240 of FIG. 14 ) having the driving circuit 214 of FIGS. 13 and 14 .

The operating cycle of FIG. 15 includes three operating cycles 250 , 252 and 254 . Operation period 250 forms a programming period, operation period 252 forms a compensation period and operation period 254 forms a drive period. Referring to FIGS. 13 to 15 , during the programming period 250 , when SEL[n] is at a high level, the node A3 is charged to a programming voltage through the switching transistor 220 . During the second operation cycle 252, SEL[n+1] goes to a high voltage. SEL[n] is disabled (or invalid). Node A3 is discharged through discharge transistor 218 . During the third operating cycle 254, SEL[n] and SEL[n+1] are disabled. Because drive transistor 216 and discharge transistor 218 have the same bias conditions, they experience the same threshold voltage shift. Considering that the discharge time is a function of the transconductance of the discharge transistor 218, when the threshold voltage of the drive transistor 216/discharge transistor 218 increases, the discharge voltage decreases. Accordingly, the gate voltage of drive transistor 216 is adjusted accordingly.

Furthermore, in pixel 240 of FIG. 14, an increase in the OLED voltage of OLED 242 results in a higher gate voltage. Therefore, the pixel current remains constant.

FIG. 16 illustrates an example of a display system for the driving circuits of FIGS. 13 and 14 . Display system 1060 of FIG. 16 includes a display array 1062 having a plurality of pixels 1064 . The pixel 1064 includes the driving circuit 214 of FIGS. 13 and 14 , and may be the pixel circuit 210 of FIG. 13 or the pixel circuit 240 of FIG. 14 .

Display array 1062 is an active matrix light emitting display. In one example, display array 1062 is an AMOLED display array. Display array 1062 may be a monochrome, multicolor, or full-color display, and may include one or more EL elements (eg, organic EL). Display array 1062 can be used in mobile devices, PDAs, computer monitors or cell phones.

SEL[k] (k=n+1, n+2) is an address line for the kth row. VDATA1(l=j, j+1) is a data line and corresponds to VDATA of FIGS. 13 and 14 . The pixels 1064 are arranged in rows and columns. In the display array 1062, the pixels in the same row share the selection line SEL[k]. In the display array 1062, the pixels in the same column share the data line VDATA1.

In FIG. 16, four pixels 1064 are shown. However, the number of pixels 1064 may vary according to system design and is not limited to four. In FIG. 16, three address lines and two data lines are shown. However, the number of address lines and data lines may vary according to system design.

Gate driver 1066 drives SEL[k]. The gate driver 1066 may be an address driver for supplying address signals to address lines (eg, selection lines). Data driver 1068 generates programming data and drives VDATA1. Controller 1070 controls drivers 1066 and 1068 so that they drive pixel 1064 as described above.

FIG. 17 illustrates simulation results of the pixel circuit 160 of FIG. 5 . In FIG. 17, "g5" represents the current of the pixel circuit 160 shown in FIG. 5 for different drifts of the threshold voltage of the driving transistor 166 and the initial current is 630 nA; "g6" represents the threshold voltage for the driving transistor 166 The current of the pixel circuit 160 in the case of different drifts and the initial current is 430nA. It can be seen that even after the threshold voltage of the driving transistor drifts by 2V, the pixel current is still very stable. Since the pixel circuit 210 of FIG. 13 is similar to the pixel circuit 160 of FIG. 15 , it is obvious to those skilled in the art that the pixel current of the pixel circuit 210 will also be stable.

FIG. 18 illustrates simulation results of the pixel circuit 160 of FIG. 5 . In FIG. 18, "g7" represents the current of the pixel circuit 160 shown in FIG. 5 for different OLED voltages of the drive transistor 166 and an initial current of 515 nA; "g8" represents the different OLED voltages of the drive transistor 166 and The current of the pixel circuit 160 when the initial current is 380 nA. It can be seen that even after the OLED voltage drifts by 2V, the pixel current is still very stable. Since the pixel circuit 210 of FIG. 13 is similar to the pixel circuit 160 of FIG. 15, it is obvious to those skilled in the art that the pixel current of the pixel circuit 210 will also be stable.

FIG. 19 shows a driving cycle and a programming cycle for driving the display array 1062 of FIG. 16 . In FIG. 16 , row j (j=1, 2, 3, 4) represents the jth row of the display array 1062 . In FIG. 19, "P" represents a program cycle; "C" represents a compensation cycle; and "D" represents a drive cycle. The programming period P of the jth row overlaps with the driving period D of the (j+1)th row. The compensation period C of the jth row overlaps with the programming period P of the (1+1)th row. The driving period D of the jth row overlaps with the compensation period C of the (j+1)th row.

FIG. 20 illustrates an example of a pixel circuit to which a pixel driving scheme according to yet another embodiment of the present invention is applied. The pixel circuit 300 of FIG. 20 includes an OLED 302 and a driving circuit 304 for driving the OLED 302. The drive circuit 304 includes a drive transistor 306 , a switch transistor 308 , a discharge transistor 310 and a storage capacitor 312 . OLED 302 includes, for example, an anode, a cathode, and a light emitting layer between the anode and the cathode.

In one example, transistors 306, 308, and 310 are n-type transistors. In another example, transistors 306, 308, and 310 are p-type transistors, or a combination of n-type and p-type transistors. In one example, transistors 306, 308, and 310 each include a gate terminal, a source terminal, and a drain terminal. Transistors 306, 308, and 310 may be fabricated using amorphous silicon, nano/microcrystalline silicon, polysilicon, organic semiconductor technology (eg, organic TFT), NMOS/PMOS technology, or CMOS technology (eg, MOSFET).

The drive transistor 306 is provided between the voltage supply line Vdd and the OLED 302. One terminal (eg, source) of drive transistor 306 is connected to Vdd. The other terminal (eg, the drain) of the drive transistor 306 is connected to one electrode (eg, the anode electrode) of the OLED 302. The other electrode (eg, cathode electrode) of OLED 302 is connected to power line (eg, common ground) 314 . One terminal of the storage capacitor 312 is connected to the gate terminal of the drive transistor 306 at node A4. The other terminal of the storage capacitor 312 is connected to Vdd. The gate terminal of switching transistor 308 is connected to select line SELM. One terminal of the switching transistor 308 is connected to the data line VDATA. The other terminal of switching transistor 308 is connected to node A4. The gate terminal of the discharge transistor 310 is connected to a selection line SEL[i−1] or SEL[i+1]. In one example, select line SEL[m] (m=i−1, i, 1+1) is an address line for the mth row in the display array. One terminal of the discharge transistor 310 is connected to node A4. The other terminal of discharge transistor 310 is connected to sensor 316 . In one example, each pixel includes a sensor 316 . In another example, sensor 316 is shared by multiple pixel circuits.

Sensor 316 includes a sense terminal and a bias terminal Vb1. The sense terminal of sensor 316 is connected to discharge transistor 310 . The bias terminal Vb1 may be connected to, for example, but not limited to, ground, Vdd, or a terminal (eg, source) of the drive transistor 306 . Sensor 316 detects the transfer of energy from the pixel circuit. The sensor 316 has a conductance that varies according to the sensing result. The sensor 316 absorbs the light or thermal energy emitted by the pixels, so the carrier density of the sensor changes. Sensor 316 provides feedback by, for example, but not limited to, optical, thermal, or other transduction means. Sensor 316 may be, but is not limited to, an optical sensor or a thermal sensor. Node A4 is discharged according to the conductance of sensor 316 as described below.

The driving circuit 304 is used to implement programming, compensation/correction and driving of the pixel circuit. Pixel circuit 300 provides constant brightness over its display lifetime by adjusting the gate voltage of drive transistor 306 .

FIG. 21 illustrates another example of a pixel circuit having the driving circuit 304 of FIG. 20 . The pixel circuit 330 of FIG. 21 is similar to the pixel circuit 300 of FIG. 20 . Pixel circuit 330 includes OLED 332. OLED 332 can be the same as or similar to OLED 302 of FIG. 20 . In the pixel circuit 330, one terminal (for example, the drain) of the driving transistor 306 is connected to one electrode (for example, the cathode electrode) of the OLED 332, and the other terminal (for example, the source) of the driving transistor 306 is connected to the power supply line (eg, common ground) 334 . Also, one terminal of the storage capacitor 312 is connected to the node A4 , and the other terminal of the storage capacitor 312 is connected to the power supply line 334 . In a similar manner to pixel circuit 300 of FIG. 20, pixel circuit 330 provides constant brightness over its display lifetime.

Referring to Figures 20 and 21, the aging of the drive transistor 306 and OLED 302/332 in the pixel circuit is compensated in two different ways: intra-pixel compensation and intra-panel correction.

In-pixel compensation will be described in detail. FIG. 22 illustrates an example of a driving method of a pixel circuit according to still another embodiment of the present invention. In-pixel compensation is implemented by applying the waveform of FIG. 22 to a pixel having the drive circuit 304 of FIGS. 20 and 21 .

The operating cycle of FIG. 22 includes three operating cycles 340 , 342 and 344 . The operation cycle 340 is a programming cycle of the i-th row and a driving cycle of the (i+1)-th row. The operation period 342 is a compensation period of the i-th row and a programming period of the (i+1)-th row. The operation period 344 is the driving period of the ith row and is the compensation period of the (i+1)th row. 20 to 22, in the programming period 340 of the i-th row of the display, when the selection line SEL[i] is at a high level, the node A4 of the i-th row in the pixel circuit is charged to the programming through the switching transistor 308 Voltage. During programming cycle 342 at row (i+1), SEL[i+1] goes high and the voltage stored at node A4 varies according to the conductance of sensor 316 . During the driving period 344 of the ith row, the current of the driving transistor 306 controls the brightness of the OLED.

The amount of discharge voltage at node A4 depends on the conductance of sensor 316 . Sensor 316 is controlled by OLED brightness or temperature. Therefore, as the pixel ages, the amount of discharge voltage decreases. This results in a constant brightness over the lifetime of the pixel circuit.

FIG. 23 illustrates an example of a display system for the driving circuit 304 of FIGS. 20 and 21 . Display system 1080 of FIG. 23 includes a display array 1082 having a plurality of pixels 1084 . The pixel 1084 includes the driving circuit 304 of FIGS. 20 and 21 , and may be the pixel circuit 300 of FIG. 20 or the pixel circuit 330 of FIG. 21 .

Display array 1082 is an active matrix light emitting display. In one example, display array 1082 is an AMOLED display array. Display array 1082 may be a monochrome, multicolor, or full-color display, and may include one or more electroluminescent (EL) elements (eg, organic EL). Display array 1082 may be used in a mobile device, personal digital assistant (PDA), computer monitor, or cell phone.

SEL[i] (i=m-1, m, m+1) in FIG. 23 is an address line for the i-th row. VDATAn (j+1) in FIG. 23 is the data line for the nth column. The address line SEL[i] corresponds to the selection line SEL[i] of FIGS. 20 and 21 . The data line VDATAn corresponds to VDATA of FIGS. 20 and 21 .

The gate driver 1086 includes an address driver for supplying address signals to respective address lines to drive the address lines. The data driver 1088 generates programming data and drives the data lines. Controller 1090 controls drivers 1086 and 1088 so that they drive pixel 1084 and implement in-pixel compensation as described above.

In FIG. 23, four pixels 1084 are shown. However, the number of pixels 1084 may vary according to system design and is not limited to four. In FIG. 23, three address lines and two data lines are shown. However, the number of select and data lines may vary depending on the system design.

In FIG. 23 , pixels 1084 each include the sensor 316 of FIGS. 20 and 21 . In another example, as shown in FIG. 24 , display array 1080 may include one or more reference pixels with sensor 316 .

FIG. 24 illustrates another example of a display system for the driving circuit 304 of FIGS. 20 and 21 . The display system 1100 of FIG. 24 includes a display array 1102 having a plurality of pixels 1104 and one or more reference pixels 1106 . The reference pixel 1106 includes the driving circuit 304 of FIG. 20 and FIG. 21 , and may be the pixel circuit 300 of FIG. 20 or the pixel circuit 330 of FIG. 21 . In FIG. 24, two reference pixels 1106 are shown. However, the number of pixels 1084 may vary according to system design and is not limited to two. Pixel 1104 includes an OLED and a drive transistor for driving the OLED, and does not contain the sensor 316 of FIGS. 20 and 21 . SEL_REF is a select line for selecting the discharge transistors in the array of reference pixels 1106 .

The gate driver 1108 drives a select line SEL_REF and address lines. Gate driver 1108 may be the same as or similar to gate driver 1108 of FIG. 24 . The data driver 1110 drives the data lines. The data driver 1110 may be the same as or similar to the data driver 1088 of FIG. 23 . Controller 1112 controls drivers 1108 and 1110 .

The reference pixels (1084 of FIG. 23, 1106 of FIG. 24) of FIGS. 23 and 24 can be operated on to provide aging information for the following in-panel algorithm: 1112) or the driver side (1088 of FIG. 23, 1110 of FIG. 24) corrects the programming voltage.

The in-panel correction will be described in detail. Referring to FIG. 21 , in-panel correction is performed by extracting the aging of the pixel circuit in a readback manner to the sensor 316 and correcting the programming voltage. In-panel correction compensates for pixel aging including threshold Vt drift and OLED degradation.

Figure 25 illustrates an example of a pixel system according to an embodiment of the present invention. The pixel system of FIG. 25 includes readback circuitry 360 . Readback circuit 360 includes charge pump amplifier 362 and capacitor 364 . One terminal of the charge pump amplifier 362 can be connected to the data line VDATA via the switch SW1. The other terminal of the charge pump amplifier 362 is connected to the bias voltage Vb2. The charge pump amplifier 362 reads back the voltage discharged from the node A4 via the switch SW1.

The output 366 of the charge pump amplifier 362 varies according to the voltage at node A4. The time-dependent characteristic of the pixel circuit can be read from node A4 via the charge pump amplifier 362 .

In FIG. 25, one readback circuit 360 and one switch SW1 are illustrated for one pixel circuit. However, readback circuit 360 and switch SW1 may be provided for a group of pixel circuits (eg, pixel circuits in a column). In FIG. 25 , a readback circuit 360 and a switch SW1 are provided in the pixel circuit 300 . In another example, the readback circuit 360 and the switch SW1 are applied to the pixel circuit 330 of FIG. 21 .

FIG. 26 illustrates an example of a display system having the readback circuit 360 of FIG. 25 . Display system 1120 of FIG. 26 includes a display array 1122 having a plurality of pixels 1124 . The pixel 1124 includes the driving circuit 304 of FIG. 20 and FIG. 21 , and may be the pixel circuit 300 of FIG. 20 or the pixel circuit 330 of FIG. 21 . Pixel 1124 may be the same as or similar to 1084 of FIG. 23 or 1106 of FIG. 24 .

In FIG. 26, four pixels 1124 are shown. However, the number of pixels 1124 may vary according to system design and is not limited to four. In FIG. 26, three address lines and two data lines are shown. However, the number of select and data lines may vary depending on the system design.

For each column, a readback circuit RB1[n] (n=j, j+1) and a switch SW1[n] (not shown) are provided. The readback circuit RB1[n] may include a switch SW1[n]. The readback circuit RB1[n] and the switch SW1[n] correspond to the readback circuit 360 and the switch SW1 of FIG. 25, respectively. In the following description, the terms RB1 and RB1[n] can be used interchangeably, and RB1 may refer to the readback circuit 360 of a certain row in FIG. 25 .

Display array 1122 is an active matrix light emitting display. In one example, display array 1122 is an AMOLED display array. Display array 1122 may be a monochrome, multicolor, or full-color display, and may include one or more electroluminescent (EL) elements (eg, organic EL). Display array 1122 may be used in a mobile device, personal digital assistant (PDA), computer monitor, or cell phone.

The gate driver 1126 includes an address driver for driving address lines. Gate driver 1126 may be the same as or similar to gate driver 1086 of FIG. 23 or gate driver 1108 of FIG. 24 . The data driver 1128 generates program data and drives the data lines. The data driver 1128 includes circuits that calculate programming data based on the output of the corresponding readback circuit RB1[n]. Controller 1130 controls drivers 1126 and 1128 to drive pixel 1124 as described above. The controller 1130 controls the switch SW1[n] to be turned on or off so that RB1[n] is connected to the corresponding data line VDATAn.

Pixels 1124 are operated to provide aging information for an in-panel algorithm in which the programming voltage is corrected at the controller 1130 or driver 1128 side according to the output voltage of the readback circuit RB1. A simple correction could be scaling in which the programming voltage is amplified by a change in the output voltage of the readback circuit RB1.

In FIG. 26 , pixels 1124 each include sensor 316 of FIGS. 20 and 21 . In another example, display array 1120 may include one or more reference pixels with sensor 316, as shown in FIG. 27 .

FIG. 27 illustrates another example of a display system with the readback circuit of FIG. 25 . Display system 1140 of FIG. 27 includes a display array 1142 having a plurality of pixels 1144 and one or more reference pixels 1146 . The reference pixel 1146 includes the driving circuit 304 of FIG. 20 and FIG. 21 , and may be the pixel circuit 300 of FIG. 20 or the pixel circuit 330 of FIG. 21 . In FIG. 27, two reference pixels 1146 are shown. However, the number of pixels 1084 may vary according to system design and is not limited to two. Pixel 1144 includes an OLED and a drive transistor for driving the OLED, and does not include the sensor 316 of FIGS. 20 and 21 . SEL_REF is a select line for selecting the discharge transistors in the array of reference pixels 1146 .

The gate driver 1148 drives address lines and select lines SEL_REF. The gate driver 1148 may be the same as or similar to the gate driver 1126 of FIG. 26 . The data driver 1150 generates program data, corrects the program data and drives data lines. The data driver 1150 may be the same as or similar to the data driver 1128 of FIG. 26 . Controller 1152 controls drivers 1148 and 1150 .

The reference pixel 1146 is operated to provide aging information for the in-panel algorithm, wherein the programming voltage is corrected at the controller 1152 or driver 1150 side according to the output voltage of the readback circuit RB1. A simple correction could be scaling such that the programming voltage is amplified by the change in the output voltage of the readback circuit RB1.

FIG. 28 illustrates an example of a driving method of a pixel circuit according to still another embodiment of the present invention. The display system 1120 of FIG. 26 and the display system 1140 of FIG. 27 are capable of operating according to the waveforms of FIG. 28 . In-panel correction is implemented by applying the waveform of FIG. 28 to a display system with a readback circuit (eg, 360 of FIG. 3, RB1 of FIGS. 26 and 27).

The operating cycles of FIG. 28 include operating cycles 380 , 382 , 383 , 384 and 386 . Operation cycle 380 is a program cycle for the ith row. The operation period 382 is the driving period of the i-th row. The drive cycle for each row is independent of the other rows. The operation cycle 383 is the initialization cycle of the i-th row. The operation period 384 is the integration period of the ith row. Operation cycle 386 is the readback cycle for the ith row.

Referring to FIGS. 25 to 28 , during the program period 380 of the i-th row, when the select line SEL[i] is at a high level, the node A4 in the i-th row of the pixel circuit is charged to a programming voltage through the switching transistor 308 . During the program cycle 380 of the ith row, the node A4 is charged to the corrected program voltage. During the driving period 382 of the i-th row, the brightness of the OLED is controlled by the driving transistor 306 . During the initialization period 383 of row i, node A4 is charged to a bias voltage. During the integration period 384 of the ith row, SEL[i−1] is high, thus discharging the voltage at node A4 through the sensor 316 . During readback period 386, the change in voltage at node A4 is read back for correction (eg, scaling of the programming voltage).

At the beginning of the readback cycle 384, the switch SW1 of the readback circuit RB1 is closed and the data line VDATA is charged to Vb2. In addition, capacitor 364 is charged to voltage Vpre due to leakage from all pixels connected to data line VDATA. Then, the selection line SEL[i] becomes high level, so the discharge voltage Vdisch is formed across the capacitor 364 . The difference between the two extracted voltages (Vpre and Vdisch) is used to calculate pixel aging.

Sensor 316 can be inactive most of the time and only active during integration period 384 . Therefore, sensor 316 ages very slightly. Furthermore, sensor 316 can be properly biased to significantly inhibit its degradation.

Furthermore, the method can be used to extract the aging of the sensor 316 . FIG. 29 illustrates an example of a method of extracting the aging of the sensor 316 . The sensor's extracted voltage for dark pixels and dark reference pixels can be used to find sensor 316 aging. For example, the display system 1140 of FIG. 27 can operate according to the waveforms of FIG. 29 .

The operating cycles of FIG. 29 include operating cycles 380 , 382 , 383 , 384 and 386 . Operation cycle 380 is a program cycle for the ith row. The operation period 382 is the driving period of the i-th row. The operation cycle 383 is the initialization cycle of the i-th row. The operation period 384 is the integration period of the ith row. Operation cycle 386 is the readback cycle for the ith row. Operation cycle 380 (second occurrence) is the initialization cycle of the reference row. Operation period 384 (second occurrence) is the integration period of the reference row. Operation cycle 386 (second occurrence) is the readback cycle (fetch) of the reference row.

The reference row includes one or more reference pixels (for example, 1146 in FIG. 27 ), and is located in the (m-1)th row. SEL_REF is a selection line for selecting a discharge transistor (eg, 310 of FIG. 25 ) in a reference pixel of a reference row.

Referring to Figures 25, 27 and 29, in order to extract the aging of the sensor 316, the normal pixel circuitry (eg, 1144) is disabled. The difference between the voltage extracted from the normal pixel via output 316 and the voltage extracted in the inactive state of the reference pixel (eg, 1146 ) is extracted. In the case that the reference pixel is not stressed, the off-state voltage of the reference pixel is extracted. This difference allows the degradation of the sensor 316 to be extracted.

FIG. 30 illustrates an example of a pixel system according to another embodiment of the present invention. The pixel system of FIG. 30 includes readback circuitry 400 . The readback circuit 400 includes a transimpedance amplifier 402 . One terminal of the transimpedance amplifier 402 can be connected to the data line VDATA via the switch SW2. The transimpedance amplifier 402 reads back the voltage discharged from the node A4 via the switch SW2. Switch SW2 may be the same as or similar to switch SW1 of FIG. 25 .

The output of transimpedance amplifier 402 varies according to the voltage at node A4. The time-dependent characteristic of the pixel circuit can be read from node A4 via a transimpedance amplifier 402 .

In FIG. 30, one readback circuit 400 and one switch SW2 are illustrated for one pixel circuit. However, readback circuit 400 and switch SW2 may be provided for a group of pixel circuits (eg, individual pixel circuits in a column). In FIG. 30 , a readback circuit 400 and a switch SW2 are provided in the pixel circuit 300 . In another example, the readback circuit 400 and the switch SW2 are applied to the pixel circuit 330 of FIG. 21 .

FIG. 31 illustrates an example of a display system having the readback circuit 400 of FIG. 30 . Display system 1160 of FIG. 31 includes a display array 1162 having a plurality of pixels 1164 . The pixel 1164 includes the driving circuit 304 of FIGS. 20 and 21 , and may be the pixel circuit 300 of FIG. 20 or the pixel circuit 330 of FIG. 21 . Pixel 1164 may be the same as or similar to pixel 1124 of FIG. 26 or pixel 1146 of FIG. 27 .

In FIG. 31, four pixels 1164 are shown. However, the number of pixels 1164 may vary according to system design and is not limited to four. In FIG. 31, three address lines and two data lines are shown. However, the number of select and data lines may vary according to system design.

For each column, a readback circuit RB2[n] (n=j, j+1) and a switch SW2[n] (not shown) are provided. Readback circuitry RB2[n] may include SW2[n]. The readback circuit RB2[n] and the switch SW2[n] correspond to the readback circuit 400 and the switch SW2 of FIG. 30, respectively. In the following description, the terms RB2 and RB2[n] can be used interchangeably, and RB2 may refer to the readback circuit 400 of a certain row of FIG. 30 .

Display array 1162 is an active matrix light emitting display. In one example, display array 1162 is an AMOLED display array. Display array 1162 can be a monochrome, multicolor, or full-color display, and can include one or more electroluminescent (EL) elements (eg, organic EL). Display array 1162 may be used in a mobile device, personal digital assistant (PDA), computer monitor, or cell phone.

The gate driver 1166 includes an address driver for driving address lines. The gate driver 1166 may be the same as or similar to the gate driver 1126 of FIG. 26 or the gate driver 1148 of FIG. 27 . The data driver 1168 generates program data and drives the data lines. Data driver 1168 includes circuitry to compute programming data from the output of a corresponding readback circuit RB2[n]. Controller 1170 controls drivers 1166 and 1168 to drive pixel 1164 as described above. The controller 1170 controls the switch SW2[n] to be turned on or off to connect RB2[n] to the corresponding data line VDATAn.

The pixels 1164 are operated to provide aging information for an in-panel algorithm, wherein the programming voltage is corrected at the controller 1170 or driver 1168 side according to the output voltage of the readback circuit RB2. A simple correction could be scaling such that the programming voltage is amplified by the change in the output voltage of the readback circuit RB2.

In FIG. 31 , pixels 1164 each include sensor 316 of FIGS. 20 and 21 . In another example, as shown in FIG. 32 , display array 1160 may include one or more reference pixels with sensor 316 .

FIG. 32 illustrates another example of a display system having the readback circuit 400 of FIG. 30 . The display system 1200 of FIG. 32 includes a display array 1202 having a plurality of pixels 1204 and one or more reference pixels 1206 . The reference pixel 1206 includes the driving circuit 304 of FIG. 20 and FIG. 21 , and may be the pixel circuit 300 of FIG. 20 or the pixel circuit 330 of FIG. 21 . In FIG. 32, two reference pixels 1206 are shown. However, the number of pixels 1204 can vary according to system design and is not limited to two. Pixel 1204 includes an OLED and a drive transistor for driving the OLED, and does not include sensor 316 of FIGS. 20 and 21 . SEL REF is the select line that selects the discharge transistors in the array of reference pixels 1206.

Gate driver 1208 drives select lines SEL REF and address lines. Gate driver 1208 may be the same as or similar to gate driver 1148 of FIG. 27 or gate driver 1166 of FIG. 31 . The data driver 1210 generates program data, corrects the program data and drives data lines. The data driver 1210 may be the same as or similar to the data driver 1150 of FIG. 27 or the data driver 1168 of FIG. 32 . Controller 1212 controls drivers 1208 and 1210 .

The reference pixel 1206 operates to provide aging information for an in-panel algorithm in which the programming voltage is corrected at the controller 1212 or driver 1210 side based on the output voltage of the readback circuit RB2. A simple correction could be scaling such that the programming voltage is amplified by the change in the output voltage of the readback circuit RB2.

FIG. 33 illustrates an example of a driving method of a pixel circuit according to still another embodiment of the present invention. The display system 1160 of FIG. 31 and the display system 1200 of FIG. 32 are capable of operating according to the waveforms of FIG. 33 . In-panel correction is implemented by applying the waveform of FIG. 33 to a display system with a readback circuit (eg, 400 of FIG. 30, RB2 of FIGS. 31 and 32).

The operation cycles of FIG. 33 include operation cycles 410, 422, and 422 for rows. The operation cycle 420 is a program cycle for the ith row. The operation period 422 is the driving period of the i-th row. The operation cycle 424 is a read-back (fetch) cycle of the i-th row.

Referring to FIGS. 30 to 33 , in the program period 420 of the i-th row, when the selection line SEL[i] is at a high level, the node A4 in the i-th row of the pixel circuit is charged to a programming voltage through the switching transistor 308 . During the driving period 422 of the ith row, the pixel brightness is controlled by the current of the driving transistor 306 . During the extraction period 424 of row i, SEL[i] and SEL[i−1] are high and monitor the sensor 316 current. Readback circuit RB2 amplifies this change in current. This change is used to measure the brightness degradation of the pixel and compensate for the brightness degradation of the pixel by correcting (eg, scaling) the programming voltage.

At the beginning of the readback cycle 424, when SEL[i] is low, the algorithm selects the row for correction with switch SW2 on. Therefore, the leakage current is extracted as the output voltage of the transimpedance amplifier 402 . The above selection of rows can be performed based on stress history, random or sequential methods, etc. Next, SEL[i] goes high, and the sensor current related to the brightness or temperature of the pixel is read back as the output voltage of the transimpedance amplifier 402 . Using the two extracted voltages of leakage current and sensor current, pixel aging can be calculated.

Sensor 316 can be inactive most of the time and only active during integration period 424 . Therefore, sensor 316 ages very slightly. Furthermore, sensor 316 can be properly biased to significantly inhibit its degradation.

Furthermore, the method can be used to extract the aging of the sensor 316 . FIG. 34 illustrates an example of a method of extracting the aging of the sensor 316 of FIG. 30 . For example, the display system 1200 of FIG. 32 can operate according to the waveforms of FIG. 34 .

The operating cycles of FIG. 34 include operating cycles 420 , 422 and 424 . Operation cycle 420 (first occurrence) is the programming cycle for row i. The operation period 422 is the driving period of the i-th row. Operation cycle 424 (first occurrence) is the readback (fetch) cycle for row i. Operation cycle 424 (second occurrence) is a readback (fetch) cycle of the reference row.

The reference row includes one or more reference pixels (for example, 1206 in FIG. 32 ), and is located in the (m-1)th row. SEL REF is a select line for selecting the discharge transistor (eg, 310 of FIG. 30 ) in the reference pixel of the reference row.

Referring to Figures 30, 32 and 34, in order to extract the aging of the sensor 316, the normal pixel circuitry (eg, 1204) is disabled. The difference between the voltage extracted from the normal pixel circuit via the output of the transimpedance amplifier 402 and the voltage extracted in the inactive state of the reference pixel (eg, 1206 ) is extracted. In the case that the reference pixel is not stressed, the off-state voltage of the reference pixel is extracted. As a result, the degradation of the sensor 316 is extracted.

FIG. 35 illustrates an example of a pixel circuit to which a pixel driving scheme according to yet another embodiment of the present invention is applied. The pixel circuit 500 of FIG. 35 includes an OLED 502 and a driving circuit 504 for driving the OLED 502. The drive circuit 504 includes a drive transistor 506 , a switch transistor 508 , a discharge transistor 510 , a regulation circuit 510 and a storage capacitor 512 .

OLED 502 may be the same as or similar to OLED 212 of FIG. 13 or OLED 302 of FIG. 20 . Capacitor 512 may be the same as or similar to capacitor 224 of FIG. 13 or capacitor 312 of FIG. 20 . Transistors 506 , 508 and 510 may be the same as or similar to transistors 206 , 220 and 222 of FIG. 13 or transistors 306 , 308 and 310 of FIG. 20 . In one example, transistors 506, 508, and 510 each include a gate terminal, a source terminal, and a drain terminal.

The driving transistor 506 is provided between the voltage supply line VDD and the OLED 502. One terminal (eg, drain) of drive transistor 506 is connected to VDD. The other terminal (eg, source) of drive transistor 506 is connected to one electrode (eg, anode electrode) of OLED 502. The other electrode (eg, cathode electrode) of OLED 502 is connected to power supply line VSS (eg, common ground) 514 . One terminal of the storage capacitor 512 is connected to the gate terminal of the drive transistor 506 at node A5. The other terminal of the storage capacitor 512 is connected to the OLED 502 . The gate terminal of switching transistor 508 is connected to select line SEL[n]. One terminal of the switching transistor 508 is connected to the data line VDATA. The other terminal of switching transistor 508 is connected to node A5. The gate terminal of the transistor 510 is connected to the control line CNT[n]. In one example, n represents the nth row in the display array. One terminal of transistor 510 is connected to node A.S. The other terminal of transistor 510 is connected to one terminal of regulation circuit 516 . The other terminal of the conditioning circuit 516 is connected to the OLED 502.

Since the resistance of the regulation circuit 516 varies according to pixel aging, the regulation circuit 516 is arranged to regulate the voltage of A5 in conjunction with the discharge transistor 510 . In one example, adjustment circuit 516 is transistor 218 of FIG. 13 . In another example, conditioning circuit 516 is sensor 316 of FIG. 20 .

In order to improve the drift of the threshold voltage of the driving transistor 506, the pixel circuit is turned off for a part of the frame time.

FIG. 36 illustrates an example of a driving method of a pixel circuit according to still another embodiment of the present invention. The waveforms of FIG. 36 are applied to the pixel circuit of FIG. 35 . The operation periods of the pixel circuit 500 include a programming period 520 , a discharging period 522 , a light emitting period 524 , a reset period 526 and a relaxation period 527 .

During programming cycle 520, node A5 is charged to programming voltage VP. During discharge period 522, CNT[n] goes high, and the voltage at node A5 is partially discharged to compensate for aging of the pixel. During the light emitting period 524, SEL[n] and CNT[n] go low. During an emission period 524, the drive transistor 506 controls the OLED 502. During the reset period 526 , CNT[n] becomes high level so as to fully discharge the voltage at the node A5 during the reset period 526 . During relaxation period 527 , drive transistor 506 is unstressed and recovers from emission period 524 . Thus, the aging of the drive transistor 506 is significantly reduced.

FIG. 37 illustrates an example of a display system including the pixel circuit of FIG. 35 . The display system 1300 of FIG. 37 includes a display array 1302 having a plurality of pixels 500 . Display array 1302 is an active matrix light emitting display. In one example, display array 1302 is an AMOLED display array. The pixels 500 are arranged in rows and columns. In FIG. 37, two pixels 500 of the nth row are shown. Display array 1302 may include more than two pixels.

Display array 1302 may be a monochrome, multicolor, or full-color display, and may include one or more electroluminescent (EL) elements (eg, organic EL). Display array 1302 may be used in a mobile device, personal digital assistant (PDA), computer monitor, or cell phone.

The address line SEL[n] is provided in the nth row. The control line CNT[n] is provided in the nth row. The data line VDATAk (k=j, j+1) is provided in the kth column. The address line SEL[n] corresponds to SEL[n] of FIG. 35 . The control line CNT[n] corresponds to CNT[n] of FIG. 35 . The data line VDATAk (k=j, j+1) corresponds to VDATA of FIG. 35 .

Gate driver 1306 drives SEL[n]. Data driver 1308 generates program data and drives VDATAk. Controller 1310 controls drivers 1306 and 1308 to drive pixel 500 to generate the waveforms of FIG. 36 .

FIG. 38 illustrates another example of a display system including the pixel circuit 500 of FIG. 35 . The display system 1400 of FIG. 38 includes a display array 1402 having a plurality of pixels 500 . Display array 1402 is an active matrix light emitting display. In one example, display array 1302 is an AMOLED display array. The pixels 500 are arranged in rows and columns. In FIG. 38, four pixels 500 of the nth row are shown. Display array 1402 may include more than four pixels.

SEL[i] (i=n, n+1) is a selection line and corresponds to SEL[n] of FIG. 35 . CNT[i] (i=n, n+1) is a control line and corresponds to CNT[n] of FIG. 35 . OUT[k] (k=n−1, n, n+1) is the output of the gate driver 1406 . The select line can be connected to one of the output from the gate driver 1402 or the VL line. VDATAm (m=j+1) is a data line and corresponds to VDATA of FIG. 35 . The data driver 1408 controls VDATAm. The controller 1410 controls the gate driver 1406 and the data driver 1408 to operate the pixel circuit 500 .

The control and select lines share the same output from gate driver 1406 through switch 1412 . During discharge cycle 526 of FIG. 36 , the RES signal reverses switch 1412 and connects the select line to the VL line with a low voltage to turn off transistor 508 of pixel circuit 500 . OUT[n-1] is high level, so CNT[n] is high level. Accordingly, the voltage at node A5 is regulated by regulation circuit 516 and discharge transistor 510 . During other operating cycles, the RES signal and switch 1412 connect the select line to the corresponding output of the gate driver (eg, SEL[n] to OUT[n]). The switch 1412 can be fabricated on the panel using panel fabrication technology (eg, amorphous silicon) or can be integrated inside the gate driver.

FIG. 39 illustrates an example of a pixel circuit to which a pixel driving scheme according to yet another embodiment of the present invention is applied. In the programming period, the pixel circuit 600 is programmed according to the programming information, and in the light emitting period, the pixel circuit 600 is driven to emit light according to the programming information. The pixel circuit 600 of FIG. 39 includes an OLED 602 and a driving circuit 604 for driving the OLED 602. The OLED 602 is a light emitting device that emits light during a light emitting cycle. OLED 602 has capacitance 632. OLED 602 includes, for example, an anode, a cathode, and a light emitting layer between the anode and the cathode.

The drive circuit 604 includes a drive transistor 606 , a switch transistor 608 , a switch bank 650 , a storage capacitor 612 and an adjustment transistor 646 . The drive transistor 606 delivers a drive current through the OLED 602 during an emission period. During a programming cycle, storage capacitor 612 is charged with a voltage based at least in part on the programming information. The switching transistor 608 operates according to a select line SEL and delivers a voltage to the storage capacitor 612 during a programming cycle. The regulation transistor 646 passes the leakage current to the gate terminal of the drive transistor 606 , thereby regulating the gate voltage of the drive transistor 606 .

In one example, transistors 606, 608, and 646 are n-type transistors. In another example, transistors 606, 608, and 646 are p-type transistors, or a combination of n-type and p-type transistors. In one example, transistors 606, 608, and 646 each include a gate terminal, a source terminal, and a drain terminal.

Transistors 606, 608, and 646 may be fabricated using amorphous silicon, nano/microcrystalline silicon, polysilicon, organic semiconductor technology (eg, organic TFT), NMOS/PMOS technology, or CMOS technology (eg, MOSFET).

The drive transistor 606 is provided between the voltage supply line VDD and the OLED 602 through a switch or directly. One terminal of the drive transistor 606 is connected to VDD. The other terminal of the drive transistor 606 is connected to one electrode of the OLED 602 (eg, the anode electrode). The gate terminal of the switching transistor 608 is connected to a select line SEL. One terminal of the switching transistor 608 is connected to the data line VDATA. The other terminal of switching transistor 608 is connected to node A. One terminal of the storage capacitor 612 is connected to node A. The other terminal of the storage capacitor 612 is connected to the OLED 602. The other electrode (eg, cathode electrode) of OLED 602 is connected to power line (eg, common ground) 614 .

One terminal of the adjustment transistor 646 is connected to the gate terminal of the drive transistor 606 . A second terminal of adjustment transistor 646 is connected to one electrode of OLED 602 (eg, the anode electrode). The gate terminal of the adjustment transistor 646 is connected to the second terminal of the adjustment transistor 646 . Thus, pass transistor 646 is biased in the subthreshold region where very little current is supplied. At higher temperatures, the subthreshold current of pass transistor 646 increases significantly, which reduces the average gate voltage of drive transistor 606 .

Switch bank 650 can include any of the discharge transistors, additional switching transistors, resistors, sensors, and/or amplifiers, etc. configurations described above with respect to various embodiments of the invention. For example, as shown in FIG. 1 , switch bank 650 can include discharge transistor 108 . During the light emitting period, the discharge transistor 108 drains the voltage charged on the storage capacitor 612 . In this embodiment, one terminal of discharge transistor 108 and the gate terminal of discharge transistor 108 are connected at node A to the gate terminal of drive transistor 606 . The other terminal of discharge transistor 108 is connected to OLED 602.

In another example, as shown in FIG. 8, the switch group 650 can include a second switch transistor 172 and a discharge transistor connected in series between the gate terminal of the drive transistor 606 and one electrode (e.g., the anode electrode) of the OLED 602. 168. The gate terminal of the switching transistor 172 is connected to the bias voltage line VB. The gate terminal of discharge transistor 168 is connected at node A to the gate terminal of drive transistor 606 . During the light emitting period, the discharge transistor 168 discharges the voltage charged on the storage capacitor 612 .

In yet another example, as shown in FIG. 13, the switch group 650 can include a second switch transistor 222 and a discharge transistor connected in series between the gate terminal of the drive transistor 606 and one electrode (e.g., the anode electrode) of the OLED 602. 218. The gate terminal of the switching transistor 222 is connected to the selection line SEL[n+1]. The gate terminal of discharge transistor 218 is connected at node A to the gate terminal of drive transistor 606 . During the light emitting period, the discharge transistor 218 discharges the voltage charged on the storage capacitor 612 .

In another example, as shown in FIG. 35, the switch bank 650 can include the discharge transistor 510 connected in series between the gate terminal of the drive transistor 606 and one electrode (eg, the anode electrode) of the OLED 602. The gate terminal of the discharge transistor is connected to the control line CNT[n]. The regulation circuit 516 is arranged to regulate the voltage of node A in conjunction with the discharge transistor 510 because the resistance of the regulation circuit 516 varies according to pixel aging. In one example, adjustment circuit 516 is transistor 218 of FIG. 13 . In another example, conditioning circuit 516 is sensor 316 of FIG. 20 . During the light emitting period, the discharge transistor 510 discharges the voltage charged on the storage capacitor 612 .

According to these embodiments, pixel circuit 600 provides a constant average current over a frame time.

FIG. 40 illustrates an example of a pixel circuit to which a pixel driving scheme according to another embodiment of the present invention is applied. In the programming period, the pixel circuit 610 is programmed according to the programming information, and in the light emitting period, the pixel circuit 610 is driven to emit light according to the programming information. The pixel circuit 610 of FIG. 40 includes an OLED 602 and a driving circuit for driving the OLED 602. The OLED 602 is a light emitting device that emits light during a light emitting cycle. OLED 602 has capacitance 632. OLED 602 includes, for example, an anode, a cathode, and a light emitting layer between the anode and the cathode.

The drive circuit includes a drive transistor 606 , a first switch transistor 608 , a second switch transistor 688 , a storage capacitor 612 , a discharge transistor 686 and a regulation transistor 646 . The drive transistor 606 delivers a drive current through the OLED 602 during the light emitting period. During a programming cycle, storage capacitor 612 is charged with a voltage based at least in part on the programming information. The first switch transistor 608 operates according to the select line and delivers a voltage to the storage capacitor 612 during a programming cycle. During the light emitting period, discharge transistor 686 discharges the voltage on storage capacitor 612 . The regulation transistor 646 passes the leakage current to the gate terminal of the drive transistor 606 , thereby regulating the gate voltage of the drive transistor 606 .

In one example, transistors 606, 608, 646, and 686 are n-type transistors. In another example, transistors 606, 608, 646, and 686 are p-type transistors, or a combination of n-type and p-type transistors. In one example, transistors 606, 608, 646, and 686 each include a gate terminal, a source terminal, and a drain terminal.

Transistors 606, 608, 646, and 686 may be fabricated using amorphous silicon, nano/microcrystalline silicon, polysilicon, organic semiconductor technology (eg, organic TFT), NMOS/PMOS technology, or CMOS technology (eg, MOSFET).

The drive transistor 606 is provided between the voltage supply line VDD and the OLED 602 through a switch or directly. One terminal of the drive transistor 606 is connected to VDD. The other terminal of the drive transistor 606 is connected to one electrode of the OLED 602 (eg, the anode electrode). The gate terminal of the first switching transistor 608 is connected to a select line SEL. One terminal of the switching transistor 608 is connected to the data line VDATA. The other terminal of switching transistor 608 is connected to node A. One terminal of the storage capacitor 612 is connected to node A. The other terminal of storage capacitor 612 is connected to OLED 602 at node B. The other electrode (eg, cathode electrode) of OLED 602 is connected to a power line (eg, common ground).

The gate terminal of the discharge transistor 686 is connected to the control line CNT. The control line CNT may correspond to CNT[n] of FIG. 35 . One terminal of the discharge transistor 686 is connected to node A. One terminal of the second switching transistor 688 is connected to node A. The other terminal of the discharge transistor 686 is connected at node C to the other terminal of the second switching transistor 688 . The gate terminal of the second switching transistor 688 is connected to node C.

One terminal of adjustment transistor 646 is connected to node C. A second terminal of adjustment transistor 646 is connected to one electrode of OLED 602 (eg, the anode electrode). The gate terminal of the pass transistor is connected to node A. Thus, pass transistor 646 is biased in the subthreshold region where very little current is supplied. However, such a small current is sufficient to change the gate voltage of the drive transistor 606 during the frame time. At higher temperatures, the subthreshold current of pass transistor 646 increases significantly, which reduces the average gate voltage of drive transistor 606 .

According to this embodiment, the pixel circuit 610 provides a constant average current over the frame time.

FIG. 41 illustrates an example of a pixel circuit to which a pixel driving scheme according to yet another embodiment of the present invention is applied. In the programming period, the pixel circuit 620 is programmed according to the programming information, and in the light emitting period, the pixel circuit 620 is driven to emit light according to the programming information. The pixel circuit 620 of FIG. 41 includes an OLED 602 and a driving circuit for driving the OLED 602. The OLED 602 is a light emitting device that emits light during a light emitting cycle. OLED 602 has capacitance 632. OLED 602 includes, for example, an anode, a cathode, and a light emitting layer between the anode and the cathode.

The drive circuit includes a drive transistor 606 , a first switch transistor 608 , a second switch transistor 688 , a storage capacitor 612 , a discharge transistor 686 and a regulation transistor 646 . The drive transistor 606 delivers a drive current through the OLED 602 during the light emitting period. During a programming cycle, storage capacitor 612 is charged with a voltage based at least in part on the programming information. The first switch transistor 608 operates according to the select line and delivers a voltage to the storage capacitor 612 during a programming cycle. During the light emitting period, discharge transistor 686 discharges the voltage on storage capacitor 612 . The regulation transistor 646 passes the leakage current to the gate terminal of the drive transistor 606 , thereby regulating the gate voltage of the drive transistor 606 .

The drive transistor 606 is provided between the voltage supply line VDD and the OLED 602 through a switch or directly. One terminal of the drive transistor 606 is connected to VDD. The other terminal of the drive transistor 606 is connected to one electrode of the OLED 602 (eg, the anode electrode). The gate terminal of the first switching transistor 608 is connected to a select line SEL. One terminal of the switching transistor 608 is connected to the data line VDATA. The other terminal of switching transistor 608 is connected to node A. One terminal of the storage capacitor 612 is connected to node A. The other terminal of storage capacitor 612 is connected to OLED 602 at node B. The other electrode (eg, cathode electrode) of OLED 602 is connected to a power line (eg, common ground).

The gate terminal of the discharge transistor 686 is connected to the control line CNT. The control line CNT may correspond to CNT[n] of FIG. 35 or the control line CNT of FIG. 40 . One terminal of the second switching transistor 688 is connected to node A. The other terminal of the second switching transistor 688 is connected to the OLED 602 at node B. The gate terminal of the second switching transistor is connected to OLED 602 at node B.

One terminal of the discharge transistor 686 is connected to node A. The other terminal of discharge transistor 686 is connected to one terminal of regulation transistor 646 . The other terminal of the adjustment transistor 646 is connected at node B to one electrode (eg, the anode electrode) of the OLED 602. The gate terminal of the pass transistor is connected to node A. Thus, pass transistor 646 is biased in a subthreshold region that provides very little current. However, such a small current is sufficient to change the gate voltage of the drive transistor 606 during the frame time. At higher temperatures, the subthreshold current of pass transistor 646 increases significantly, reducing the average gate voltage of drive transistor 606 .

According to this embodiment, the pixel circuit 610 provides a constant average current over the frame time.

According to another embodiment, a method of operating a display having a pixel circuit 600, 610 or 620 for driving a light emitting device is proposed. The method includes: during a programming period, charging the pixel circuit by turning on the first switching transistor so that a voltage is charged to a node in the pixel circuit connected to the capacitor and the gate terminal of the drive transistor; The leakage current is delivered to the gate terminal of the driving transistor, thereby regulating the voltage at the node; and draining the voltage at the node through the amplifying transistor during an emission period in which the pixel circuit is driven to emit light according to the programming information.

According to embodiments of the present invention, the driving circuit and the waveforms applied to the driving circuit provide a stable AMOLED display even though the backplane and OLED are not stable. The driving circuit and its waveform reduce the effects of differential aging of the pixel circuit. The pixel scheme in the embodiments does not require additional driving cycles or driving circuits, which enables low-cost applications in portable devices including mobile devices and PDAs. Furthermore, it is insensitive to temperature changes and mechanical stress, as appreciated by those of ordinary skill in the art.

One or more presently preferred embodiments have been described by way of example as described above. It will be apparent to those skilled in the art that many changes and modifications can be made without departing from the scope of the present invention as defined in the claims.

Claims (25)

1. a display system, described system comprises:

Image element circuit, described image element circuit is programmed according to programming information and is driven to emit light according to described programming information in light period in programming cycle, and described image element circuit comprises:

Luminescent device, described luminescent device is used in described light period luminous,

Driving transistors, described driving transistors is used for transmitting in described light period driving current through described luminescent device, and described driving transistors has gate terminal, source terminal and drain terminal,

Holding capacitor, use in described programming cycle and charge to described holding capacitor according to the voltage of described programming information at least partly, described holding capacitor has the first terminal and the second terminal, and described the first terminal is connected to the grid of described driving transistors,

First switching transistor, described first switching transistor selects line to operate according to first, and described first switching transistor is used for, in described programming cycle, described voltage is sent to described holding capacitor, and

Regulate transistor, described adjustment transistor is used for gate terminal leakage current being sent to described driving transistors, thus regulate the grid voltage of described driving transistors, described adjustment transistor has gate terminal, source terminal and drain terminal, the gate terminal of described adjustment transistor is connected to a terminal of described holding capacitor, and the one in the source terminal of described adjustment transistor and drain terminal is connected to the gate terminal of described driving transistors

Wherein, described image element circuit is provided in average current constant in frame time.

2. system according to claim 1, also comprises:

Array of display, described array of display comprises the multiple described image element circuit arranged in the mode of ranks, and

For driving the driver of described array of display.

3. system according to claim 1, also comprises:

Data driver, described data driver charges to described holding capacitor according to described programming information, thus programmes to described image element circuit via data line;

Gate drivers, described gate drivers is used for driving described first to select line; With

Controller, described controller is used for operating described data driver and described gate drivers.

4. system according to claim 1, also comprises:

Second switch transistor, described second switch transistor operates according to offset line, and described second switch transistor is used for the terminal described gate terminal of described driving transistors being connected to described holding capacitor.

5. system according to claim 4, also comprises:

Array of display, described array of display comprises the multiple described image element circuit arranged in the mode of ranks; With

For driving the driver of described array of display,

Wherein, described offset line is shared by the above image element circuit in multiple described image element circuit.

6. system according to claim 1, also comprises:

Second switch transistor, described second switch transistor selects line to operate according to second, and described second switch transistor is used for the terminal described gate terminal of described driving transistors being connected to described holding capacitor.

7. system according to claim 1, wherein, described discharge transistor operates according to control line.

8. system according to claim 1, also comprises:

Regulating circuit, described regulating circuit for regulating the grid voltage of described driving transistors,

Wherein, described discharge transistor is connected between described regulating circuit and described driving transistors.

9. system according to claim 8, wherein, described regulating circuit comprises second switch transistor.

10. system according to claim 8, wherein, described regulating circuit comprises sensor, and described sensor is for detecting the energy transferring from described image element circuit.

11. systems according to claim 10, wherein, described discharge transistor discharges to described voltage according to the conductance of described sensor.

12. systems according to claim 10, wherein, described sensor is optical sensor or thermal sensor.

13. systems according to claim 1, wherein, described adjustment transistor is biased and is in sub-threshold region.

14. 1 kinds of methods that the display of the image element circuit had for driving luminescent device is operated, described method comprises:

By conducting first switching transistor, described image element circuit is charged in programming cycle, voltage to be charged in described image element circuit as lower node with this: as described in node be connected to (a) have the capacitor of the first terminal and the second terminal as described in the gate terminal of the first terminal and (b) driving transistors, described driving transistors also has source terminal and drain terminal; And

Leakage current is transmitted by the adjustment transistor with gate terminal, source terminal and drain terminal, the described gate terminal of described adjustment transistor is connected to a terminal in the described the first terminal of described holding capacitor and described second terminal, and the one in the source terminal of described adjustment transistor and drain terminal is connected to the described gate terminal of described driving transistors, thus regulate the voltage of described Nodes.

15. methods according to claim 14, wherein, described image element circuit is provided in average current constant in frame time.

16. methods according to claim 14, wherein, carry out the first switching transistor described in conducting by selecting line.

17. methods according to claim 16,

Wherein, data driver produces programming information,

Wherein, described in gate driver drive, select line, and

Wherein, controller controls described data driver and described gate drivers.

18. methods according to claim 14, wherein, described discharge transistor and described driving transistors have identical bias condition.

19. methods according to claim 14, wherein, described adjustment transistor is offset to sub-threshold region.

20. methods according to claim 14, also comprise:

By conducting second switch transistor, described discharge transistor is forced to enter linear operating region.

21. methods according to claim 20, wherein, by second switch transistor described in offset line conducting.

22. methods according to claim 20, wherein, by selecting second switch transistor described in line conducting.

23. methods according to claim 14, wherein, carry out operated discharge transistor according to control line.

24. methods according to claim 14, also comprise:

The energy transferring from described image element circuit is detected by sensor.

25. methods according to claim 24, wherein, described discharge transistor discharges according to the voltage of the conductance of described sensor to described Nodes.