CN104662664B - Silicon carbide semiconductor device - Google Patents

Abstract

A silicon carbide semiconductor device (1) includes an element region (IR) and a guard ring region (5). The semiconductor element (7) is arranged in the element region (IR). The guard ring region (5) surrounds the element region (IR) in plan view and has the first conductivity type. The semiconductor element (7) comprises a drift region (12) having a second conductivity type different from the first conductivity type. The guard ring region (5) includes a linear region (B) and a curvature region (A) continuously connected to the linear region (B). A value obtained by dividing a curvature radius (R) of an inner peripheral portion (2c) of a curvature region (A) by a thickness (Tl) of the drift region (12) is not less than 5 and not more than 10. Therefore, a silicon carbide semiconductor device (1) capable of suppressing a decrease in on-state current while increasing the breakdown voltage can be provided.

Description

Silicon carbide semiconductor device

technical field

The present invention relates to a silicon carbide semiconductor device, more particularly, to a silicon carbide semiconductor device with a guard ring region.

Background technique

A guard ring region may be formed in a semiconductor device such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) to surround a region where a semiconductor element is provided in order to suppress the semiconductor element from being damaged by concentration of an electric field.

For example, Japanese Patent Publication No. 2008-4643 (Patent Document 1) describes a structure of a MOSFET made of silicon including an element region and a terminal region formed to surround the element region, and a guard ring is formed at the terminal region . According to the MOSFET described in Japanese Patent Publication No. 2008-4643, the guard ring layer and the embedded guard ring layer are formed to have curvature at the corners of the outermost base region so that they are concentric with each other. Also, in order to suppress electric field concentration at corners of the outermost base region, the outermost base region is configured to have a curvature radius of about two to four times the thickness of the drift layer.

Citation list

patent documents

PTD 1: Japanese Patent Publication No.2008-4643

Contents of the invention

technical problem

However, if a MOSFET using silicon carbide having a bandgap larger than that of silicon is manufactured such that the radius of curvature of the outermost base region (in other words, the radius of curvature of the guard ring formed to contact the end of the outermost base region) is approximately Two to four times the thickness of the drift layer, the electric field will concentrate at the corners of the guard ring, thus damaging the MOSFET.

Meanwhile, in order to alleviate electric field concentration at the corners of the guard ring, it is considered to increase the radius of curvature of the corners of the guard ring. However, a larger radius of curvature results in a smaller element area, resulting in reduced on-state current.

In view of this, an object of the present invention is to provide a silicon carbide semiconductor device capable of increasing breakdown voltage while suppressing reduction in on-state current.

problem solving

While silicon has a cubic crystal structure, silicon carbide can have a hexagonal crystal structure. Silicon having a cubic crystal structure does not have anisotropy of electric field strength, but silicon carbide having a hexagonal crystal structure has anisotropy of electric field strength. Specifically, the electric field strength of silicon carbide having a hexagonal crystal structure in the direction parallel to the c-axis is 1.6 times that in the direction perpendicular to the c-axis. Therefore, the ratio of the radius of curvature of the guard ring in silicon to the thickness of the drift layer does not apply at all to silicon carbide. As a result of diligent studies, the present inventors have achieved the present invention by finding that a value obtained by dividing the radius of curvature of the inner peripheral portion of the curvature region by the thickness of the drift region is set to be not less than 5 and not When it is greater than 10, the breakdown voltage of the silicon carbide semiconductor device can be increased while suppressing the reduction of the on-state current.

A silicon carbide semiconductor device according to the present invention includes an element region and a guard ring region. In the element region, semiconductor elements are provided. The guard ring region has the first conductivity type and surrounds the element region in plan view. The semiconductor component includes a drift region having a second conductivity type different from the first conductivity type. The guard ring region includes a linear region and a curvature region consecutively connected to the linear region. A value obtained by dividing the radius of curvature of the inner peripheral portion of the curvature region by the thickness of the drift layer is not less than 5 and not more than 10.

According to the silicon carbide semiconductor device according to the present invention, the value obtained by dividing the radius of curvature of the inner peripheral portion of the curvature region by the thickness of the drift layer is not less than 5 and not more than 10. Therefore, it is possible to increase the breakdown voltage while suppressing a decrease in on-state current.

Preferably, in the silicon carbide semiconductor device described above, the semiconductor element includes a body region contacting the drift region and having the second conductivity type. The thickness of the body region is greater than that of the guard ring region. Therefore, electric field concentration can be effectively suppressed at the corner portion of the body region.

Preferably, in the above silicon carbide semiconductor device, the guard ring region includes a contact body region and has a JTE region of the second conductivity type. Therefore, the breakdown voltage can be improved by contacting the JTE region of the body region 13 .

Preferably, in the above silicon carbide semiconductor device, the semiconductor element includes a source region contacting the body region and having the first conductivity type, and a source electrode contacting the source region. The JTE region contacts the source electrode. Therefore, the source region can extract electrons from the JTE region at high speed, whereby a depletion layer can be formed also in high-frequency operation.

Preferably, in the above silicon carbide semiconductor device, the guard ring region includes a guard ring not in contact with the element region. Therefore, the breakdown voltage can be increased by the guard ring not in contact with the element region.

Preferably, in the above silicon carbide semiconductor device, a plurality of guard rings are provided. A value obtained by dividing the radius of curvature of the inner peripheral portion of the curvature region of the innermost guard ring of the plurality of guard rings by the thickness of the drift layer is not less than 5 and not more than 10. In the case where there are a plurality of guard rings, the radius of curvature of the innermost guard ring becomes smaller than the radii of curvature of the other guard rings. Since the value obtained by dividing the radius of curvature of the inner peripheral portion of the curvature region of the innermost guard ring by the thickness of the drift layer is not less than 5 and not more than 10, the on-state current can be suppressed while increasing the breakdown voltage. reduce.

Preferably, the silicon carbide semiconductor device described above further includes a field stop region having the first conductivity type and surrounding the guard ring region in plan view. Therefore, the breakdown voltage of the silicon carbide semiconductor device can be further improved.

Preferably, in the silicon carbide semiconductor device described above, the distance between the outer peripheral portion of the guard ring region and the inner peripheral portion of the field stop region is constant at any position of the outer peripheral portion of the guard ring region in plan view. Therefore, local concentration of the electric field can be suppressed.

Beneficial Effects of the Invention

As apparent from the above description, according to the present invention, it is possible to provide a silicon carbide semiconductor device capable of increasing breakdown voltage while suppressing a decrease in on-state current.

Description of drawings

FIG. 1 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device in one embodiment of the present invention.

FIG. 2 is a schematic plan view showing the configuration of the silicon carbide semiconductor device in this embodiment of the invention.

3 is a schematic cross-sectional view showing the configuration of a first modification of the silicon carbide semiconductor device in this embodiment of the invention.

4 is a schematic cross-sectional view showing the configuration of a second modification of the silicon carbide semiconductor device in this embodiment of the invention.

5 is a schematic cross-sectional view showing the configuration of a third modification of the silicon carbide semiconductor device in this embodiment of the invention.

6 is a schematic plan view showing a third modification of the silicon carbide semiconductor device in this embodiment of the present invention.

FIG. 7 is a flowchart schematically showing a method of manufacturing a silicon carbide semiconductor device in this embodiment of the present invention.

8 is a schematic cross-sectional view showing the first step of the method of manufacturing the silicon carbide semiconductor device in this embodiment of the invention.

9 is a schematic cross-sectional view showing a second step of the method of manufacturing the silicon carbide semiconductor device in this embodiment of the invention.

10 is a schematic cross-sectional view showing a third step of the method of manufacturing the silicon carbide semiconductor device in this embodiment of the present invention.

FIG. 11 shows the relationship between on-resistance and breakdown voltage.

detailed description

Embodiments of the present invention are explained below with reference to the accompanying drawings. It should be noted that in the following drawings, the same or corresponding parts are designated by the same reference symbols and will not be described repeatedly. For crystallographic notation in this specification, individual crystal orientations are represented by [ ], group crystal orientations are represented by < >, and individual crystal planes are represented by ( ), group crystal planes are represented by { }. In addition, a negative index is considered to be crystallographically represented by "-" (bar) placed on the number, but is represented by placing a minus sign before the number in this specification. For the description of the angle, a system with an omnidirectional angle of 360° is used.

First, the following explains the configuration of a MOSFET as a silicon carbide semiconductor device in one embodiment of the present invention.

Referring to FIGS. 1 and 2, MOSFET 1 has an element region IR (active region) and an end region OR (inactive region) surrounding the element region IR. The termination region OR includes a guard ring 5 . In other words, the element region IR is surrounded by the guard ring 5 . In the element region IR, semiconductor elements 7 such as transistors or diodes are provided.

Semiconductor element 7 mainly includes, for example, silicon carbide substrate 10 made of hexagonal silicon carbide, gate insulating film 15 , gate electrode 17 , source electrode 16 , and drain electrode 20 . Silicon carbide substrate 10 mainly includes n+ substrate 11 , drift region 12 , body region 13 , n+ source region 14 and p+ region 18 . Silicon carbide substrate 10 is made of, for example, hexagonal silicon carbide. Silicon carbide substrate 10 may have, for example, main surface 10 a corresponding to a plane shifted by about not more than 8° relative to the {0001} plane.

n + substrate 11 is a substrate made of hexagonal silicon carbide and having n-type conductivity (first conductivity type).

n+ substrate 11 includes n-type impurities such as N (nitrogen) at a high concentration. The concentration of impurities such as nitrogen in n+ substrate 11 is, for example, about 1.0×10 ¹⁸ cm ⁻³ .

Drift region 12 is an epitaxial layer made of silicon carbide and having n-type conductivity. Drift region 12 has, for example, a thickness T1 of approximately 15 μm. Preferably, the thickness T1 of the drift region 12 is not less than 14.5 μm and not more than 15.5 μm. The n-type impurity in drift region 12 is, for example, nitrogen, and is contained in drift region 12 at an impurity concentration lower than that of the n-type impurity in n + substrate 11 . The concentration of impurities such as nitrogen in drift region 12 is, for example, about 7.5×10 ¹⁵ cm ⁻³ .

The p-body region 13 has p-type conductivity. P body region 13 is formed in drift region 12 to include main surface 10 a of silicon carbide substrate 10 . P body region 13 includes p type impurities such as Al (aluminum) or B (boron). The concentration of impurities such as aluminum in p body region 13 is, for example, about 1×10 ¹⁷ cm ⁻³ .

The n+ source region 14 has n-type conductivity. N + source region 14 includes main surface 10 a and is formed in p body region 13 so as to be surrounded by p body region 13 . N + source region 14 includes an n-type impurity such as P (phosphorus) at a concentration higher than that in drift region 12 , for example, at a concentration of about 1×10 ²⁰ cm ⁻³ .

The p+ region 18 has p-type conductivity. p + region 18 is formed in contact with main surface 10 a and p body region 13 so as to extend through the vicinity of the center of n + source region 14 . P ⁺ region 18 includes a p-type impurity such as aluminum or boron at a concentration higher than that of p-type impurity in p body region 13 , for example, at a concentration of about 1×10 ²⁰ cm ⁻³ .

Gate insulating film 15 is formed in contact with drift region 12 to extend from over the upper surface of one n + source region 14 to over the upper surface of the other n + source region 14 . Gate insulating film 15 is made of silicon dioxide, for example.

Gate electrode 17 is arranged on and in contact with gate insulating film 15 so as to extend from over one n + source region 14 to over the other n + source region 14 . Gate electrode 17 is made of, for example, a conductor such as polysilicon or aluminum.

On one main surface 10 a , source electrode 16 is arranged in contact with n+ source region 14 and p+ region 18 . Also, the source electrode 16 includes, for example, titanium (Ti) atoms, aluminum (Al) atoms, and silicon (Si). The source electrode 16 as an ohmic contact electrode containing Ti, Al, and Si thus has a low contact resistance with respect to the p-type silicon carbide region and the n-type silicon carbide region.

Drain electrode 20 is formed in contact with the main surface of n + substrate 11 opposite to the main surface on which drift region 12 is formed. This drain electrode 20 may have the same construction as the source electrode 16 or may be made of a different material, such as Ni, for example allowing an ohmic contact with the n+ substrate 11 . Therefore, drain electrode 20 is electrically connected to n + substrate 11 .

Guard ring region 5 has a ring shape, and is arranged in termination region OR of silicon carbide substrate 10 so as to surround element region IR in which semiconductor element 7 is provided. Guard ring region 5 has p-type conductivity (second conductivity type). The guard ring area 5 is a conductive area as a guard ring. The guard ring region 5 includes, for example: a JTE region 2 in contact with the p-body region 13 ; and a plurality of guard rings 3 not in contact with the p-body region 13 . Preferably, the p-body region 13 of the semiconductor element 7 has a thickness T1 greater than the thickness T2 of the guard ring region 5 .

The plurality of guard rings 3 of the guard ring region 5 include impurities such as boron or aluminum. The impurity concentration in each of the plurality of guard rings 3 is lower than that of the p body region 13 . The impurity concentration in each of the plurality of guard rings 3 is, for example, 1.3×10 ¹³ cm ⁻³ , and preferably approximately not less than 8×10 ¹² cm ⁻³ and not more than 1.4×10 ¹³ cm ⁻³ .

As shown in FIG. 2 , the guard ring region 5 has a linear region B and a curvature region A connected to the linear region B in succession. Specifically, the linear regions B and the curvature regions A are alternately arranged to form an annular guard ring region 5 surrounding the element region IR. The curvature region A has an inner peripheral portion 2c formed along a circular arc with a center C. As shown in FIG. The area of curvature A of the guard ring area 5 has a radius of curvature R. As shown in FIG. The curvature radius R is, for example, not less than 50 μm and not more than 1260 μm.

The value obtained by dividing the curvature radius R of the inner peripheral portion 2c of the guard ring region 5 by the thickness T1 of the drift region 12 of the semiconductor element 7 is not less than 5 and not more than 10. For example, the thickness T1 of the drift region 12 is 15 μm and the radius of curvature of the inner circumference of the inner peripheral portion 2 c of the guard ring region 5 is 125 μm. In the above case, the value obtained by dividing the curvature radius R of the inner peripheral portion 2 c of the guard ring region 5 by the thickness T1 of the drift region 12 of the semiconductor element 7 is about 8.3. When the guard ring region 5 includes a plurality of guard rings 3, the inner peripheral portion 2c of the guard ring region 5 refers to the inner peripheral portion 2c of the guard ring 3 arranged closest to the semiconductor element 7 (in other words, the innermost guard ring 3) .

When the guard ring area 5 includes a plurality of guard rings 3 , the plurality of guard rings 3 are arranged with gaps interposed therebetween. Specifically, each of the plurality of guard rings 3 has a linear region B and a curvature region A. The linear regions B of the plurality of guard rings 3 are arranged parallel to each other in plan view. Meanwhile, the curvature regions A of the plurality of guard rings 3 are arranged along arcs of concentric circles having a center C and having different radii. The respective concentrations of p-type impurities in the plurality of guard rings 3 may be the same or may be different from each other. Among the plurality of guard rings 3 , the guard ring 3 on the outer peripheral side preferably has an impurity concentration lower than that of the guard ring 3 on the inner peripheral side.

The guard ring region 5 may have a p-body region 13 contacting the semiconductor element 7 and having, for example, a JTE (Junction Termination Extension) region 2 with p-type conductivity. The JTE region 2 may have the same impurity as that of the guard ring 3 at the same impurity concentration as that of the guard ring 3 . The impurity concentration of JTE region 2 is lower than that of p body region 13 . Preferably, the thickness T1 of the p-body region 13 of the semiconductor element 7 is greater than the thickness T2 of the JTE region 2 . It should be noted that when the guard ring region 5 includes the JTE region 2 and the guard ring 3, the guard ring region 5 refers to the region between the inner peripheral portion 2c of the JTE region 2 and the outer peripheral portion 3d of the outermost guard ring 3 in plan view.

Referring to FIG. 3 , guard ring region 5 of MOSFET 1 may not have JTE region 2 contacting p-body region 13 and may have guard ring 3 not contacting p-body region 13 . The impurity and impurity concentration of the guard ring 3 are the same as those of the guard ring 3 described above. One guard ring 3 or a plurality of guard rings 3 may be provided. Preferably, a plurality of guard rings 3 are arranged with gaps interposed therebetween.

Referring to FIG. 4 , MOSFET 1 may have JTE region 2 contacting p body region 13 , and source electrode 16 a may be formed contacting JTE region 2 . Source electrode 16 a is electrically connected to source electrode 16 formed in contact with source region 14 surrounded by p body region 13 and p + region 18 surrounded by source region 14 .

Referring to FIGS. 5 and 6 , the MOSFET 1 further includes a field stop region 4 having n-type conductivity so as to surround a guard ring region 5 having p-type conductivity. Field stop region 4 has the same conductivity type (n type) as drift region 12 . Field stop region 4 has an impurity concentration higher than that of drift region 12 . The impurity concentration in field stop region 4 is, for example, about 1.0×10 ¹⁸ cm ⁻³ . Preferably, at any position of the outer peripheral portion 3d of the guard ring area 5, the shortest distance D between the outer peripheral portion 3d of the guard ring area 5 and the inner peripheral portion 4c of the field stop area 4 is constant. When the guard ring region 5 has a plurality of guard rings 3 , the shortest distance D refers to the shortest distance between the outer peripheral portion 3 d of the outermost guard ring 3 and the inner peripheral portion 4 c of the field stop region 4 .

The operation of MOSFET 1 is explained below. When gate electrode 17 is fed with a voltage not greater than the threshold value, that is, during an off state, p-body region 13 and drift region 12 just below gate insulating film 15 are reverse-biased, with the result that MOSFET 1 enters a non-conductive state. On the other hand, when gate electrode 17 is fed with a positive voltage, an inversion layer is formed in the channel region near the position where p body region 13 contacts gate insulating film 15 . Therefore, n+ source region 14 and drift region 12 are electrically connected to each other, whereby current flows between source electrode 22 and drain electrode 20 .

A method of manufacturing MOSFET 1 according to this embodiment of the present invention is explained below.

Referring to FIG. 8 , silicon carbide substrate 10 is first prepared in a substrate preparation step ( S10 : FIG. 7 ). Specifically, drift region 12 is formed by epitaxial growth on one main surface of n + substrate 11 made of hexagonal silicon carbide. For example, epitaxial growth can be performed using a mixed gas of SiH ₄ (silane) and C ₃ H ₈ (propane) as a source gas. In this case, for example, N (nitrogen) is introduced as an n-type impurity. In this way, drift region 12 is formed, which includes n-type impurities at a lower concentration than that in n+ substrate 11 .

Next, an oxide film made of silicon dioxide is formed on main surface 10 a of silicon carbide substrate 10 by, for example, CVD (Chemical Vapor Deposition). Subsequently, a photoresist is coated on the oxide film, and then exposure and development are performed, thereby forming a photoresist film having an opening at a region conforming to the shape of the desired p-body region 13 . Subsequently, for example, using a photoresist film as a mask, the oxide film is partially removed by means of an RIE (Reactive Ion Etching) mask, thereby forming a mask layer composed of the oxide film having an opening pattern on drift region 12 .

Referring to FIG. 9, an ion implantation step (S20: FIG. 7) is performed. In the ion implantation step, ions are implanted into silicon carbide substrate 10 , thereby forming p body region 13 , n+ source region 14 , and guard ring region 5 . Specifically, after removing the above-mentioned photoresist film, p-type impurity ions such as Al are implanted into drift region 12 using the mask layer as a mask, thereby forming p-body region 13 and guard ring region 5 . Also, after removing the oxide film used as a mask, a mask layer having an opening at a region conforming to the shape of the desired n + source region 14 is formed.

Next, the mask layer is used as a mask to introduce n-type impurities such as P (phosphorus) into drift region 12 by ion implantation, thereby forming n + source region 14 . Subsequently, a mask layer having an opening at a region conforming to the shape of the desired p+ region 18 is formed, and this mask layer is used as a mask for introducing p-type impurities such as Al or B into the drift region 12 by ion implantation. , thereby forming the p+ region 18 . It should be noted that p body region 13 of semiconductor element 7 may be formed before/after formation of guard ring region 5 . The formation of the guard ring region 5 specifically refers to the formation of the JTE region 2 and the guard ring 3 . It should be noted that the implantation depth of the p body region 13 is preferably greater than the implantation depth of the guard ring region 5 . Also, the field stop region 4 may be formed to surround the guard ring region 5 in plan view.

Next, heat treatment is performed to activate the impurities introduced by the above ion implantation. Specifically, for example, silicon carbide substrate 10 having ions implanted therein is heated at about 1700° C. under an Ar (argon gas) atmosphere, and kept for about 30 minutes.

Referring to FIG. 10, a gate insulating film forming step (step S30: FIG. 7) is performed. Specifically, first, silicon carbide substrate 10 in which desired ion implantation regions are formed through the above steps is thermally oxidized (S20: FIG. 7). For example, thermal oxidation can be performed by heating at about 1300° C. for about 40 minutes under an oxygen atmosphere. Thus, gate insulating film 15 made of silicon dioxide is formed on main surface 10 a of silicon carbide substrate 10 .

Next, a gate electrode forming step (S40: FIG. 7) is performed. In this step, gate electrode 17 made of a conductor such as polysilicon or aluminum is formed in contact with gate insulating film 15 so as to extend from over one n + source region 14 to over the other n + source region 14 . When polysilicon is used as the material of gate electrode 17, polysilicon can be configured to include phosphorus at a high concentration greater than 1×10 ²⁰ cm ⁻³ . Subsequently, an insulating film made of, for example, silicon dioxide is formed to cover gate electrode 17 .

Next, an ohmic electrode forming step ( S50 : FIG. 7 ) is performed. Specifically, for example, a photoresist pattern is formed to expose a part of n+ source region 14 and p+ region 18, and a metal film including, for example, Si atoms, Ti atoms, and Al atoms is formed on the entire surface of the substrate by, for example, sputtering. Subsequently, metal film 50 is formed in contact with gate insulating film 15 and in contact with p + region 18 and n + source region 14 , for example, by lifting off the photoresist pattern. Subsequently, for example, by heating the metal film at about 1000° C., source electrode 16 is formed in ohmic contact with silicon carbide substrate 10 . Also, drain electrode 20 is formed in contact with n + substrate 11 of silicon carbide substrate 10 . MOSFET 1 shown in Figure 1 is completed.

It should be noted that a configuration may be employed in which n-type conductivity and p-type conductivity in the embodiments are replaced with each other. Also, in the present embodiment, a planar MOSFET has been described as an example of a silicon carbide semiconductor device, and the silicon carbide semiconductor device may be a trench MOSFET. Also, the silicon carbide semiconductor device may be an IGBT (Insulated Gate Bipolar Transistor) or the like.

Next, the action and effect of the method of manufacturing MOSFET 1 according to the present embodiment are explained below.

According to MOSFET 1 according to the present embodiment, the value obtained by dividing the curvature radius R of inner peripheral portion 2c of curvature region A of guard ring region 5 by the thickness of drift region 12 is not less than 5 and not more than 10. Since the value obtained by dividing the curvature radius R of the inner peripheral portion 2c of the curvature region A of the guard ring region 5 by the thickness of the drift region 12 is not less than 5 and not more than 10, it is possible to suppress conduction while increasing the breakdown voltage. reduction in on-state current.

Furthermore, according to MOSFET 1 according to the present embodiment, semiconductor element 7 includes body region 13 contacting drift region 12 and having the second conductivity type. The thickness T2 of the body region 13 is greater than the thickness T3 of the guard ring region 5 . Therefore, electric field concentration can be effectively suppressed at the corner portion 13 c of the body region 13 .

Furthermore, according to MOSFET 1 according to the present embodiment, guard ring region 5 includes contact body region 13 and has JTE region 2 of the second conductivity type. Therefore, the breakdown voltage can be improved by contacting the JTE region 2 of the body region 13 .

Furthermore, according to MOSFET 1 according to the present embodiment, semiconductor element 7 includes source region 14 contacting body region 13 and having the first conductivity type, and source electrode 16 contacting source region 14 . JTE region 2 contacts source electrode 16 . Therefore, source region 14 can extract electrons from JTE region 2 at a high speed, whereby a depletion layer can be formed also under high-frequency operation.

Furthermore, according to MOSFET 1 according to the present embodiment, guard ring region 5 includes guard ring 3 not in contact with element region IR. Therefore, the breakdown voltage can be increased by the guard ring 3 not in contact with the element region IR.

Furthermore, according to the MOSFET 1 according to the present embodiment, a plurality of guard rings 3 are provided. A value obtained by dividing the curvature radius R of the inner peripheral portion 2c of the curvature region A of the innermost guard ring 3 of the plurality of guard rings 3 by the thickness T1 of the drift region 12 is not less than 5 and not more than 10. In the case where a plurality of guard rings 3 exist, the radius of curvature R of the innermost guard ring 3 becomes smaller than the radii of curvature R of the other guard rings 3 . Since the value obtained by dividing the radius of curvature R of the inner peripheral portion of the curvature region A of the innermost guard ring 3 by the thickness T1 of the drift region 12 is not less than 5 and not more than 10, it is possible to suppress the breakdown voltage while increasing the breakdown voltage. reduction of on-state current.

MOSFET 1 according to the present embodiment further includes field stop region 4 having the first conductivity type and surrounding guard ring region 5 in plan view. Therefore, the breakdown voltage of the silicon carbide semiconductor device can be further improved.

Furthermore, according to the MOSFET 1 according to the present embodiment, at any position of the outer peripheral portion 3d of the guard ring region 5 in plan view, the distance between the outer peripheral portion 3d of the guard ring region 5 and the inner peripheral portion 4c of the field stop region 4 The distance d is kept constant. Therefore, local concentration of the electric field can be suppressed.

[example]

In this example, the on-state current and the strike current were examined by changing the value obtained by dividing the radius of curvature R of the inner peripheral portion of the guard ring 3 by the thickness T1 of the drift region 12 (hereinafter referred to as "drift layer ratio"). The relationship between the breakdown voltage. First, three types of MOSFETs 1 each made of silicon carbide and including drift region 12 having thickness T1 of 15 μm were prepared using the manufacturing method shown in this example. The n-type impurity concentration of drift region 12 was set to 7.5×10 ¹⁵ cm ⁻³ . The die of MOSFET 1 is a square with 3mm on each side.

In MOSFET 1, guard ring region 5 is provided to surround element region IR. The impurity concentration of the guard ring region 5 was set to 1.3×10 ¹³ cm ⁻³ . The radius of curvature R of the inner peripheral portion 2c of the curvature region A of the guard ring region 5 of the MOSFET 1 is set to 50 μm, 125 μm, and 1260 μm, respectively. That is, three types of MOSFET 1 were prepared with drift layer ratios of 3.3, 8.3, and 84.3. For each MOSFET 1, on-state current and breakdown voltage were measured. It should be noted that the shape of the element region IR of the MOSFET having the drift layer ratio of 84.3 is circular in plan view.

The breakdown voltage was measured by applying a reverse voltage to each MOSFET and measuring the reverse current. The breakdown voltage is defined as the voltage at which the reverse current rapidly increases as the reverse voltage increases. The final breakdown portion was specified using a radio microscope. For example, when MOSFET 1 having a drift layer ratio of 3.3 and a reverse voltage of 1200V was observed with a radio microscope, strong light emission was observed at curvature region A of guard ring region 5 . That is, it was confirmed that the breakdown occurred at the curvature region A of the guard ring region 5 .

Referring to FIG. 11 , the relationship between the on-state current and the breakdown voltage of MOSFET 1 is explained below. When the curvature radius R of the curvature region A of the guard ring region 5 becomes smaller, the electric field tends to concentrate on the curvature region A, resulting in lowered breakdown voltage. The target specification of the breakdown voltage in MOSFET1 is, for example, 1200V. When the drift layer ratio is 3.3, the on-state current exhibits a high value of 13.6A, but the breakdown voltage is about 1100V, which does not satisfy the specification. The drift layer ratio that allows a breakdown voltage of not less than 1200V is considered to be 5 or more.

On the other hand, when the curvature radius R of the curvature region A of the guard ring region 5 becomes larger, electric field concentration is relieved, resulting in an increase in breakdown voltage. However, when the area of the curvature region A increases, the area of the element region IR decreases, and as a result, the on-state current flowing in the semiconductor element 7 becomes smaller. MOSFET 1 desirably has a high breakdown voltage as well as a high on-state current (ie, has the characteristics indicated on the upper right side in FIG. 11 ). For the on-resistance in MOSFET 1, the target specification is, for example, 12A. When the drift layer ratio is 8.3, the breakdown voltage is 1800V and the on-state current is 12.8A. When the drift layer ratio is 84.3, the breakdown voltage is high, that is, 1900V, but the on-state current is about 10A, which does not meet the specification. When the drift layer ratio exceeds 8.3, the breakdown voltage does not increase much, but the on-state current decreases rapidly. A drift layer ratio that allows an on-state current of not less than 12A is considered to be 10 or less. Therefore, it is considered that the drift layer ratio is not less than 5 and not more than 10 to achieve the specifications of both the on-state current and the breakdown voltage.

The embodiments and examples disclosed herein are illustrative and not restrictive in any respect. The scope of the present invention is defined by the terms of the claims, rather than the above-described embodiments, and is intended to embrace any modifications within the scope and meaning equivalent to the terms of the claims.

List of reference symbols

1: MOSFET; 2: JTE area; 2a: curvature area; 2b: linear area; 2c: inner periphery; 3: guard ring; 3a: curvature area; 3b: linear area; 5: guard ring area; 7: semiconductor element ;10: silicon carbide substrate; 10a: main surface; 11: n+ substrate; 12: drift region; 13: p body region; 14: n+ source region; 15: gate insulating film; 16: source electrode; 17: gate Electrode; 18: p+ region; 20: drain electrode; A: curvature region; B: linear region; IR: element region; OR: termination region.

Claims (8)

1. a sic semiconductor device, including: it is provided with the element region of semiconductor element；And there is the first conduction type And in plan view around the protection ring region of described element region,

Described semiconductor element includes the drift region with second conduction type different from described first conduction type,

Described protection ring region includes linear zone and is successively connected to the curvature district of described linear zone,

By by the radius of curvature of the inner peripheral portion in described curvature district divided by described drift region thickness obtain value be not less than 5 and It is not more than 10.

Sic semiconductor device the most according to claim 1, wherein

Described semiconductor element includes contacting described drift region and having the body district of described second conduction type, and

The thickness in described body district is more than the thickness of described protection ring region.

Sic semiconductor device the most according to claim 2, wherein said protection ring region includes contacting described body district also And there is the JTE district of described second conduction type.

Sic semiconductor device the most according to claim 3, wherein

Described semiconductor element includes contacting described body district and having the source region of described first conduction type, and contact is described The source electrode of source region, and

Described JTE district contacts described source electrode.

5., according to the sic semiconductor device described in any one in Claims 1-4, wherein said protection ring region includes not The protection ring contacted with described element region.

Sic semiconductor device the most according to claim 5, wherein

Multiple described protection ring is set, and

By by the radius of curvature of the inner peripheral portion in the curvature district of the inner side protection ring of multiple described protection rings divided by described drift The value that the described thickness in district obtains is not less than 5 and no more than 10.

7., according to the sic semiconductor device described in any one in Claims 1-4, also include that there is described first conduction Type and in plan view around the stop zone, field of described protection ring region.

Sic semiconductor device the most according to claim 7, the most in plan view, in the periphery of described protection ring region Any position in portion, the distance between described peripheral part and the inner peripheral portion of stop zone, described field of described protection ring region is all permanent Fixed.