CN104464823B - Storage arrangement and method for managing zone errors - Google Patents

Abstract

The application is related to storage arrangement and method for managing zone errors.Storage arrangement and method of the present invention description comprising memory die stacking and logic die.Described method and device, which is included, realizes that splitting the memory die again stacks and those method and devices by new partitioned storage in memory mapping.The stem portion for removing memory is allowed it is not used without influenceing the remainder of the storage arrangement if carrying out segmentation again with selected configuration.Also disclose extra means, system and method.

Description

Memory device and method for managing error areas

This case is a divisional application. The parent case of this case is the international application number PCT/US2010/021807, the application date is January 22, 2010, the application number is 201080005316.X after the PCT application entered the Chinese national phase, and the invention name is "memory for managing error areas Apparatus and method" invention patent application.

Related Application Cross Reference

This patent application claims the benefit of priority to US Application Serial No. 12/359,014, filed January 23, 2009, which is incorporated herein by reference.

technical field

Various embodiments described herein relate to devices, systems, and methods associated with semiconductor memory.

Background technique

Microprocessor technology has evolved at a faster rate than semiconductor memory technology. Consequently, there is often a performance mismatch between modern host processors and the semiconductor memory subsystems to which the processors are coupled to receive instructions and data. For example, it is estimated that some high-end servers idle three quarters of their clocks waiting for a response to a memory request.

Additionally, as the number of processor cores and threads continues to increase, software application and operating system technology evolutions have increased the need for higher density memory subsystems. However, state-of-the-art memory subsystems typically represent a trade-off between performance and density. The higher bandwidth can limit the number of memory cards or memory modules that can be connected in a system without exceeding the Joint Electron Device Engineering Council (JEDEC) electrical specifications.

Extensions to the JEDEC interface standards, such as Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM), have been proposed, but deficiencies can often be found with respect to future expected memory bandwidth and density. Drawbacks include lack of memory power optimization and uniqueness of the interface between the host processor and the memory subsystem. This latter shortcoming can lead to the need to redesign the interface as processor and/or memory technology changes.

Description of drawings

Figure 1 shows a block diagram of a memory system according to an embodiment of the invention.

2 shows a cutaway conceptual diagram of a stacked die 3D memory with logic dies according to an embodiment of the invention.

Figure 3 shows a block diagram of a memory vault controller and associated modules according to an embodiment of the invention.

Figure 4 shows a flowchart of a method of operating a memory device according to an embodiment of the invention.

FIG. 5 shows a flowchart of a method of fabricating a memory device according to an embodiment of the invention.

Figure 6 shows a block diagram of an information handling system according to an embodiment of the invention.

detailed description

In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which are shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made.

Figure 1 includes a block diagram of a memory device 100 according to various example embodiments of the invention. The memory device 100 operates to substantially simultaneously transfer multiple outgoing and/or Or incoming command stream, address stream and/or data stream. Increased memory system density, bandwidth, parallelism, and scalability can result.

The multi-die memory array embodiments aggregate control logic that in previous designs would normally be located on each individual memory array die. A subsection of a group of stacked die, referred to as a memory vault in this disclosure, is shown as example vault 110 in FIG. 1 and as example vault 230 in FIG. 2 . The memory banks shown in the illustrated example share common control logic. The memory bank architecture strategically partitions memory control logic to increase energy efficiency while providing finer granularity of powered-on memory banks. The illustrated embodiments also implement a standardized host processor to memory system interface. The standardized interface can reduce the number of redesign cycles as memory technology evolves.

2 is a cutaway conceptual diagram of a stacked die 3D memory array 200 stacked together with logic die 202 to form memory device 100 in accordance with various example embodiments. The memory device 100 incorporates one or more memory arrays 203 stacked resulting in a stacked die 3D memory array 200 . A plurality of memory arrays (eg, memory array 203) are fabricated onto each of the plurality of dies (eg, die 204). The memory array die are then stacked to form a stacked die 3D memory array 200 .

Each die in the stack is divided into a number of "tiles" (eg, tiles 205A, 205B, and 205C associated with stacked die 204). Each tile (eg, tile 205C) may include one or more memory arrays 203 . Memory array 203 is not limited to any particular memory technology and may include dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, and the like.

Stacked memory array tile set 208 may include individual tiles from each of the stacked dies (e.g., tiles 212B, 212C, and 212D, where the base tiles are hidden from view in FIG. 1 ). arrive). Power, address and/or data, and similar common signals may traverse stacked set of tiles 208 along a "Z" dimension 220 on conductive paths (eg, conductive paths 224) (eg, "through wafer interconnects" (TWIs)) . Note that TWI does not necessarily need to go all the way through a particular wafer or die.

The stacked die 3D memory array 200 in one configuration is partitioned into a collection of memory "banks" (eg, memory banks 230 ). Each memory bank includes a set of stacked tiles (eg, set of tiles 208 ), one tile from each of the plurality of stacked dies, and a set of TWIs to electrically interconnect the set of tiles 208 . Each tile in the pool includes one or more memory arrays (eg, memory array 240). Although partitioning into individual banks 230 is described, 3D memory array 200 may also be partitioned in a number of other ways. Other example partitions include partitioning by die, tile, and the like.

Set of memory vaults 102 (similar to memory vault 230 from FIG. 2 ) is illustrated in FIG. 1 in the context of within memory device 100 . The memory device 100 also includes a plurality of memory vault controllers (MVCs) 104 (eg, MVC 106). Each MVC is communicatively coupled to a corresponding memory repository (eg, memory repository 110 of collection 102 ) in a one-to-one relationship. Thus, each MVC is able to communicate with the corresponding memory vault independently of communications between other MVCs and their respective memory vaults.

The memory device 100 also includes a plurality of configurable serializable communication link interfaces (SCLI) 112 . The SCLI 112 is divided into a SCLI-out group 113 and a SCLI-in group 115 , where the "outgoing" and "incoming" directions are defined from the perspective of the processor 114 . Each SCLI of plurality of SCLIs 112 is capable of operating concurrently with the other SCLIs. SCLI 112 collectively communicatively couples multiple MVCs 104 to one or more host processors 114 . Memory device 100 presents a multi-link high-throughput interface to host processor 114 .

The memory device 100 may also include a switch 116 . In some embodiments, switch 116 may comprise a matrix switch, which may also be referred to as a cross-connect switch. Switch 116 is communicatively coupled to multiple SCLIs 112 and to multiple MVCs 104 . Switch 116 is capable of cross-connecting each SCLI to a selected MVC. Thus, host processor 114 may access multiple memory banks 102 across multiple SCLIs 112 in a substantially simultaneous manner. This architecture provides high processor-to-memory bandwidth for modern processor technologies, including multi-core technologies.

Memory device 100 may also include a memory organization control register 117 coupled to switch 116 . Memory fabric control registers 117 accept memory fabric configuration parameters from a configuration source and configure one or more components of memory device 100 to operate according to selectable modes. For example, each of the switch 116 and the plurality of memory banks 102 and the plurality of MVCs 104 can generally be configured to operate independently of each other in response to individual memory requests. This configuration can enhance memory system bandwidth due to the parallelism between SCLI 112 and memory vault 102 .

Alternatively, memory device 100 may be reconfigured via memory fabric control registers 117 to cause two or more subsets of multiple memory banks 102 and the corresponding MVC subsets to operate synchronously in response to a single request. The latter configuration can be used to access data words wider than the width of the data words associated with a single bank. This word is referred to herein as a wide data word. This technique reduces latency. Other configurations may be achieved by loading selected bit patterns into the memory fabric control register 117 .

In one example, outgoing SCLI 113 may include multiple outgoing differential pair serial paths (DPSPs) 128 . DPSP 128 is communicatively coupled to host processor 114 and can commonly communicate outgoing packets. Outgoing SCLI 113 may also include a deserializer 130 coupled to multiple outgoing DPSPs 128 . The outgoing SCLI may also include a demux 138 communicatively coupled to the deserializer 130 . In one embodiment, the configuration of the DSPS, deserializer, and demultiplexer facilitates efficient transfer of data packets or sub-packets. Similar to outgoing SLCI, in one embodiment incoming SCLI and a similar configuration of DSPS, serializers, and multiplexers facilitate efficient transfer of packets or sub-packets.

3 is a block diagram of an MVC (eg, MVC 106 ) and associated modules, according to various example embodiments. MVC 106 may include Programmable Library Control Logic (PVCL) component 310 . PVCL 310 interfaces MVC 106 to a corresponding memory repository (eg, memory repository 110). PVCL 310 generates one or more control signals and/or timing signals associated with corresponding memory vaults 110 .

PVCL 310 may be configured to adapt MVC 106 to a selected configuration or memory library 110 of a selected technology. Thus, for example, memory device 100 may initially be configured using currently available DDR2 DRAM. Memory device 100 can then be adapted to accommodate DDR3-based memory bank technology by reconfiguring PVCL 310 to include DDR3 bank control and timing logic.

The MVC 106 may also include a memory sequencer 314 communicatively coupled to the PVCL 310 . The memory sequencer 314 performs a memory technology dependent set of operations based on the technology used to implement the associated memory vault 110 . For example, memory sequencer 314 may perform command decode operations, memory address multiplexing operations, memory address demultiplexing operations, memory refresh operations, memory bank training operations, and/or Memory bank prefetch operations. In some embodiments, memory sequencer 314 may include a DRAM sequencer. In some embodiments, memory refresh operations may originate in a separate refresh controller (not shown).

Memory sequencer 314 may be configured to adapt memory device 100 to memory vault 110 of a selected configuration or technology. For example, memory sequencer 314 may be configured to operate synchronously with other memory sequencers associated with memory device 100 . This configuration may be used to deliver wide data words from multiple memory banks to a cache line (not shown) associated with host processor 114 in response to a single cache line request.

The MVC 106 may also include a write buffer 316 . Write buffer 316 may be coupled to PVCL 310 to buffer data arriving at MVC 106 from host processor 114 . The MVC 106 may further include a read buffer 317 . Read buffer 317 may be coupled to PVCL 310 to buffer data arriving at MVC 106 from corresponding memory vault 110 .

MVC 106 may also include an out-of-order request queue 318 . The out-of-order request queue 318 establishes an ordered sequence of read and/or write operations to the plurality of memory banks contained in the memory bank 110 . The ordered sequence is chosen to avoid sequential operations on any single memory bank to reduce bank conflicts and lower read-to-write turnaround time.

MVC 106 may also include a memory mapped logic (MML) component 324 . MML 324 manages several operations, such as TWI repair operations using TWI repair logic 328 or other repair operations. In one example, MML 324 tracks error data for portions of 3D memory array 200 . The use of error data is discussed in more detail below. MML324 can be used to track error rates for several different parts. In one example, error data is tracked for each die 204 . Other examples include tracking error data for each tile 205, each array 203, and so on.

In one example, the tracked portion is dynamic. For example, where die 204 has an error rate that exceeds a threshold, a portion of die 204 may be selected for tracking. In another example, where the error rate is below a threshold error rate for a portion (eg, a tile), MVEL may track the error rate only for the pool that includes that tile. In one example, the tracked error rate information for a portion of the 3D memory array 200 is used to adjust (eg, change) the refresh rate of the selected portion.

FIG. 3 shows an embodiment including a memory map 315 . Memory map 315 interacts with MML 324 , keeps track of various portions of 3D memory array 200 and stores properties (eg, error data) associated with the tracked portions. Examples include other grouping tracking error data for an individual die 204 , bank 230 , tile 205 , or number of memory cells within 3D memory array 200 . In one example, memory map 315 keeps track of this information for more than one section at a time. In one example, each MVC 106 includes a separate memory map 315, although the invention is not so limited. Other embodiments include a single memory map 315 or other numbers of memory maps 315 located on the logic chip 202 to serve the 3D memory array 200 .

Although error data is discussed as a property tracked and used by the memory device 100, the invention is not so limited. Other properties unique to each portion are also tracked in various embodiments. Other characteristics may include, but are not limited to, temperature, power down state, and refresh rate.

As discussed above, in one embodiment, the tracked error data includes error rates corresponding to individual portions of the 3D memory array 200 . Other error data, such as error types or accumulated errors, are also possible error data. Types of errors include errors that can be corrected using error correction code (ECC) and hard errors such as faulty through-die interconnects. In one embodiment, the error rate is compared to a threshold error rate. In one embodiment, a memory portion is deemed to require corrective action where a threshold error rate is exceeded. Corrective actions can include several methods, including implementing error correction algorithms or removing bad regions so they no longer operate. Corrective actions using re-partitioning of the 3D memory array 200 are discussed in more detail below.

In one example, the error data is collected once, and the corrective action is implemented as a static correction. For example, memory device 100 may be evaluated once during a power-on operation and error data for various portions of 3D memory array 200 collected once. A memory map is generated (eg, created) 315, and portions of memory having errors exceeding a threshold level are removed from operation. Next, MML 324 uses memory map 315 to re-partition 3D memory array 200 from a first partition state that existed before power-on to a second partition state that removes bad memory portions so that they are no longer operational.

In another example, error data is collected only once after manufacturing, and memory map 315 is generated to remove any defective memory portions due to manufacturing errors. Examples of manufacturing yield errors include faulty vias, TWIs, other photolithographic defects, and the like. Other errors may be due to variations in the silicon or processing that produces functional parts with higher than normal error rates. In some embodiments, after first correcting errors using ECC and then moving data to portions of 3D memory array 200 that are functioning with at least normal performance, the portions that are functioning with lower than normal performance are removed so that they no longer operate. After moving the data, portions of the 3D memory array 200 with unacceptable error rates are then removed from use in the memory map 315 and the 3D memory array 200 is repartitioned.

In one example, error data is collected dynamically during operation of memory device 100, and corrective actions are dynamically implemented in response to changing error data. Dynamically changing the conditions of the 3D memory array 200 may be for several reasons, including electromigration of conductors, thermal damage over time, and the like. In a dynamic embodiment, memory map 315 is updated and corrective actions are implemented by MML 324 as needed as the condition of individual memory portions changes. Similar to the embodiments described above, corrective actions include moving data, removing faulty memory portions, and repartitioning the 3D memory array 200 .

FIG. 4 illustrates a method of operating memory including dynamically repartitioned 3D memory array 200 . In operation 410, error data is collected from a number of different first partitions of a stack of memory dies. The first partition may correspond to some of the enumerated memory portions (eg, vault 110, tile 205, etc.), although the invention is not so limited. The error data may include merely indicating that the first partition is not functioning, or the error data may include an error rate for the first partition. As discussed above, there may also be other types of erroneous data.

In operation 420 , memory map 315 is generated (eg, created) within a locally attached logic die (eg, logic die 202 ) using the error data collected in operation 410 . In operation 430, the memory map 315 is altered during operation of the memory device 100 to repartition the stack of memory dies to form a number of second partitions in the event that the erroneous data exceeds the threshold.

Embodiments described above discuss removing non-functional partitions so that they are no longer operational. Other embodiments salvage the still functioning portion of the partition. In one embodiment, the still functional portions of the first partition are combined to form the second partition. For example, in the event of a TWI failure in memory vault 110, the lower portion of vault 110 may remain functional. Two or more lower portions of such libraries 110 can be combined and re-partitioned to serve as the entire library in a second partition. In this example, two or more memory sequencers 314 can be synchronized to operate as a single bank.

In one embodiment, 3D memory array 200 is fabricated with spare memory sections. Examples of spare memory portions include spare memory die 204, spare memory vault 110, spare memory tile 205, and the like. In one example, the spare memory area is split into spare areas in the first partition, and recorded as such in the memory map 315 . In the static repartitioned memory example, at power-up or after manufacturing, where the "primary" portion of the 3D memory array 200 (as opposed to the spare portion) is bad and that portion is removed so that it is no longer used, One or more spare memory portions are mapped for use in the restriping process. Likewise, in the dynamically repartitioned memory example, during memory operations, once a memory portion satisfies the eviction criteria (e.g., the error rate exceeds a threshold), an amount of spare memory portions necessary to make up the difference are mapped into use, and The 3D memory array 200 is repartitioned to include the spare area.

In one example, there may not be enough spare memory portions to restore 3D memory array 200 up to a certain memory capacity after re-partitioning. For example, 3D memory array 200 may end up short of one or more banks 110 . In other embodiments that do not have a spare memory portion, any repartitioning will result in a smaller memory capacity than was designed in manufacture.

Figure 5 illustrates a fabrication process for sorting memory after fabrication according to available bandwidth. In operation 510, a number of memory die stacks are formed, and in operation 520 logic dies are stacked with the memory die stacks. Each stack of memory dies is fabricated in a first partitioned structure. Each stack of memory dies is then evaluated in operation 530 by collecting (eg, acquiring, generating, etc.) error data from different memory portions of the stack of memory dies. In operation 540, each stack of memory dies is repartitioned to remove portions of the memory with erroneous data that do not meet the criteria from being operational. As discussed in the examples above, where a portion of the memory die stack is completely non-functional, the erroneous data may not meet the criteria. In other instances, the erroneous data may not meet the criteria where the error rate exceeds a threshold error rate for a portion of the memory die stack.

In operation 550, the stacks of memory die are sorted according to the available bandwidth determined by the remaining memory capacity of each of the memory die stacks. As discussed above, in an embodiment without a spare memory portion, removing a portion of the stack can result in the same read bandwidth, but slightly reduced write bandwidth. Even in embodiments with spare memory portions, the spare portion can be exceeded and the resulting stack can have reduced bandwidth.

Sorting memory die stacks according to available bandwidth is similar to sorting processors by demonstrated speed after fabrication. The memory die stack can then be matched to a computing system that only requires a certain sorted memory bandwidth. For example, a personal computer can be sold with a selected processor speed and a selected memory bandwidth. The resulting combination will be based on user-provided computing speed versus depending on both processor speed and memory bandwidth.

This approach makes manufacturing yield a non-issue for memory manufacturers. The memory device 100 as described in the embodiments above need not be perfect, and due to features such as the attached logic chip and memory map, a large percentage of the operating memory bandwidth is still available and can be sold as such to the end user. Having the memory map 315 stored locally within the logic chip 202 installed locally on the memory device 100 allows the memory device 100 to optimize memory operations independent of the processor 114 .

The apparatus and systems of various embodiments may be used in applications other than high-density multi-link, high-throughput semiconductor memory subsystems. Accordingly, the various embodiments of the invention are not to be so limited. The illustration of memory device 100 is intended to provide a general understanding of the structure of various embodiments. The illustrations are not intended to be a complete description of all elements and features of devices and systems that may utilize the structures described herein.

The novel devices and systems of the various embodiments may include devices for computers, communication and signal processing circuits, single or multi-processor modules, single or multiple embedded processors, multi-core processors, data switches, and other information handling systems electronic circuits in or incorporated into them.

Examples of such systems include, but are not limited to, televisions, cellular phones, personal data assistants (PDAs), personal computers (e.g., laptops, desktops, handhelds, tablets, etc.), workstations, Radios, video players, audio players (eg, MP3 (Motion Experts Group Audio Layer 3) players), vehicles, medical devices (eg, heart monitors, blood pressure monitors, etc.), set-top boxes, and other electronic systems.

A high level example of a personal computer is included in Figure 6 to demonstrate higher level device applications of the present invention. Figure 6 is a block diagram of an information handling system 600 incorporating at least one memory device 606, according to an embodiment of the invention.

In this example, information handling system 600 includes a data processing system that includes a system bus 602 to couple the various components of the system. System bus 602 provides communication links among the various components of information handling system 600 and may be implemented as a single bus, as a combination of buses, or in any other suitable manner.

Chip assembly 604 is coupled to system bus 602 . Chip assembly 504 may include any one circuit or an operationally compatible combination of several circuits. In one embodiment, chip assembly 604 includes a processor 608 or multiple processors, which may be of any type. As used herein, "processor" means any type of computing circuitry, such as, but not limited to, a microprocessor, microcontroller, graphics processor, digital signal processor (DSP), or any other type of processor or processing circuit. As used herein, a "processor" includes multiple processors or multiple processor cores.

In one embodiment, memory device 606 is included in chip assembly 604 . Those skilled in the art will recognize that various memory device configurations may be used in chip assembly 604 . A memory device (eg, DRAM) that is constantly refreshed during operation is described in the embodiments above. One example of a DRAM device includes a stacked memory chip 3D memory device with integrated logic chips as described in the embodiments above. Memory 606 may also include non-volatile memory (eg, flash memory).

Information handling system 600 may also include external memory 611, which in turn may include one or more memory elements suitable for a particular application, such as one or more hard drives 612 and/or handle removable media 613 (e.g., One or more drives of flash memory drives, compact discs (CDs), digital video discs (DVDs), and the like).

Information handling system 600 may also include a display device 609 (e.g., a monitor), additional peripheral components 610 (e.g., speakers, etc.), and a keyboard and/or controller 614, which may include a mouse, trackball, game controller, voice recognition device or any other device that permits a system user to enter information into and receive information from information handling system 600 .

While describing several embodiments of the invention, the above list is not intended to be exhaustive. Although specific embodiments have been illustrated and described herein, those skilled in the art will appreciate that any arrangement which is intended to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover any adaptations or variations of the present invention. It should be understood that the above description is intended to be illustrative rather than restrictive. Combinations of the above embodiments, and other embodiments, will become apparent to those of ordinary skill in the art upon reviewing the above description.

Claims (30)

1. A memory device comprising: a stack of singulated memory dies; and at least one logic die coupled to the stack of memory dies, the logic die including memory mapping logic configured to repartition the stack of memory dies, wherein the memory mapping logic is configured by configured to track error data corresponding to different portions of the partitioned stack of memory die, and the different portions to be tracked are adjustable depending on the error data corresponding to the different portions. 2. The memory device of claim 1, wherein the at least one logic die is stacked with the partitioned memory die. 3. The memory device of claim 1, wherein the stack of memory dies is partitioned into vertical memory banks. 4. The memory device of claim 3, wherein the memory bank further comprises a number of spare memory banks. 5. The memory device of claim 1, wherein the memory mapping logic is configured to use a memory map that occurs immediately when the memory device is powered on. 6. The memory device of claim 1, wherein the memory mapping logic uses a memory map that occurs shortly after fabrication of the memory device. 7. The memory device of claim 3, wherein the memory mapping logic is configured to combine portions of partially defective banks into a single partition. 8. A memory device comprising: memory die stacking; and a logic die coupled to the stack of memory dies, the logic die including memory mapping logic to take actions relative to the stack of memory dies based on tracked error data in different portions of the stack of memory dies corrective action; wherein the memory mapping logic is configured to track error data in the different portions, and wherein the different portions to be tracked are adjustable according to the tracked error data corresponding to the different portions. 9. The memory device of claim 8, wherein the logic die is configured to dynamically repartition the stack of memory dies to remove tracked erroneous data of the stack of memory dies having an error threshold that exceeds an error threshold part makes it no longer operational. 10. The memory device of claim 8, wherein the memory map is configured to simultaneously track erroneous data corresponding to multiple portions of the stack of memory dies. 11. The memory device of claim 8, wherein the tracked error data includes errors correctable using error correction code (ECC). 12. The memory device of claim 11 , wherein the logic die is configured to move data to another portion of the memory die stack if the error is correctable using error correction code (ECC) . 13. A memory device comprising: A memory die stack comprising: the principal parts; and at least one spare part; and a logic die coupled to the stack of memory dies, the logic die including memory mapped logic to respond relative to the memory die if an error rate in one of the plurality of principals exceeds a threshold chip stack to take corrective action; wherein the memory mapping logic is configured to track error rates in different portions of the memory die stack, and wherein the different portions to be tracked are adjustable according to the tracked error rates corresponding to the different portions of. 14. The memory device of claim 13, wherein the corrective action includes restaging the stack of memory dies. 15. The memory device of claim 13, wherein the number of major portions includes a number of memory banks. 16. The memory device of claim 15, wherein the spare portion comprises a memory vault. 17. The memory device of claim 13, wherein the number of prime portions comprises a number of memory tiles. 18. A method of operating a memory device comprising: forming a memory die stack; stacking corresponding logic dies with the stack of memory dies; and A memory map is formed to collect data from different memory portions within each stack of memory dies, wherein the memory map is configured to re-partition the dynamically sized portions of the memory die stacks corresponding to the data. 19. The method of claim 18, wherein forming the memory map to collect data comprises forming a memory map to collect erroneous data. 20. The method of claim 18, wherein forming the memory map to collect data comprises forming a memory map to track errors correctable using error correction code (ECC). 21. The method of claim 18 , wherein forming the memory map to collect data comprises forming a memory map to correct error rate data and repartitioning the dynamically sized memory map when the error rate data exceeds an error rate threshold. part. 22. The method of claim 20, wherein forming the memory map to collect data comprises forming a memory map configured to move data to the memory if the error is correctable using error correction code (ECC) Another part of the die stack. 23. A method of operating a memory device comprising: forming a memory die stack; stacking corresponding logic dies with the stack of memory dies; and collecting data from a number of different memory portions within the stack of memory dies; and A dynamically sized portion within the stack of memory dies is partitioned according to data that does not meet criteria. 24. The method of claim 23 , wherein partitioning the memory stack comprises repartitioning portions of a first memory vault in the stack of memory dies below a defective through-wafer interconnect (TWI) into at least A second partition. 25. The method of claim 23, wherein partitioning the stack of memory dies comprises restaging together portions of partially defective first partitions into at least one second partition. 26. The method of claim 23, wherein partitioning the stack of memory dies comprises partitioning the stack of memory dies to remove defective memory tiles in the memory stack from being no longer operational. 27. The method of claim 23, wherein collecting data from the number of different memory portions comprises collecting data from a number of memory banks in the stack of memory dies. 28. The method of claim 23, further comprising forming a spare portion within the stack of memory dies. 29. The method of claim 28, wherein forming the spare portion includes forming a spare memory bank. 30. The method of claim 28, wherein forming the spare portion comprises forming a spare memory die.