CN103985748B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The application discloses a semiconductor arrangement and a method of manufacturing the same. An example arrangement may include: a substrate; a back gate formed on the substrate; a fin formed on one side of the back gate; and a back gate dielectric layer sandwiched between the back gate and the fin.

Description

Semiconductor device and manufacturing method thereof

technical field

The present disclosure relates to the field of semiconductors, and more particularly, to a semiconductor arrangement including a fin structure and a method of manufacturing the same.

Background technique

In order to meet the challenges brought about by the continuous miniaturization of semiconductor devices, such as short channel effects, a variety of high-performance devices have been proposed, such as UTBB (Ultra Thin Buried Oxide and Body) devices and FinFET (Fin Field Effect transistors), etc.

UTBB devices utilize ET-SOI (Extremely Thin-Semiconductor-On-Insulator) substrates. Due to the existence of buried oxide (BOX) in the SOI substrate, the short channel effect can be suppressed. In addition, a back gate electrode can be set on the backside of the SOI substrate to control the threshold voltage of the device, thereby effectively reducing the power consumption of the device (for example, by raising the threshold voltage when the device is turned off, thereby reducing the leakage current). However, ET-SOI is extremely expensive and suffers from self-heating issues. Moreover, with the continuous miniaturization of devices, ET-SOI is becoming more and more difficult to manufacture.

A FinFET is a three-dimensional device, including fins (fins) vertically formed on a substrate, and conductive channels of the device can be formed in the fins. Since the height of the fin can be increased without increasing its footprint, the current drive capability per unit footprint can be increased. However, FinFETs do not effectively control their threshold voltage. Also, as devices continue to be miniaturized, the fins become thinner, making them prone to collapse during fabrication.

Contents of the invention

It is an object of the present disclosure, at least in part, to provide a semiconductor arrangement and method of manufacturing the same.

According to an aspect of the present disclosure, there is provided a semiconductor arrangement including: a substrate; a back gate formed on the substrate; a fin formed on one side of the back gate; and a back gate sandwiched between the back gate and the fin medium layer.

According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, comprising: forming a back gate groove in a substrate; forming a back gate dielectric layer on the sidewall of the back gate groove; filling the back gate groove with a conductive material , forming a back gate; patterning the substrate to form fins adjacent to the back gate dielectric layer on one side of the back gate.

According to an exemplary embodiment of the present disclosure, a back gate is disposed adjacent to the fin. Based on this structure, a variety of devices can be fabricated, such as Fin Field Effect Transistors (FinFETs). In such a device, on the one hand, the threshold voltage of the device can be effectively controlled through the back gate. On the other hand, the back gate can act as a support structure for the fins, helping to improve the reliability of the structure.

Description of drawings

The above and other objects, features and advantages of the present disclosure will be more clearly described through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

FIG. 1 is a perspective view illustrating a semiconductor arrangement according to one embodiment of the present disclosure;

2 is a perspective view illustrating a semiconductor arrangement according to another embodiment of the present disclosure;

3 is a perspective view showing the semiconductor arrangement shown in FIG. 2 cut along the line A-A';

4-23 are schematic diagrams illustrating various stages in the flow of manufacturing a semiconductor arrangement according to another embodiment of the present disclosure.

detailed description

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions/layers with different shapes, sizes, and relative positions can be additionally designed as needed.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be intervening layers/elements in between. element. Additionally, if a layer/element is "on" another layer/element in one orientation, the layer/element can be located "below" the other layer/element when the orientation is reversed.

According to an embodiment of the present disclosure, a semiconductor arrangement is provided. The semiconductor arrangement may include a fin and a back gate adjacently disposed on a substrate. The fin is separated from the back gate by a back gate dielectric, so that the fin can be controlled by applying a bias to the back gate. According to an example, the fins may be formed from a portion of the substrate by patterning the substrate. Alternatively, the fins can be formed by patterning an epitaxial layer grown on the substrate.

According to an embodiment of the present disclosure, the back gate may be in electrical contact with the substrate. In this way, a bias can be applied to the back gate through the substrate. In order to improve bias application efficiency, a well region may be formed in the substrate such that the back gate is in electrical contact with the well region. A bias can be applied to the back gate through an electrical contact to the well region. In addition, in order to further reduce the contact resistance between the back gate and the well region, a contact region may be formed in the well region at a position corresponding to the back gate. The doping concentration of such a contact region may be higher than that of the rest of the well region.

According to the embodiments of the present disclosure, various semiconductor devices, such as FinFETs, can be formed based on the above structure. Although this structure includes a back gate, it can be fin-shaped as a whole, so that various existing FinFET manufacturing processes and manufacturing equipment are still applicable. Therefore, the technology of the present disclosure can be applied without redevelopment of additional manufacturing processes and manufacturing equipment.

Such a FinFET may, for example, include a gate stack formed on a substrate intersecting the fin (and the back gate). To electrically isolate the gate stack from the substrate, the FinFET may include an isolation layer formed on the substrate exposing a portion of the middle fin (which serves as the actual fin of the FinFET) on which the gate stack is formed. Since the bottom of the fin is blocked by the isolation layer, it is difficult for the gate stack to effectively control the bottom of the fin, which may cause leakage current between the source and the drain via the bottom of the fin. To suppress this leakage current, the FinFET may include a punch through stopper (PTS) under the exposed portion of the fin. For example, the PTS may be located substantially in the portion of the fin that is obscured by the isolation layer.

The gate stack defines a channel region in the fin (corresponding to the portion of the fin that intersects the gate stack), and thus defines source/drain regions (corresponding to portions of the fin on opposite sides of the channel region). In order to avoid interference between the gate stack and the back gate, a dielectric layer may be formed between them and thus electrically isolated.

According to some examples, to enhance device performance, strained source/drain techniques may be applied. For example, the source/drain regions may include a semiconductor layer of a different material than the fins so that stress may be applied to the channel region. For example, for p-type devices, compressive stress can be applied; for n-type devices, tensile stress can be applied.

According to some examples of the present disclosure, the aforementioned adjacent arrangement of fins and back gates may be fabricated as follows. For example, a back gate trench may be formed in the substrate by filling the back gate trench with a conductive material such as metal, doped polysilicon, etc. to form the back gate. In addition, before filling the back gate trench, a back gate dielectric layer may be formed on the sidewall of the back gate trench. According to an advantageous example, such a back gate dielectric layer can be fabricated according to a spacer forming process, thereby simplifying the process. Next, the substrate may be patterned to form fins adjacent to the back gate dielectric layer. For example, the substrate may be patterned such that a (fin-shaped) portion of the substrate is left on one side wall of the back gate groove (more specifically, the back gate dielectric layer formed on the side wall of the back gate groove) .

In order to facilitate patterning of the back gate trenches and fins, according to an advantageous example, a patterning auxiliary layer may be formed on the substrate. The patterning auxiliary layer may be patterned to have an opening corresponding to the back gate groove, and a pattern transfer layer may be formed on a sidewall thereof opposite to the opening. In this way, the patterning auxiliary layer and the pattern transfer layer can be used as a mask to pattern the back gate groove (hereinafter referred to as "first patterning"); in addition, the pattern transfer layer can be used as a mask to pattern the fins (hereinafter referred to as "second patterning"). composition").

In this way, the fin is formed by patterning twice: in the first pattern, one side of the fin is formed; and in the second pattern, the other side of the fin is formed. In the first configuration, the fins are still attached to the body of the substrate and thus supported. Also, in the second configuration, the fin is connected to the back gate and thus supported. As a result, collapse during fin manufacturing can be prevented, and thus thinner fins can be manufactured with higher yield.

Before the second patterning, a dielectric layer may be formed in the back gate trench to cover the back gate. On the one hand, the dielectric layer can electrically isolate the back gate (for example, from the gate stack), and on the other hand, it can prevent the second pattern from affecting the back gate.

In addition, in order to facilitate patterning, according to an advantageous example, the pattern transfer layer may be formed on the sidewall of the patterning auxiliary layer according to a sidewall forming process. Since the sidewall forming process does not require a mask, the number of masks used in the process can be reduced. In order to form the pattern transfer layer only on one side of the patterning auxiliary layer, a preliminary pattern transfer layer may be formed on both sides thereof according to a sidewall process first. Then, for example, by angular ion implantation, the properties of the preliminary pattern transfer layer on one side are changed, so that the preliminary pattern transfer layer on this side can be selectively removed relative to the preliminary pattern transfer layer on the other side. As a result, a preliminary pattern transfer layer is left on the other side, which constitutes the pattern transfer layer used to form the fins. According to an advantageous example, a sidewall forming auxiliary layer may also be formed on the patterning auxiliary layer. For example, the sidewall forming auxiliary layer may include the same material (eg, nitride) as the pattern transfer layer. When oblique ion implantation is performed, ions may also enter into the sidewall forming auxiliary layer and thus change its properties. In this way, when the preliminary pattern transfer layer on one side is selectively removed with respect to the preliminary pattern transfer layer on the other side, the sidewall formation auxiliary layer can also be removed.

According to an example, the substrate may include Si, Ge, SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb, and the patterning assistance layer may include amorphous silicon. In this case, in order to avoid unnecessary etching of the patterning auxiliary layer during patterning of the back gate trenches, a protective layer may be formed on the top surface of the patterning auxiliary layer. In addition, before forming the patterning auxiliary layer, a stopper layer may also be formed on the substrate. Patterning of the patterning assist layer (to form openings therein) can be stopped at the stop layer. For example, the protection layer may include oxide (eg, silicon oxide), the pattern transfer layer may include nitride, and the stop layer may include oxide (eg, silicon oxide).

Additionally, according to some examples of the present disclosure, after fabricating the adjacent arrangement of fins and back gates as described above, a FinFET may be fabricated as follows. For example, an isolation layer exposing a portion of the fin may be formed on the substrate on which the fin and the back gate are formed. A gate stack intersecting the fin (and back gate) can then be formed on the isolation layer.

In order to form the above-mentioned PTS, ion implantation may be performed after forming the isolation layer and before forming the gate stack. Due to the form factor of the fin and the various dielectric layers (eg, pattern transfer layer, etc.) present on top of the fin, the PTS can be formed substantially in the portion of the fin that is obscured by the isolation layer.

The disclosure can be presented in various forms, some examples of which are described below.

FIG. 1 is a perspective view showing a semiconductor arrangement according to one embodiment of the present disclosure. As shown in FIG. 1, the semiconductor device includes a substrate 100, such as a bulk semiconductor substrate such as Si, Ge, etc., a compound semiconductor substrate such as SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb, etc., semiconductor-on-insulator substrate (SOI), etc. For the convenience of description, a bulk silicon substrate and a silicon-based material are used as examples for description below.

The semiconductor arrangement also includes a combined arrangement of fins and back gates formed on the substrate. Specifically, the combined arrangement may include adjacently arranged fins 104 and back gates 120 formed on the substrate. The width of the fin 104 is, for example, about 3-28 nm, and is separated from the back gate 120 by the back gate dielectric layer 116 . The back gate dielectric layer 116 may include various suitable dielectric materials, such as oxide (eg, silicon oxide), and its equivalent thickness (dimension in the horizontal direction in the drawing) is, for example, about 10-40 nm. The back gate 120 may comprise various suitable conductive materials, such as doped polysilicon, and its width (dimension in the horizontal direction in the drawing) is, for example, about 5-30 nm. The back gate 120 may be in electrical contact with the substrate 100 so that a bias may be applied to the back gate 120 through the substrate 100 . To this end, a well region 100 - 1 may be included in the substrate 100 to enhance electrical contact with the back gate 120 .

In the example of FIG. 1 , the fins 104 are integral with, and formed from a portion of, the substrate 100 . It should be noted here that although the well region 100 - 1 is shown in FIG. 1 as also entering into the fin 104 , the present disclosure is not limited thereto. For example, well region 100 - 1 may be located in the portion of the substrate below fin 104 without entering into fin 104 (in particular, in the case of forming punch-through barriers at the bottom of fin 104 , as described below).

Also shown in FIG. 1 is a dielectric layer 124 on top of the back gate 120 . Dielectric layer 124 may include, for example, nitride (eg, silicon nitride). In addition, FIG. 1 also shows a dielectric layer disposed on the side of the back gate 120 opposite to the fin 104 . According to an example of the present disclosure, the dielectric layer may be formed in the same manufacturing step as the back gate dielectric layer 116 and include the same material (thus, for convenience, when referring to the dielectric layer hereinafter, it is sometimes also referred to as a back gate medium layer). The dielectric layer, as well as the dielectric layer 124, may electrically isolate the back gate 120 from the remaining components (eg, gate stack) formed on the front side (upper surface in FIG. 1 ) of the substrate.

2 is a perspective view showing a semiconductor arrangement according to another embodiment of the present disclosure, and FIG. 3 is a perspective view showing the semiconductor arrangement shown in FIG. 2 cut along line A-A'. The semiconductor arrangement shown in FIGS. 2 and 3 also includes a substrate 200 and a combined arrangement of fins and back gates formed on the substrate 200 . Similar to the embodiment of FIG. 1 , the combined arrangement may include adjacently disposed fins 204 and back gates 220 on the substrate. The fin 204 is separated from the back gate 220 by the back gate dielectric layer 216 . In order to enhance electrical contact between the back gate 220 and the base substrate 200, the base substrate 200 may include a well region 200-1 therein. For the structural and material parameters of these features, see the description above in connection with FIG. 1 .

Additionally, the semiconductor arrangement includes an isolation layer 202 formed on the substrate 200 and a gate stack formed on the isolation layer 202 to intersect the combined arrangement of fins and back gates. For example, isolation layer 202 may include oxide. The gate stack may include a gate dielectric layer 238 and a gate conductor layer 240 . For example, the gate dielectric layer 238 may include a high-K gate dielectric such as HfO ₂ with a thickness of 1-5 nm; the gate conductor layer 240 may include a metal gate conductor. In addition, the gate dielectric layer 238 may also include a thin layer of oxide (the high-K gate dielectric is formed on the oxide), for example, with a thickness of 0.3-1.2 nm. Between the gate dielectric layer 238 and the gate conductor 240, a work function adjustment layer (not shown in the figure) may also be formed. In addition, gate spacers 230 are formed on both sides of the gate stack. For example, the gate spacer 230 may include nitride with a thickness of about 5-20 nm. The back gate 220 is isolated from the gate stack by a dielectric layer 224 on its top surface and a back gate dielectric layer on one side.

Due to the existence of the gate stack, a channel region (corresponding to the portion where the fin intersects the gate stack) and a source/drain region (corresponding to the portion of the fin located on opposite sides of the channel region) are defined in the fin. In the semiconductor arrangement shown in FIG. 2, in the source/drain regions, a semiconductor layer 232 is also grown and formed on the surface of the fin. The semiconductor layer 232 may comprise a different material than the fins 204 so as to be able to apply stress to the fins 204 , in particular the channel region therein. For example, in the case where the fin 204 includes Si, for an n-type device, the semiconductor layer 232 may include Si:C (the atomic percentage of C is, for example, about 0.2-2%) to apply tensile stress; for a p-type device, the semiconductor layer 232 may include 232 may include SiGe (eg, about 15-75 atomic percent Ge) to apply compressive stress. In addition, the existence of the semiconductor layer 232 also widens the source/drain region, thereby facilitating the subsequent manufacture of the contact portion with the source/drain region.

As shown in FIG. 3 , the gate stack intersects the side of the fin 204 (opposite the back gate 220 ). Specifically, the gate dielectric layer 238 is in contact with the side surface of the fin 204 , so that the gate conductor layer 240 can control the formation of a conductive channel on the side surface of the fin 204 through the gate dielectric layer 238 .

In the example shown in FIGS. 2 and 3 , some layer structures on top of the fin 204 are also shown. These layer structures may, for example, remain during the manufacturing process of the semiconductor device and have no substantial influence on the structure and operation of the semiconductor device. According to some examples of the present disclosure, these residual layer structures may also be removed.

4-23 are schematic diagrams illustrating various stages in the flow of manufacturing a semiconductor arrangement according to another embodiment of the present disclosure.

As shown in FIG. 4, a substrate 1000, such as a bulk silicon substrate, is provided. In the substrate 1000, a well region 1000-1 is formed, for example, by ion implantation. For example, for a p-type device, an n-type well region can be formed; and for an n-type device, a p-type well region can be formed. For example, the n-type well region can be formed by implanting n-type impurities such as P or As into the substrate 1000 , and the p-type well region can be formed by implanting p-type impurities such as B into the substrate 1000 . Annealing can also be performed after implantation, if desired. Those skilled in the art can think of multiple ways to form the n-type well and the p-type well, which will not be repeated here.

A stop layer 1006 , a patterning auxiliary layer 1008 , a protective layer 1048 and a spacer forming auxiliary layer 1010 may be sequentially formed on the substrate 1000 . For example, the stop layer 1006 can protect oxide (such as silicon oxide) with a thickness of about 5-25 nm; the patterning auxiliary layer 1008 can include amorphous silicon with a thickness of about 50-200 nm; ) with a thickness of about 20-50 nm; the sidewall forming auxiliary layer 1010 may include nitride (such as silicon nitride) with a thickness of about 5-15 nm. The choice of materials for these layers is primarily to provide etch selectivity during subsequent processing. It will be appreciated by those skilled in the art that these layers may comprise other suitable materials, and that some of these layers may be omitted in some cases.

Next, a photoresist 1012 may be formed on the sidewall forming auxiliary layer 1010 . The photoresist 1012 is patterned, for example by photolithography, to form openings therein corresponding to the back gates to be formed. The width D1 of the opening may be, for example, about 15-100 nm.

Next, as shown in FIG. 5, the photoresist 1012 can be used as a mask to sequentially etch the sidewall formation auxiliary layer 1010, the protective layer 1048, and the patterning auxiliary layer 1008, such as reactive ion etching (RIE), so that Openings are formed in the wall formation auxiliary layer 1010 , the protective layer 1048 and the patterning auxiliary layer 1008 . Etching may be stopped at the stop layer 1006 . Of course, even this stop layer 1006 can be removed if there is sufficient etch selectivity between the patterning aid layer 1008 and the underlying substrate 1000 . Afterwards, photoresist 1012 may be removed.

Then, a pattern transfer layer may be formed on one side wall of the patterning auxiliary layer 1008 (opposite to the opening). According to an example of the present disclosure, such a pattern transfer layer may be formed as follows. Specifically, as shown in FIG. 6, a layer of nitride can be deposited on the surface of the structure shown in FIG. A preliminary pattern transfer layer 1014 in the form of a sidewall is formed on the sidewalls on both sides of the layer 1008 . The thickness of the deposited nitride layer may be about 3-28 nm (essentially determining the width of the subsequently formed fin). Such deposition can be performed, for example, by atomic layer deposition (ALD). Those skilled in the art know many ways to form such sidewalls, which will not be repeated here. Next, as shown by the arrow in FIG. 6, oblique ion implantation can be performed to change the preliminary pattern transfer layer (and the side above the auxiliary patterning layer 1008) on the sidewall of the auxiliary patterning layer 1008 (left side in the figure). The properties of the wall forming auxiliary layer 1010) (for example, damage caused therein due to ion implantation). Then, the preliminary pattern transfer layer (on the left side) as modified by RIE (and the sidewall forming auxiliary layer 1010 on the top) can be selectively removed relative to the unmodified other side (right side in the figure) preliminary pattern transfer layer. ), so as to obtain the pattern transfer layer 1014 on the other side (the right side in the figure).

Next, as shown in FIG. 7 , the patterning auxiliary layer 1008 and the pattern transfer layer 1014 can be used as a mask to pattern the substrate 1000 to form a back gate groove BG therein. Here, RIE may be performed on the stop layer 1006 and the substrate 1000 in sequence to form the back gate groove BG. These RIEs do not affect the patterning aid layer 1008 due to the presence of the protective layer 1048 . Of course, if there is sufficient etching selectivity between the material of the patterning auxiliary layer 1008 and the materials of the stop layer 1006 and the substrate 1000 , even the protection layer 1048 can be removed.

According to an advantageous embodiment, the back gate groove BG may enter into the well region 1000-1. For example, as shown in FIG. 7 , the bottom surface of the back gate groove BG is recessed by a depth D2 compared to the top surface of the well region 1000 - 1 or the bottom of the finally formed FET channel. D2 may be in the range of about 10-30 nm.

Subsequently, as shown in FIG. 8 , a back gate dielectric layer 1016 may be formed on the sidewall of the back gate groove BG. The back gate dielectric layer 1016 may include any suitable dielectric material, such as oxide or high-K dielectric material such as HfO ₂ . Here, the back gate dielectric layer 1016 can be fabricated according to the sidewall forming process. For example, the spacer can be formed by thermally oxidizing the surface of the structure shown in FIG. form of back gate dielectric layer.

Here, in order to reduce the contact resistance between the back gate to be formed and the substrate, as shown by the arrow in FIG. -1) The contact region 1018 is formed. The doping type of the ion implantation is the same as that of the well region, so that the doping concentration of the contact region 1018 (for example, 1E18-1E21 cm ⁻³ ) is higher than that of the rest of the well region 1000-1. Due to the presence of D2 (see FIG. 7 ), ion-implanted dopants can be prevented from entering the subsequently formed fins.

Then, as shown in FIG. 9 , a conductive material may be filled in the back gate groove BG to form a back gate 1020 . The back gate 1020 may comprise a doped (and thus conductive) semiconductor material such as polysilicon, the polarity of the doping (p-type or n-type) may be used to adjust the threshold voltage of the device, and the doping concentration may be about 1E18-1E21 cm ^-3 . Filling can be done, for example, by depositing and then etching back conductive material. Alternatively, the back gate 1020 may include a metal such as TiN, W, etc. or a combination thereof. According to an advantageous example, the top surface of the back gate 1020 may be substantially level with or (slightly) higher than the top surface of the substrate 1000 .

After forming the back gate as described above, the substrate 1000 may be patterned next to form fins.

In this embodiment, the gate stack intersecting the fin will then be formed to fabricate the FinFET. In order to avoid interference between the back gate 1020 and the gate stack, as shown in FIG. 10 , a dielectric layer 1024 is further filled in the back gate groove BG to cover the back gate 1020 . For example, dielectric layer 1024 may include nitride and may be formed by depositing an oxide followed by etching back. In addition, according to an advantageous example, before filling the dielectric layer 1024, the portion of the back gate dielectric layer 1016 exposed by the back gate 1020 can be selectively removed (in this example, both the protective layer 1048 and the back gate dielectric layer 1016 include oxide, Therefore, it can also be selectively removed), so that the dielectric layer 1024 completely covers the back gate stack (the back gate 1020 and the back gate dielectric layer 1016 ), so as to prevent it from being affected in subsequent processing.

Next, as shown in FIG. 11 , the patterning auxiliary layer 1008 may be removed by selective etching, such as wet etching by TMAH solution, leaving the pattern transfer layer 1014 . Then, the pattern transfer layer 1014 can be used as a mask to further selectively etch the RIE stop layer 1006 and the substrate 1000 . Thus, as shown in FIG. 12 , a fin-shaped substrate portion 1004 is left on the back gate 1020 side (left side in the figure), which corresponds to the shape of the pattern transfer layer 1014 .

It should be noted here that although the bottom of the fin 1004 is shown to be substantially level with the bottom of the back gate 1020 in FIG. 12 , the present disclosure is not limited thereto. According to an example of the present disclosure, in order for the back gate 1020 to effectively control the fin 1004 , the extending range of the fin 1004 in the vertical direction preferably does not exceed the extending range of the back gate 1020 .

In this way, a combined arrangement of fins and back gates according to this embodiment is obtained. As shown in FIG. 12 , the combined arrangement includes a back gate 1020 and a fin 1004 located on one side of the back gate 1020 (left side in the figure), and a back gate dielectric layer 1016 is sandwiched between the back gate 1020 and the fin 1004 . A dielectric layer 1024 is disposed on the top surface of the back gate 1020 , and a back gate dielectric layer 1016 is also covered on the other side (the right side in the figure).

In the combined arrangement of Figure 12, the residues of the pattern transfer layer 1014 and the stop layer 1006 are also shown. These residues have no substantial impact on subsequent processes, so they can be ignored here to simplify the process. Of course, they can be removed as desired.

After the combined arrangement of the fin and the back gate is obtained through the above process, various devices can be manufactured based on the combined arrangement. It should be noted here that in the example shown in FIG. 12, three combination settings are formed together. But the present disclosure is not limited thereto. For example, more or fewer combined arrangements can be formed as desired. In addition, the layout of the resulting combined arrangement is not necessarily a parallel arrangement as shown.

In the following, an example method flow for fabricating a FinFET will be described.

To fabricate FinFETs, an isolation layer may be formed on the substrate 1000 . For example, as shown in FIG. 13 , a dielectric layer 1002 (eg, may include oxide) can be formed on the substrate, eg, by deposition, and then the deposited dielectric layer is etched back to form the isolation layer. Typically, a deposited dielectric layer can completely cover the combined arrangement, and the deposited dielectric can be planarized, such as chemical mechanical polishing (CMP), prior to etch back. According to a preferred example, the deposited dielectric layer can be planarized by sputtering. For example, sputtering can use plasmas such as Ar or N plasmas.

In the case of forming well region 1000-1 in substrate 1000, the top surface of the well region may not be lower than the top surface of isolation layer 1002 (see FIG. 14). For example, the top surface of the isolation layer 1002 may slightly expose the well region, that is, the top surface of the isolation layer 1002 is slightly lower than the top surface of the well region 1000-1 (the height difference between them is not shown in the figure).

To improve device performance, especially reduce source-drain leakage, according to an example of the present disclosure, as shown by the arrow in FIG. 14 , a punch-through stopper (PTS) 1046 may be formed by ion implantation. For example, for n-type devices, p-type impurities such as B, BF ₂ or In can be implanted; for p-type devices, n-type impurities can be implanted, such as As or P. Ions can be implanted perpendicular to the substrate surface. Control the parameters of the ion implantation, so that the PTS is formed in the part of the fin 1004 located below the surface of the isolation layer 1006, and has a desired doping concentration, for example, about 5E17-2E19 cm ^-3 , and the doping concentration should be higher than that of the well in the substrate The doping concentration of region 1000-1. It should be noted that the steep doping profile in the depth direction is favored due to the form factor (elongated shape) of the combined fin and back gate arrangement and the respective dielectric layers present on top of it. Anneals such as spike anneals, laser anneals, and/or rapid anneals may be performed to activate the implanted dopants. This PTS helps reduce source-drain leakage.

Next, a gate stack intersecting the combined arrangement (especially the fins therein) may be formed on the isolation layer 1002 . For example, this can be done as follows. Specifically, as shown in FIG. 15 , for example, a gate dielectric layer 1026 is formed by deposition. For example, the gate dielectric layer 1026 may include oxide with a thickness of about 0.8-1.5 nm. In the example shown in FIG. 15 , only the Π-shaped gate dielectric layer 1026 is shown. However, the gate dielectric layer 1026 may also include a portion extending on the top surface of the isolation layer 1002 . A gate conductor layer 1028 is then formed, for example by deposition. For example, the gate conductor layer 1028 may include polysilicon. The gate conductor layer 1028 may fill gaps between combined arrangements and may be subjected to a planarization process such as CMP.

As shown in FIG. 16 (FIG. 16(b) shows a cross-sectional view along line BB' in FIG. 16(a)), the gate conductor layer 1028 is patterned. In the example of FIG. 16, the gate conductor layer 1028 is patterned into stripes intersecting the fins. According to another embodiment, the patterned gate conductor layer 1028 can also be used as a mask to further pattern the gate dielectric layer 1026 .

After the patterned gate conductor is formed, for example, the gate conductor can be used as a mask to perform halo implantation and extension implantation.

Next, as shown in Figure 17 (Figure 17(b) shows a cross-sectional view along line C1C1' in Figure 17(a), and Figure 17(c) shows a cross-sectional view along line C2C2' in Figure 17(a) ), a gate spacer 1030 may be formed on the sidewall of the gate conductor layer 1028 . For example, the gate spacer 1030 can be formed by depositing a nitride (such as silicon nitride) with a thickness of about 5-20 nm, and then performing RIE on the nitride. Here, the amount of RIE can be controlled when forming the gate spacer, so that the gate spacer 1030 is substantially not formed on the combined sidewalls. Those skilled in the art know many ways to form such sidewalls, which will not be repeated here.

After the spacer is formed, the gate conductor and the sidewall can be used as a mask to perform source/drain (S/D) implantation. Subsequently, the implanted ions can be activated by annealing to form source/drain regions to obtain a FinFET.

To improve device performance, according to an example of the present disclosure, strained source/drain technology can be utilized. Specifically, Fig. 18 (Fig. 18(b) shows a sectional view along the C1C1' line in Fig. 18(a), and Fig. 18(c) shows a sectional view along the C2C2' line in Fig. 18(a) ), the gate dielectric layer 1026 exposed by the gate stack can be removed (if the gate dielectric layer 1026 is also patterned during the patterning process of the above gate stack, this step can be omitted), thereby exposing a part of the fin 1004 (corresponding in the source/drain region). The semiconductor layer 1032 may be formed on the surface of the exposed fin portion by epitaxy. According to an embodiment of the present disclosure, in-situ doping can be performed on the semiconductor layer 1032 while growing it. For example, for n-type devices, n-type in-situ doping can be performed; for p-type devices, p-type in-situ doping can be performed. Additionally, to further enhance performance, the semiconductor layer 1032 may comprise a different material than the fin 1004 so that stress can be applied to the fin 1004 (in which the channel region of the device will be formed). For example, in the case where the fin 1004 includes Si, for an n-type device, the semiconductor layer 1032 may include Si:C (the atomic percentage of C is, for example, about 0.2-2%) to apply tensile stress; for a p-type device, the semiconductor layer 1032 may include 1014 may include SiGe (eg, about 15-75 atomic percent Ge) to apply compressive stress. On the other hand, the grown semiconductor layer 1032 is laterally widened to some extent, thereby facilitating the subsequent formation of contacts to the source/drain regions.

In case the gate conductor layer 1028 comprises polysilicon, the growth of the semiconductor layer 1032 may also occur on the top surface of the sacrificial gate conductor layer 1028 . This is not shown in the drawings.

In the above-described embodiments, the gate stack is formed directly after forming the combined arrangement of the fin and the back gate. The present disclosure is not limited thereto. For example, a replacement gate process is also applicable to the present disclosure.

According to another embodiment of the present disclosure, the gate dielectric layer 1026 and the gate conductor layer 1028 formed in FIG. for the sacrificial gate stack). Next, the gate spacer 1030 can be formed according to the operation described above in conjunction with FIG. 17 . In addition, the strained source/drain technique can also be applied according to the operation described above in connection with FIG. 18 .

Next, the sacrificial gate stack can be processed according to the replacement gate process to form the real gate stack of the device. For example, this can be done as follows.

Specifically, as shown in Figure 19 (Figure 19(a) corresponds to the cross-sectional view of Figure 18(b), and Figure 19(b) corresponds to the cross-sectional view of Figure 18(c)), for example, by deposition, a dielectric layer is formed 1034. The dielectric layer 1034 may comprise oxide, for example. Subsequently, the dielectric layer 1034 is planarized such as CMP. The CMP may stop at the gate spacer 1030 , thereby exposing the sacrificial gate conductor layer 1028 . Subsequently, the sacrificial gate conductor 1028 is selectively removed, such as by TMAH solution, thereby forming a gate trench 1036 inside the gate spacer 1030 . According to another example, the sacrificial gate dielectric layer 1026 may be further removed.

Then, as shown in Figure 20 (Figure 20(a) corresponds to the cross-sectional view of Figure 19(a), Figure 20(b) corresponds to the cross-sectional view of Figure 19(b), and Figure 20(c) corresponds to the cross-sectional view of Figure 16(b) 21 (showing the top view of the structure shown in FIG. 20 ), by forming the gate dielectric layer 1038 and the gate conductor layer 1040 in the gate groove, the final gate stack is formed. The gate dielectric layer 1038 may include a high-K gate dielectric such as HfO ₂ with a thickness of about 1-5 nm. In addition, the gate dielectric layer 1038 may also include a thin layer of oxide (the high-K gate dielectric is formed on the oxide), for example, the thickness is 0.3-1.2 nm. The gate conductor layer 1040 may include a metal gate conductor. Preferably, a work function adjustment layer (not shown) may also be formed between the gate dielectric layer 1038 and the gate conductor layer 1040 .

In this way, the FinFET according to this embodiment is obtained. As shown in FIGS. 20 and 21 , the FinFET includes a gate stack (including a gate dielectric layer 1038 and a gate conductor layer 1040 ) formed on the substrate 1000 and intersecting the combination of the back gate 1020 and the fin 1004 . As clearly shown in FIG. 20( c ), the gate conductor layer 1040 can control the fin 1004 to form a conductive channel on the side (the side opposite to the back gate 1020 ) via the gate dielectric layer 1038 . In addition, the back gate 1020 can control the fin 1004 through the back gate dielectric layer 1016, so as to change the threshold of the FinFET as required. The back gate 1020 is electrically isolated from the gate stack by the dielectric layer 1024 and the back gate dielectric layer 1016 .

After forming the FinFET as described above, various electrical contacts can also be made. For example, as shown in FIG. 22 , an interlayer dielectric (ILD) layer 1042 may be deposited on the surface of the structure shown in FIG. 21 . The ILD layer 1042 may include oxide, for example. A planarization process such as CMP may be performed on the ILD layer 1042 to make its surface substantially flat. Then, for example, a contact hole can be formed by photolithography, and a conductive material such as metal (for example, W or Cu, etc.) can be filled in the contact hole to form a contact portion, such as the contact portion 1044-1 with the gate stack, and the source/ The contact portion 1044-2 of the drain region and the contact portion 1044-2 with the back gate.

Fig. 23(a) and (b) respectively show cross-sectional views along line B1B1' and line B2B2' in Fig. 22 . As shown in Figure 23, the contact portion 1044-1 penetrates the ILD layer 1042, reaches the gate conductor 1040, and thus makes electrical contact with the gate conductor 1040; the contact portion 1044-2 penetrates the ILD layer 1042 and the dielectric layer 1034, and reaches the source/drain region (semiconductor layer 1032 in this example), and thus electrically contacts the source/drain region; contact 1044-3 penetrates ILD layer 1042, dielectric layer 1034, and isolation layer 1002 to substrate 1000 (in particular, where well region 1000-1), and thus make electrical contact with the back gate 1020. Via these electrical contacts, the required electrical signals can be applied.

It should be noted here that although the source/drain regions of the three fins are shown as being connected to the same contact in FIG. 23 , the present disclosure is not limited thereto. The specific electrical connection method can be determined according to the design.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design a method that is not exactly the same as the method described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be advantageously used in combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the present disclosure, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (19)

1. A semiconductor arrangement comprising: Substrate; a back gate formed on and protruding from the substrate; a fin formed on one side of the back gate, protruding from the substrate and extending adjacent to the back gate; a back gate dielectric layer sandwiched between the back gate and the fin; an isolation layer formed on the substrate exposing a portion of the fin; and A gate stack formed on the isolation layer, the gate stack intersects the fin and the back gate, wherein the gate stack is isolated from the back gate by a dielectric layer. 2. The semiconductor arrangement of claim 1, wherein a top surface of the back gate is level with or higher than a top surface of the fin. 3. The semiconductor arrangement of claim 1, wherein the back gate comprises a conductive material and has a width of 5-30 nm. 4. The semiconductor arrangement of claim 1, wherein the fins comprise Si, Ge, SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb and have a width of 3-28nm. 5. The semiconductor device according to claim 1, wherein the back gate dielectric layer comprises oxide and has an equivalent thickness of 10-40 nm. 6. The semiconductor arrangement of claim 1, wherein the substrate includes a well region therein, wherein the back gate is in electrical contact with the well region. 7. The semiconductor arrangement according to claim 6, further comprising: a punch-through barrier formed under a portion of the fin exposed by the isolation layer, the punch-through barrier having a doping concentration higher than that of the well region. 8. The semiconductor arrangement of claim 1, further comprising a semiconductor layer grown on a surface of portions of the fin on opposite sides of the gate stack. 9. The semiconductor arrangement according to claim 8, wherein if the semiconductor arrangement is used in a p-type device, the semiconductor layer is under compressive stress; if the semiconductor arrangement is used in an n-type device, the semiconductor layer is under tensile stress. 10. A method of manufacturing a semiconductor arrangement, comprising: forming back gate trenches in the substrate; forming a back gate dielectric layer on the sidewall of the back gate groove; Filling the back gate groove with conductive material to form a back gate; forming a dielectric layer in the back gate groove to cover the back gate; Patterning the substrate to form fins adjacent to the back gate dielectric layer on one side of the back gate; forming an isolation layer on the substrate exposing a portion of the fin; A gate stack is formed on the isolation layer, the gate stack intersects the fin and the back gate. 11. The method of claim 10, wherein, Forming the back gate groove includes: forming a patterning auxiliary layer on the substrate, the patterning auxiliary layer is patterned to have an opening corresponding to the back gate groove; forming a pattern transfer layer on the sidewall of the side wall of the patterning auxiliary layer opposite to the opening; Using the patterning auxiliary layer and the pattern transfer layer as a mask, etching the substrate to form back gate grooves, and Forming fins includes: Selective removal of composition aid layers; and Using the pattern transfer layer as a mask, the substrate is etched to form fins. 12. The method according to claim 11, wherein the top surface of the conductive material filled in the back gate trench is equal to or higher than the top surface of the substrate. 13. The method of claim 11, wherein forming the pattern transfer layer comprises: According to the sidewall forming process, forming a preliminary pattern transfer layer on the sidewall of the one side and the opposite side of the patterning auxiliary layer; performing oblique ion implantation so that ions enter into the preliminary pattern transfer layer on the other side; and Selective etching to remove the preliminary pattern transfer layer on the other side. 14. The method of claim 13, further comprising: A sidewall forming auxiliary layer into which ions also enter is formed on the patterning auxiliary layer. 15. The method according to claim 14, wherein the substrate comprises Si, Ge, SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb, and the patterning auxiliary layer comprises amorphous silicon, as well as The method also includes: forming a protection layer on the top surface of the patterning auxiliary layer to protect the patterning auxiliary layer during etching of the back gate groove. 16. The method of claim 15, further comprising forming a stopper layer on the substrate, the patterning assist layer being formed on the stopper layer. 17. The method of claim 16, wherein the sidewall forming auxiliary layer includes nitride, the protective layer includes oxide, the pattern transfer layer includes nitride, and the stop layer includes oxide. 18. The method according to claim 10, wherein a back gate dielectric layer is formed on the sidewall of the back gate trench according to a sidewall forming process. 19. The method of claim 10, wherein after forming the isolation layer and before forming the gate stack, the method further comprises: Ion implantation is performed to form punch-through barriers under the exposed portions of the fins.