CN103558717B - A kind of array base palte and preparation method thereof and display device - Google Patents

Abstract

The invention provides a kind of array base palte and preparation method thereof and the display device comprising this array base palte, belong to display technique field, it can solve the problem of the easy colour mixture of neighboring sub-pixel unit in existing display device.Display device of the present invention, by the position of public electrode between two adjacent sub-pixel unit regions being provided with the slit of predetermined interval, make the scope of the fringe field between public electrode and pixel electrode can only be applied to the outer ledge of public electrode, this fringe field can not be applied to neighboring sub-pixel unit, thus avoids neighboring sub-pixel unit to produce mixed color phenomenon.

Description

Array substrate, manufacturing method thereof, and display device

technical field

The invention belongs to the field of display technology, and in particular relates to an array substrate, a preparation method thereof, and a display device including the array substrate.

Background technique

Advanced super-dimensional field switching technology (ADSDS, ADvancedSuperDimensionSwitch, ShortforADS) through the electric field generated by the edge of the slit electrode (pixel electrode) in the same plane and the generation between the slit electrode layer (pixel electrode layer) and the plate electrode layer (common electrode) The electric field in the liquid crystal cell forms a multi-dimensional electric field, so that all oriented liquid crystal molecules between the slit electrodes in the liquid crystal cell and directly above the electrodes can be rotated, thereby improving the working efficiency of the liquid crystal and increasing the light transmission efficiency.

With the continuous improvement of product resolution, the size of pixels is getting smaller and smaller, and the requirements for pixel aperture ratio are also increasing, so the width of the black matrix is reduced as much as possible; at the same time, because the common electrode of ADSDS products is generally Indium Tin Oxide (IndiumTinOxides , referred to as ITO), where the ITO resistance is high, in order to reduce the resistance-capacitance (RC) delay and increase the storage capacitance, the area of the common electrode will be increased as much as possible when designing the common electrode. Generally, the ITO and the data line will completely overlap design.

Specifically, as shown in FIG. 1 , an existing high-resolution display device includes: an array substrate 20 , a color filter substrate 27 and a liquid crystal layer 34 disposed therebetween. Among them, the color filter substrate 27 includes a flat layer 24, on which red/green/blue sub-pixel units 23 are arranged, and a black matrix 22 is arranged between adjacent sub-pixel units 23; the array substrate 20 usually includes data lines 12 , the base substrate disposed on the array substrate 20, the base substrate is provided with a common electrode 14, an insulating layer 15 is disposed above the common electrode 14, and a pixel electrode 16 is disposed above the insulating layer 15, and the pixel electrode 16 is a slit electrode The pixel electrodes 16 are arranged at intervals correspondingly below each sub-pixel unit 23 .

When the data line 12 is energized, a fringe electric field 32 is generated between the pixel electrode 16 and the common electrode 15, and the liquid crystal molecules 31 located in the liquid crystal layer 34 will be deflected in the region where the electric field acts, and the incident backlight 11 will be activated by the liquid crystal layer 34 The outgoing light 21 is emitted from the sub-pixel unit area 26 (the left side in FIG. 1 ), and presents a light beam of a corresponding color. When there is no electric field, the liquid crystal molecules 31 have no deflection, no outgoing light, and are in a black state.

Since the width of the black matrix of high-resolution products is generally less than 6.0 μm, the overlapping width of the black matrix and the data lines is small. If the color filter substrate 27 and the array substrate 20 are slightly shifted to one side, as shown in FIG. 2 , the range of the fringe electric field formed by the pixel electrode 16 and the common electrode 25 will be close to or even exceed the other side of the black matrix 22 , that is, the deflection range of the liquid crystal layer will be close to or even exceed the other side of the black matrix 22 . When the display device displays red, green, and blue images separately, that is, the first sub-pixel unit 23 is loaded with data voltage, and the adjacent sub-pixel unit 23 is not loaded with voltage, then except for the outgoing light 21 of the first sub-pixel unit 23, There will be a slight outgoing light 25 on the side of the black matrix close to the adjacent sub-pixel unit 23, which will cause the monochromatic outgoing light (such as red) of the first sub-pixel unit 23 to be emitted from the adjacent sub-pixel unit 23 Monochromatic light (such as green) undergoes color mixing (such as yellow), and the problem is exacerbated by side viewing angles.

Contents of the invention

The object of the present invention is to solve the problem of easy color mixing in display devices in the prior art, and provide an array substrate and a display device that can avoid color mixing.

The technical solution adopted to solve the technical problem of the present invention is an array substrate, including a base substrate, on which a pixel electrode layer corresponding to each sub-pixel unit area is arranged, and the pixel electrode layer includes multiple strip-shaped pixel electrodes arranged at intervals; the base substrate is also provided with a common electrode insulated from the pixel electrode layer, and the common electrode is located between two adjacent sub-pixel unit regions. Slits with preset intervals.

In the array substrate provided by the present invention, the range of the fringe electric field between the common electrode and the pixel electrode can only be applied to the outer edge of the common electrode, and the fringe electric field cannot be applied to the adjacent sub-pixel units, that is, when a voltage is applied to the sub-pixel unit, the When no voltage is applied to the adjacent sub-pixel units, the fringe electric field cannot drive the long axis of the liquid crystal molecules to rotate along the direction parallel to the electric field, which will not cause the adjacent sub-pixel units to generate outgoing light, thereby avoiding color mixing.

Preferably, a compensation resistor layer is provided in the same layer between the strip-shaped pixel electrodes located between two adjacent sub-pixel unit regions. Since a planar electric field is formed between the compensation resistance layer and the pixel electrodes of adjacent pixel units, the planar electric field and the fringe electric field can superimpose and act on the liquid crystal molecules above the pixel unit, thereby improving the transmittance of incident light.

Preferably, the compensation resistance layer is made of indium tin oxide, with a thickness in the range of , or the compensation resistor layer is made of conductive metal with a thickness range of .

Preferably, the compensation resistance layer has a width in the range of 2.0-3.0um.

Preferably, the slits at preset intervals have a width in the range of 2.0-3.0um.

Preferably, the width range between the edge of the compensation resistor layer and the adjacent edge of the strip-shaped pixel electrode is 2.0-3.0um.

Preferably, the array substrate is also provided with a common electrode line, an insulating layer is provided between the strip-shaped pixel electrodes and the common electrode, the compensation resistor layer is provided on the insulating layer, and is arranged on the The vias on the insulating layer are connected to the common electrode line.

Another object of the present invention is to solve the problem that adjacent pixel units of the display device in the prior art are prone to color mixing, and provide a display device that can avoid color mixing.

The technical solution adopted to solve the technical problem of the present invention is a display device, including a color filter substrate, and also includes the above-mentioned array substrate, the color filter substrate is provided with a black matrix and a plurality of sub-pixel units, and the array substrate The slits at preset intervals of the common electrodes correspond to the positions of the black matrix.

Preferably, the compensation resistor layer on the array substrate corresponds to the position of the black matrix.

Preferably, the width range of the black matrix is 4-6um.

The present invention also provides a method for manufacturing the above-mentioned array substrate, comprising: depositing a conductive thin film layer on the base substrate, forming a pattern including a pixel electrode layer corresponding to each sub-pixel unit area, and a pattern of a common electrode through a patterning process, In addition, the pixel electrode layer includes a plurality of strip-shaped pixel electrodes arranged at intervals, and the common electrode is provided with slits at preset intervals at positions between two adjacent sub-pixel unit regions.

Preferably, the manufacturing method of the array substrate further includes: forming a pattern of a compensation resistance layer in the same layer between the strip-shaped pixel electrodes located between two adjacent sub-pixel unit regions.

Preferably, the manufacturing method of the array substrate further includes: forming a pattern of common electrode lines and a pattern of an insulating layer on the base substrate, and the insulating layer is formed between the pixel electrode layer and the common electrode, so that The above-mentioned compensation resistance layer is formed on the insulating layer, and is connected to the common electrode line through the via hole provided on the insulating layer. Since the display device of the present invention has the above-mentioned array substrate, it can avoid color mixing between adjacent sub-pixel units.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a display device in the prior art when the boxes are correctly aligned.

FIG. 2 is a schematic cross-sectional view of a display device in the prior art when color mixing occurs due to a deviation in alignment of boxes.

Fig. 3 is a schematic cross-sectional view of the display device when the box is correctly aligned in Embodiment 1 of the present invention.

FIG. 4 is a schematic cross-sectional view of the display device in Embodiment 1 of the present invention when the box is deviated.

FIG. 5 is a schematic diagram of connecting the compensation resistance layer to the common electrode line through a via hole in Embodiment 1 of the present invention.

FIG. 6 is a schematic partial cross-sectional view of the array substrate with via holes in Embodiment 1 of the present invention.

in:

11. Incident light; 12. Data line; 13. Substrate substrate; 14. Common electrode; 15. Insulation layer; 16. Pixel electrode; 17. Compensation resistance layer; 18. Via hole; 19. Common electrode line; 20. Array substrate; 21. Outgoing light; 22. Black matrix; 23. Subpixel unit; 24. Flat layer; 25. Small beam of outgoing light; 26. Subpixel unit area; 27. Color filter substrate; 31. Liquid crystal molecules; 32 . Fringe electric field; 33. Plane electric field; 34. Liquid crystal layer; 35. Slit.

detailed description

In order to enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

Example 1

As shown in FIGS. 3-6 , the present embodiment provides an array substrate, a display device including the array substrate, and a manufacturing method of the array substrate.

As shown in FIG. 3 , the display device of the present invention includes an array substrate 20 and a color filter substrate 27 , and a liquid crystal layer 34 disposed therebetween.

Wherein, the array substrate 20 includes a base substrate 13, on which a pixel electrode layer corresponding to each sub-pixel unit area 26 is arranged, and the pixel electrode layer includes a plurality of strip-shaped pixel electrodes arranged at intervals. 16. The base substrate 13 is also provided with a common electrode 14 which is insulated from the pixel electrode layer, wherein an insulating layer 15 may be provided between the common electrode 14 and the pixel electrode 16; the common electrode 14 is located between two adjacent sub-pixel unit regions 26 and is provided with slits 35 at predetermined intervals. Preferably, the width of the slits 35 at preset intervals ranges from 2.0-3.0um.

In this way, the range of the fringe electric field 32 between the common electrode 14 and the pixel electrode 16 can only act on the outer edge of the common electrode 14, and the fringe electric field 32 is only within the range of the sub-pixel unit area 26, and will not exceed this range, that is, when When a voltage is applied to the sub-pixel unit area 26 (the left side in the figure), and no voltage is applied to the adjacent sub-pixel unit area (the sub-pixel unit area on the right side of 26 in the figure), the fringe electric field 32 cannot act on the 26 in the figure. Therefore, the long axis of the liquid crystal molecules 31 in this region will not rotate, so that the sub-pixel unit region on the right side of the adjacent sub-pixel unit region 26 will not generate outgoing light 21, thereby avoiding the mixed colors.

Preferably, a compensation resistor layer 17 is provided in the same layer between the strip-shaped pixel electrodes 16 located between two adjacent sub-pixel unit regions 26 . Since the planar electric field 33 is formed between the compensation resistance layer 17 and the pixel electrode 16 of the adjacent sub-pixel unit region 26, the planar electric field 33 and the fringe electric field 32 can superimpose and act on the liquid crystal molecules 31 above the sub-pixel unit region 26, which improves the incident The transmittance of light 11.

Further, the width range of the slit 35 can be controlled so that the projection of the compensation resistor layer 17 on the plane where the common electrode 14 is located does not intersect with the common electrode 14 .

Wherein, the color filter substrate 27 includes a flat layer 24 and a plurality of sub-pixel units 23 arranged on the flat layer 24, and a black matrix 22 is arranged between adjacent sub-pixel units 23 of the color filter substrate 27; preferably, the array The preset spacing of the slits 35 of the common electrodes 14 on the substrate 20 corresponds to the position of the black matrix 22 . Further, the compensation resistance layer 17 on the array substrate 20 corresponds to the position of the black matrix 22, that is, the compensation resistance layer 17 is below the black matrix 22, that is, the compensation resistance layer 17 is located on the black matrix 22 and the compensation resistance layer 17 In the projection of the plane where it is located, this further prevents the action range of the plane electric field 33 from going beyond the other side of the black matrix 22 .

As shown in FIG. 4 , even if the color filter substrate 27 and the array substrate 20 are shifted to one side when the box is aligned, there will be no sub-pixel unit area adjacent to the sub-pixel unit area 26 (right side in the figure). Produces a small beam of outgoing light. Preferably, the width range of the black matrix is 4-6um, and the size of the compensation resistance layer in the direction of the shortest distance between the sub-pixel units 23 on both sides is 2.0-3.0um, that is, the compensation resistance layer 17 shown in FIG. 3 The width range is 2.0-3.0um.

Preferably, the centerline of the compensation resistor layer 17 in the direction perpendicular to the color filter substrate 27 coincides with the centerline of the black matrix 22 in the direction perpendicular to the color filter substrate 27, so that when the color filter substrate 27 and the array substrate 20 When the box is shifted to one side, the deviation of the above-mentioned center line of the black matrix 22 and the compensation resistance layer 17 is also within the control range, and the range of action of the plane electric field 33 will not exceed the other side of the black matrix 22, such as As shown in FIG. 4 , a small beam of outgoing light will not be generated in the sub-pixel unit area adjacent to the sub-pixel unit area 26 (right side in the figure).

Preferably, the width range between the edge of the compensation resistor layer 17 and the adjacent edge of the strip-shaped pixel electrode 16 is 2.0-3.0 um. An appropriate distance is kept to control the range of action of the planar electric field 33 .

Preferably, the compensation resistance layer 17 is made of indium tin oxide or conductive metal, and the thickness ranges are respectively or Both the common electrode 14 and the compensation resistance layer 17 can use indium tin oxide, which can save operation steps; when using conductive metal, since the compensation resistance layer 17 is located in the projection of the black matrix 22 on the plane where the compensation resistance layer 17 is located, even if the conductive metal It is not transparent and does not affect the emission of light. At the same time, the conductive metal has better conductivity and reduces the resistance of the common electrode.

As shown in FIGS. 5-6 , preferably, an insulating layer 15 is provided between the common electrode 14 and the pixel electrode 16, and the compensation resistance layer 17 is disposed on the insulation layer 15. The hole 18 is connected to the common electrode line 19, which can reduce the resistance of the common electrode, which is beneficial to the improvement of the display quality.

The manufacturing method of the above-mentioned array substrate 20 includes the following steps:

1. Deposit a conductive thin film layer on the base substrate 13, form a pattern comprising a pixel electrode layer corresponding to each sub-pixel unit area 26, and a pattern of a common electrode 14 through a patterning process, and the pixel electrode layer includes a plurality of intervals The strip-shaped pixel electrodes 16 are provided, and the common electrode 14 is provided with slits 35 at preset intervals at positions between two adjacent sub-pixel unit regions 26 . The patterning process belongs to the prior art category, and will not be repeated here.

2. A pattern of compensation resistance layer 17 is formed on the same layer between the strip-shaped pixel electrodes 16 located between two adjacent sub-pixel unit regions 26 . The patterning process belongs to the prior art category, and will not be repeated here.

3. Form the pattern of the common electrode line 19 and the pattern of the insulating layer 15 on the base substrate, and the insulating layer 15 is formed between the pixel electrode layer and the common electrode 14, and the compensation resistance layer 17 is formed on on the insulating layer 15 and connected to the common electrode line 19 through the via hole 18 provided on the insulating layer 15 . The patterning process and the fabrication of via holes are in the scope of the prior art, and will not be repeated here.

It can be understood that, the above embodiments are only exemplary embodiments adopted for illustrating the principle of the present invention, but the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims (11)

1. An array substrate, comprising a base substrate, the base substrate is provided with a pixel electrode layer corresponding to each sub-pixel unit area, and the pixel electrode layer includes a plurality of strip-shaped pixel electrodes arranged at intervals; The base substrate is also provided with a common electrode that is insulated from the pixel electrode layer, and is characterized in that the common electrode is located between two adjacent sub-pixel unit regions and is provided with a predetermined interval. slit; A compensation resistor layer is provided on the same layer between the strip-shaped pixel electrodes located between two adjacent sub-pixel unit regions. 2. The array substrate according to claim 1, wherein the compensation resistor layer is made of indium tin oxide, and its thickness ranges from Or the compensation resistance layer is made of conductive metal with a thickness range of 3. The array substrate according to claim 1, wherein the compensation resistor layer has a width in the range of 2.0-3.0um. 4 . The array substrate according to claim 1 , wherein the slits at predetermined intervals have a width in the range of 2.0-3.0 um. 5 . The array substrate according to claim 1 , wherein a width range between the edge of the compensation resistor layer and the edge of the adjacent strip-shaped pixel electrode is 2.0-3.0 um. 6. The array substrate according to claim 1, wherein a common electrode line is further arranged on the array substrate, an insulating layer is arranged between the strip-shaped pixel electrode and the common electrode, and the compensation resistor layer It is arranged on the insulating layer and connected to the common electrode line through the via hole arranged on the insulating layer. 7. A display device, comprising a color filter substrate, characterized in that it also includes the array substrate according to any one of claims 1-6, the color filter substrate is provided with a black matrix and a plurality of sub-pixel units, the The slits at preset intervals of the common electrodes of the array substrate correspond to the positions of the black matrix. 8. The display device according to claim 7, wherein the compensation resistor layer on the array substrate corresponds to the position of the black matrix. 9. The display device according to claim 7, wherein the width of the black matrix is 4-6um. 10. A method for manufacturing an array substrate, comprising: depositing a conductive thin film layer on the base substrate, forming a pattern comprising a pixel electrode layer corresponding to each sub-pixel unit area, and a pattern of the common electrode through a patterning process , and the pixel electrode layer includes a plurality of strip-shaped pixel electrodes arranged at intervals, and the common electrode is located between two adjacent sub-pixel unit regions, and a slit at a preset interval is provided; It also includes: forming a pattern of a compensation resistance layer in the same layer between the strip-shaped pixel electrodes located between two adjacent sub-pixel unit regions. 11. The method according to claim 10, further comprising: forming the pattern of the common electrode line and the pattern of the insulating layer on the substrate, and the insulating layer is formed on the pixel electrode layer and the common electrode Between, the compensation resistor layer is formed on the insulating layer, and is connected to the common electrode line through the via hole provided on the insulating layer.