CN102779481A - A kind of driving circuit for OLED panel - Google Patents

Abstract

The present invention provides a driving circuit for an OLED panel, including: a line buffer having an input terminal for receiving a data voltage signal; and an output buffer electrically connected to the line buffer, wherein the first multiplexer outputs one of the data voltage signal and the reference voltage signal by a first enable signal, and the second multiplexer outputs the other of the data voltage signal and the reference voltage signal by a second enable signal. The first multiplexer alternately outputs the data voltage signal and the reference voltage signal, and the second multiplexer alternately outputs the reference voltage signal and the data voltage signal. By adopting the invention, the first multiplexer and the second multiplexer in the output buffer output the data voltage signal and the reference voltage signal in an interleaving manner, so that two channels can be adopted for carrying out charge sharing operation when the two are switched, and each channel is only responsible for half of voltage change during charge sharing, thereby effectively reducing the dynamic loss of the circuit and further reducing the working temperature of the circuit.

Description

A kind of driving circuit for OLED panel

technical field

The invention relates to an OLED panel, in particular to a source driving circuit in the OLED panel.

Background technique

Currently, the OLED (Organic Light Emitting Diode) display has the characteristics of self-luminescence, which can save the weight, volume and power consumption of the backlight module, so it is not only thinner than the Liquid Crystal Display (LCD), but also The operating voltage can be reduced to 2V to 10V. In addition, OLED has a wide viewing angle, fast picture response (such as less than 10ms) and better color performance than LCD, and has a bendable feature, which makes its application range extremely wide. It has been used in handheld devices such as mobile phones and personal digital assistants. Display panels for electronic products.

As we know, OLED panels use organic light-emitting diodes as light-emitting components, and organic light-emitting diodes are components driven by current, and their luminous brightness will change with the current passing through the organic light-emitting diodes. Specifically, in a traditional OLED panel, the brightness of the panel is proportional to the current flowing through the organic light-emitting diode, and the OLED current is proportional to the Vgs (gate-source voltage) of the corresponding thin film transistor (Thin Film Transistor, TFT). The Ids are related, so the final panel brightness can be expressed as:

T _OLED =β×I _OLED =β×k×(V _GS −V _TH ) ²

Among them, β and k are constants, V _GS is the voltage difference between the gate and source of the TFT, V _TH is the turn-on voltage of the TFT, I _OLED is the current flowing through the organic light-emitting diode, and T _OLED is the voltage of the OLED panel. brightness. However, due to the process differences among multiple TFTs, it is easy to cause uneven display. One solution to the traditional OLED panel is: first, use the reset signal to release the residual charge of the OLED and TFT; The compensation voltage is stored in the pixel capacitor; then, the data voltage is written into the pixel capacitor; finally, the capacitance stored in the pixel capacitor determines the V _GS of the TFT, and then determines the current flowing through the OLED to adjust the brightness of the OLED panel. In this way, a reference voltage needs to be output during the reset phase and compensation phase, and a data voltage needs to be output during the data writing phase, causing the output terminal of the operational amplifier to continuously switch between the reference voltage and the data voltage, resulting in a large dynamic loss and higher temperature rise.

In view of this, how to design a novel driving circuit for OLED panels to reduce the dynamic loss of the source driver and reduce its operating temperature is an urgent task to be solved by relevant technical personnel in the industry.

Contents of the invention

Aiming at the above-mentioned defects of the drive circuit for OLED panels in the prior art, the present invention provides a novel drive circuit for OLED panels to reduce the dynamic loss of the circuit and reduce its operating temperature.

According to one aspect of the present invention, a driving circuit for an OLED panel is provided, including:

a line buffer having an input end, the input end of the line buffer is used to receive a data voltage signal; and

an output buffer electrically connected to the line buffer, the output buffer includes a first multiplexer and a second multiplexer, the first multiplexer is enabled by a first enable signal outputting one of the data voltage signal and a reference voltage signal, the second multiplexer outputs the other of the data voltage signal and the reference voltage signal through a second enable signal,

Wherein, the first multiplexer outputs the data voltage signal and the reference voltage signal alternately, and the second multiplexer outputs the reference voltage signal and the data voltage signal alternately.

In one embodiment, the drive circuit further includes: a first RS latch having a set terminal, a reset terminal and an output terminal, the set terminal is connected to a first set signal, and the reset terminal connected to a second set signal, the output terminal outputs the first enable signal; and a second RS latch, which has a set terminal, a reset terminal and an output terminal, and the set terminal is connected to For the second setting signal, the reset terminal is connected to the first setting signal, and the output terminal outputs the second enabling signal.

In one embodiment, both the first setting signal and the second setting signal are periodic signals, and there is a preset delay time between the first setting signal and the second setting signal.

In an embodiment, the driving circuit further includes a clock signal, the first setting signal corresponds to a falling edge of the clock signal, and the second setting signal corresponds to a rising edge of the clock signal. Further, when the first set signal is a falling edge, the first multiplexer outputs the data voltage signal, and the second multiplexer outputs the reference voltage signal. When the second set signal is a falling edge, the first multiplexer outputs the reference voltage signal, and the second multiplexer outputs the data voltage signal.

In one embodiment, the data voltage signal is greater than or equal to the reference voltage signal.

According to another aspect of the present invention, a driving circuit for an OLED panel is provided, including:

A timing controller, the timing controller includes a plurality of data frames, each data frame is divided into a first subframe and a second subframe, the first subframe is used to input a first data voltage signal, so The second subframe is used to input a second data voltage signal;

An output buffer, electrically connected to the timing controller, the output buffer includes a first multiplexer and a second multiplexer, the first multiplexer is controlled by a first enable signal Outputting one of the first data voltage signal and a reference voltage signal, the second multiplexer outputs the other of the second data voltage signal and the reference voltage signal through a second enable signal one,

Wherein, the first multiplexer outputs the first data voltage signal and the reference voltage signal alternately, and the second multiplexer outputs the reference voltage signal and the second data voltage signal alternately .

In one embodiment, the drive circuit further includes: a first RS latch, having a set terminal, a reset terminal and an output terminal, the set terminal is connected to a first set signal, and the reset The terminal is connected with a second setting signal, and the output terminal outputs the first enabling signal; and a second RS latch has a setting terminal, a reset terminal and an output terminal, and the setting terminal The second setting signal is connected, the reset terminal is connected to the first setting signal, and the output terminal outputs the second enabling signal.

In one embodiment, both the first setting signal and the second setting signal are periodic signals, and there is a preset delay time between the first setting signal and the second setting signal.

Using the drive circuit for OLED panels of the present invention, the first multiplexer in the output buffer outputs one of the data voltage signal and the reference voltage signal, and the second multiplexer outputs the data voltage signal and the reference voltage signal. The other one of the reference voltage signal makes it possible to use two channels for charge sharing operation when switching between the data voltage signal and the reference voltage signal. Since each channel is only responsible for half of the voltage change during charge sharing, the circuit can be effectively reduced The dynamic loss, thereby reducing the operating temperature of the circuit.

Description of drawings

Readers will have a clearer understanding of various aspects of the present invention after reading the detailed description of the present invention with reference to the accompanying drawings. in,

FIG. 1 shows a schematic structural diagram of a driving circuit for an OLED panel in the prior art;

FIG. 2 shows a schematic structural diagram of a driving circuit for an OLED panel according to an embodiment of the present invention;

Fig. 3 (a) shows in the driving circuit of Fig. 2, is used for controlling the circuit schematic diagram of the first enabling signal of the first multiplexer;

Fig. 3 (b) shows in the drive circuit of Fig. 2, is used to control the circuit schematic diagram of the second enabling signal of the second multiplexer;

FIG. 4 shows a schematic diagram of signal waveforms of a clock signal, a first set signal, a second set signal, odd channels and even channels of a line buffer in the driving circuit of FIG. 2; and

FIG. 5 shows a schematic diagram of data waveforms output by the clock signal, the first set signal, the second set signal, the odd-channel operational amplifier and the even-channel operational amplifier of the output buffer in the driving circuit of FIG. 2 .

Detailed ways

In order to make the technical content disclosed in this application more detailed and complete, reference may be made to the drawings and the following various specific embodiments of the present invention, and the same symbols in the drawings represent the same or similar components. However, those skilled in the art should understand that the examples provided below are not intended to limit the scope of the present invention. In addition, the drawings are only for schematic illustration and are not drawn according to their original scale.

The specific implementation manners of various aspects of the present invention will be further described in detail below with reference to the accompanying drawings.

FIG. 1 shows a schematic structural diagram of a driving circuit for an OLED (Organic Light Emitting Diode, organic light emitting diode) panel in the prior art. Referring to FIG. 1 , a conventional driving circuit includes two parts, a source driver 10 and a pixel circuit 20 . Wherein, the source driver 10 includes a multiplexer 101 (MUX) and an operational amplifier 103 (OP). The input terminal of the operational amplifier 103 is electrically connected to the output terminal of the multiplexer 101 . In addition, the multiplexer 101 further includes two input terminals, one of which is used to receive a data voltage signal Vdata, and the other input terminal is used to receive a reference voltage signal Vref.

Generally, the data voltage signal Vdata is greater than or equal to the reference voltage signal, when the multiplexer 101 selects the data voltage signal as the output signal, the operational amplifier 103 processes the data voltage signal; when the multiplexer 101 selects the reference voltage signal as the output signal, the operational amplifier 103 processes the reference voltage signal. As shown in FIG. 1 , the data module 201 of the pixel circuit 20 is used to send the processed data voltage signal Vdata or the reference voltage signal Vref to the subsequent thin film transistor to generate the current I _OLED . As mentioned above, in the traditional circuit structure, the pixel circuit 20 needs to generate a reference voltage during the reset phase and the compensation phase, and needs to generate a data voltage during the data writing phase, which will cause the output terminal of the operational amplifier 103 to Constantly switching between the reference voltage Vref and the data voltage Vdata causes greater dynamic loss and higher temperature rise.

In order to effectively solve the problem of dynamic loss in the existing driving circuit, FIG. 2 shows a schematic structural diagram of a driving circuit for an OLED panel according to an embodiment of the present invention.

Referring to FIG. 2 , in this embodiment, a driving circuit for an OLED panel includes a line buffer 30 and an output buffer 40 . Wherein, the line buffer 30 has an input terminal for receiving a data voltage signal Data. The output buffer 40 is electrically connected to the line buffer 30 . The output buffer 40 includes a first multiplexer 401, a first operational amplifier 403, a second multiplexer 405 and a second operational amplifier 407, wherein the first operational amplifier 403 is electrically connected to the first multiplexer The output end of the second multiplexer 401, and the second operational amplifier 407 is electrically connected to the output end of the second multiplexer 405. In addition, the output terminal of the first operational amplifier 403 is connected to a pixel storage capacitor Cst via a switch, and the output terminal of the second operational amplifier 407 is connected to another pixel storage capacitor Cst via another switch. When the output terminal of the first operational amplifier 403 outputs the data voltage signal, and the output terminal of the second operational amplifier 407 outputs the reference voltage signal, the opening or conduction of the corresponding switch is controlled, so that the circuit works in charge sharing (Charge Sharing, CS )state.

It should be noted that, according to the number of pulses of the clock signal, the line buffer 30 may correspondingly include an odd-numbered output channel and an even-numbered output channel. For example, when the clock signal is a falling edge, a first set signal STB1 is generated, and the odd-numbered output channels of the line buffer 30 output the data voltage signal (marked as V _{data_o} , corresponding to an odd number) by the first set signal STB1 data); when the clock signal is a rising edge, a second set signal STB2 is generated, and by the second set signal STB2, the even-numbered output channels of the line buffer 30 output the data voltage signal (marked as V _{data_e} , corresponding even data). Those skilled in the art should understand that the above is only a schematic example of the source drive circuit of the present invention. In other embodiments, the set signal STB1 can also be generated when the clock signal is on the rising edge, and output by an odd number channels to output the data voltage signal; and when the clock signal is a falling edge, a set signal STB2 is generated, and the data voltage signal is output by the even output channels.

In a specific embodiment, the first multiplexer 401 alternately outputs the data voltage signal V _{data_o} and the reference voltage signal V _ref , and the second multiplexer 405 alternately outputs the data voltage signal V _{data_e} and the reference voltage signal _Vref . In addition, the first multiplexer 401 can also include a control terminal Sel_o, and the second multiplexer 405 can also include a control terminal Sel_e, and the output signals of the first multiplexers 401 and 405 can be controlled respectively through the control terminals Sel_o and Sel_e . Specifically, it can be described in detail in conjunction with FIG. 3( a ) and FIG. 3( b ) below.

In one embodiment, the driving circuit further includes a timing controller and an output buffer. The timing controller can output a plurality of data frames, each data frame is divided into a first subframe and a second subframe, and the first subframe is used to correspond to a first data voltage signal, and the second subframe is used to corresponding to a second data voltage signal. For example, the pulse width and amplitude of the first data voltage signal and the second data voltage signal are the same, and the data voltage signal is correspondingly input to the first multiplexer 401 in the first half frame of the data frame, and in the second half frame of the data frame The corresponding input data voltage signal is sent to the second multiplexer 405 . The first multiplexer 401 outputs one of the data voltage signal and the reference voltage signal according to a first control signal (or enable signal) input to the control terminal Sel_o, and the second multiplexer 405 outputs one of the data voltage signal and the reference voltage signal according to the input control terminal Sel_o. A second control signal (or called an enable signal) of Sel_e outputs the other one of the data voltage signal and the reference voltage signal. That is to say, when the first multiplexer 401 outputs the data voltage signal, the second multiplexer 405 outputs the reference voltage signal, and when the first multiplexer 401 outputs the reference voltage signal, the second multiplexer 405 outputs the data voltage Signal.

Fig. 3 (a) shows in the driving circuit of Fig. 2, is used for controlling the circuit schematic diagram of the first enable signal of the first multiplexer, and Fig. 3 (b) shows in the driving circuit of Fig. 2, is used to control the first multiplexer A schematic circuit diagram of the second enable signal of the two multiplexers.

Referring to Fig. 3 (a) and Fig. 3 (b), in this embodiment, the drive circuit also includes RS latch 501 (Rest-Set latch, or called SR latch) and RS latch 503 . Wherein, the RS latch 501 corresponds to the first multiplexer 401 , and the RS latch 503 corresponds to the second multiplexer 403 .

Specifically, the RS latch 501 has a set terminal set, a reset terminal reset and an output terminal. The set terminal set is connected to a first set signal STB_1, the reset terminal reset is connected to a second set signal STB2, and the output terminal outputs the first enable signal Sel_o. Similarly, the RS latch 503 has a set terminal set, a reset terminal reset and an output terminal. The set terminal set is connected to a first set signal STB2, the reset terminal reset is connected to a second set signal STB1, and the output terminal outputs the second enable signal Sel_e. For example, when the set signal STB1 is a falling edge, the first multiplexer 401 outputs a data voltage signal, and the second multiplexer 403 outputs a reference voltage signal; when the set signal STB2 is a falling edge, the first multiplexer 401 A reference voltage signal is output, and the second multiplexer 403 outputs a data voltage signal, as shown in FIG. 4 .

In an embodiment, n/2 latches may be provided before the level shifting circuit in the driving circuit as the aforementioned line buffer 30 . In operation, when the set signal STB1 is at a rising edge, the latch in the driving circuit sends the odd data to the aforementioned output buffer 40 and the even data to the aforementioned line buffer 30 via the level shift circuit. When the set signal STB1 is a falling edge, the first operational amplifier 403 in the output buffer 40 outputs a data voltage signal corresponding to odd data, and the second operational amplifier 407 in the output buffer 40 outputs a corresponding reference voltage signal.

In addition, when the set signal STB2 is at a rising edge, the line buffer 30 sends the even-numbered data to the aforementioned output buffer 40 through the level shift circuit, and when the setting signal STB2 is at a falling edge, the data in the output buffer 40 The second operational amplifier 407 outputs a data voltage signal corresponding to even data, and the first operational amplifier 403 outputs a corresponding reference voltage signal.

On the other hand, the aforementioned output buffer 40 can also be set in the timing controller (Tcon), in which the data is rearranged or configured as odd data and even data, and the odd data and even data are output at different times , and the data transmission speed is also doubled accordingly.

For example, odd number data is output during a single frame, and when the set signal STB1 is a rising edge, the latch sends the odd number data to the output buffer 40, and when the set signal STB1 is a falling edge , the first operational amplifier 403 in the output buffer 40 outputs a data voltage signal corresponding to odd data, and the second operational amplifier 407 in the aforementioned output buffer 40 outputs a corresponding reference voltage signal. Next, the even data is output during the same frame, and when the set signal STB2 is a rising edge, the latch sends the even data to the output buffer 40, and when the set signal STB2 is a falling edge, the output buffer The second operational amplifier 407 in the device 40 outputs a data voltage signal corresponding to even data, and the first operational amplifier 403 outputs a corresponding reference voltage signal.

In one embodiment, both the first set signal STB1 and the second set signal STB2 are periodic signals, and there is a preset delay time between the first set signal STB1 and the second set signal STB2 . For example, the delay period corresponds to the pulse width of the clock signal, as shown in FIG. 5 .

Using the drive circuit for OLED panels of the present invention, the first multiplexer in the output buffer outputs one of the data voltage signal and the reference voltage signal, and the second multiplexer outputs the data voltage signal and the reference voltage signal. The other one of the reference voltage signal makes it possible to use two channels for charge sharing operation when switching between the data voltage signal and the reference voltage signal. Since each channel is only responsible for half of the voltage change during charge sharing, the circuit can be effectively reduced The dynamic loss, thereby reducing the operating temperature of the circuit.

Hereinbefore, specific embodiments of the present invention have been described with reference to the accompanying drawings. However, those skilled in the art can understand that without departing from the spirit and scope of the present invention, various changes and substitutions can be made to the specific embodiments of the present invention. These changes and substitutions all fall within the scope defined by the claims of the present invention.

Claims (10)

1. a driving circuit for OLED (Organic Light Emitting Diode, organic light emitting diode) panel, it is characterized in that, described driving circuit comprises: a line buffer having an input end, the input end of the line buffer is used to receive a data voltage signal; and an output buffer electrically connected to the line buffer, the output buffer includes a first multiplexer and a second multiplexer, the first multiplexer is enabled by a first enable signal outputting one of the data voltage signal and a reference voltage signal, the second multiplexer outputs the other of the data voltage signal and the reference voltage signal through a second enable signal, Wherein, the first multiplexer outputs the data voltage signal and the reference voltage signal alternately, and the second multiplexer outputs the reference voltage signal and the data voltage signal alternately. 2. The drive circuit according to claim 1, wherein the drive circuit further comprises: A first RS latch has a set terminal, a reset terminal and an output terminal, the set terminal is connected to a first set signal, the reset terminal is connected to a second set signal, and the output Outputting the first enabling signal at the terminal; and A second RS latch has a set terminal, a reset terminal and an output terminal, the set terminal is connected to the second set signal, and the reset terminal is connected to the first set signal, so The output end outputs the second enabling signal. 3. The drive circuit according to claim 2, wherein both the first set signal and the second set signal are periodic signals, and the first set signal and the second set signal There is a preset delay time between bit signals. 4. The drive circuit according to claim 3, wherein the drive circuit further comprises a clock signal, the first set signal corresponds to the falling edge of the clock signal, and the second set signal signal corresponds to the rising edge of the clock signal. 5. The driving circuit according to claim 4, wherein when the first set signal is a falling edge, the first multiplexer outputs the data voltage signal, and the second multiplexer outputting the reference voltage signal. 6. The drive circuit according to claim 4, wherein when the second set signal is a falling edge, the first multiplexer outputs the reference voltage signal, and the second multiplexer outputting the data voltage signal. 7. The driving circuit according to claim 5 or 6, wherein the data voltage signal is greater than or equal to the reference voltage signal. 8. A drive circuit for an OLED (Organic Light Emitting Diode, organic light emitting diode) panel, characterized in that the drive circuit comprises: A timing controller, the timing controller includes a plurality of data frames, each data frame is divided into a first subframe and a second subframe, the first subframe is used to input a first data voltage signal, The second subframe is used to input a second data voltage signal; An output buffer, electrically connected to the timing controller, the output buffer includes a first multiplexer and a second multiplexer, the first multiplexer is controlled by a first enable signal Outputting one of the first data voltage signal and a reference voltage signal, the second multiplexer outputs the other of the second data voltage signal and the reference voltage signal through a second enable signal one, Wherein, the first multiplexer outputs the first data voltage signal and the reference voltage signal alternately, and the second multiplexer outputs the reference voltage signal and the second data voltage signal alternately . 9. The drive circuit according to claim 8, wherein the drive circuit further comprises: A first RS latch has a set terminal, a reset terminal and an output terminal, the set terminal is connected to a first set signal, the reset terminal is connected to a second set signal, and the output Outputting the first enabling signal at the terminal; and A second RS latch has a set terminal, a reset terminal and an output terminal, the set terminal is connected to the second set signal, and the reset terminal is connected to the first set signal, so The output end outputs the second enabling signal. 10. The driving circuit according to claim 8, wherein both the first setting signal and the second setting signal are periodic signals, and the first setting signal and the second setting signal There is a preset delay time between bit signals.

Images