CN102520760A - Processor for arbitrary waveform generating system - Google Patents

Abstract

The invention discloses a processor used in an arbitrary waveform generation system. The instruction buffer unit buffers the instruction set from an external computer; the processor core reads and executes each instruction one by one from the instruction set, and the instruction set supported by the waveform It is composed of generation instruction, loop control instruction, conditional jump instruction, wait instruction and clear trigger condition instruction. The waveform generation instruction also includes an output marker list, and outputs pulses according to the list; the marker storage unit is used to buffer the output pulse when outputting waveform data. The output mark list; the external control condition input unit transmits the trigger condition of the external input to the processor core, and the trigger condition can be used as the execution condition of each instruction. The invention simplifies the complexity of waveform generation by designing the instruction set that the processor can support, improves the overall execution speed, and improves the function and performance of arbitrary waveform generator products.

Description

A Processor Used in Arbitrary Waveform Generation System

technical field

The invention relates to the technical field of arbitrary waveform generators, in particular to a processor used in an arbitrary waveform generating system.

Background technique

Arbitrary waveform generator, as one of the common test and measurement instruments, has experienced many years of technical development. Similar products that are widely used and promoted in the market are mainly divided into desktop instruments and bus-type virtual instruments. The desktop instrument is relatively independent, but its volume is relatively large, and the scope of use environment is small, so it has certain limitations in the realization of remote operation and system integration. The bus-type virtual instrument has unique advantages in system integration and remote operation.

At present, the arbitrary waveform generator based on the bus can generate standard waveform, arbitrary waveform, arbitrary sequence and other functions. However, in the current arbitrary waveform generator, all the data of the arbitrary waveform is generated by the computer according to the demand, and then downloaded to the waveform generation module through the bus, and the waveform generation module outputs the analog waveform point by point according to the waveform data. However, the way that the computer uniformly generates all waveform data is relatively slow, and a large amount of data needs to be transmitted in the bus, which cannot realize real-time scheduling of arbitrary waveforms.

On the same day, this application applied for an invention titled "An Arbitrary Waveform Generation System Based on a Custom Processor". As shown in Figure 1, the system includes a control part and a hardware part, and the two parts perform data interaction through their respective interface units. The waveform generation module is used to generate waveform segment data of various types, lengths and periods, and name them respectively, and then download them to the hardware part through the waveform download module and the first interface unit. The storage control logic module realizes the read and write control of the waveform memory. The control program generation module receives the command set input by the user. The command set indicates the waveform segment name, calling order, and calling times that need to be called to form the required arbitrary waveform. The command set is compiled by the compiling module and downloaded to the hardware. part. The custom waveform processor receives and parses the command set, generates the call command of the corresponding waveform segment according to the command set instruction, and reads the waveform segment data through the storage control logic module; The required arbitrary waveform is formed after the waveform segment data is processed and output by the signal conditioning module.

It can be seen from the above description that the custom waveform processor is the core of the entire waveform generation system, and the instruction set that the custom waveform processor can support determines the complexity of the waveform that can be generated and the complexity of its own implementation.

Contents of the invention

In view of the fact that the arbitrary waveform and arbitrary sequence functions of arbitrary waveform generators on the market are relatively simple, they cannot provide more complex arbitrary waveform or arbitrary sequence functions in some tests. Therefore, the present invention provides a method for arbitrary waveform Generate a custom processor for the system. By designing the instruction set that the processor can support, the complexity of waveform generation is simplified, the overall execution speed is improved, and the function and performance of arbitrary waveform generator products are improved.

The scheme is implemented like this:

A kind of processor that is used for arbitrary waveform generation system is characterized in that, comprises: processor core, instruction buffer unit, number of cycles marking unit, Marker mark storage unit, external control condition input unit;

The instruction buffer unit is used to cache the instruction set from the external computer;

The processor core is used to read and execute each instruction one by one from the instruction set; the instruction set supported by the processor core consists of a waveform generation instruction, a loop control instruction, a conditional jump instruction, a wait instruction, and a clear trigger condition command composition;

When the processor core processes the waveform generation instruction, it extracts the name of the waveform segment from the waveform generation instruction, generates the calling instruction of the corresponding waveform segment, and sends it to the storage control logic module; the waveform segment data read by the storage control logic module is sequentially arranged one by one Output to the FIFO of the external signal conditioning module of the custom processor; the waveform generation instruction also includes an output marker list; the output marker list is stored in the Marker marker storage unit, each output marker is a numerical value, and the processor core outputs the waveform When segmenting data, compare the number of current output data with the value in the output tag list, and if they are the same, output a pulse;

When the processor core processes the loop control instruction, according to the loop condition according to the order and the number of times specified by the loop control instruction, the specified instruction is executed in a loop; wherein the number of loops is marked and stored in the loop number of marking unit;

When the processor core processes a conditional jump instruction, it first judges whether the jump condition is true, and if the condition is true, executes the specified instruction;

When the processor core processes the waiting instruction, it continuously judges whether the waiting end condition specified by the waiting instruction is satisfied, and if it is satisfied, executes the subsequent instruction;

When the processor core processes the clear trigger condition instruction, the trigger condition Trigger0 is set low; when the trigger condition Trigger0 is used as the waiting end condition and/or loop condition and/or jump condition, the processor core judges according to the value of Trigger0 Whether the corresponding conditions are met;

The Marker tag storage unit is used to cache the output tag list;

The external control condition input unit is configured to transmit an externally input trigger condition Trigger0 to the processor core.

Preferably, the waveform generation instruction Generate has a subset parameter subset(<start position>, <end position>);

When the processor core executes the waveform generation instruction Generate, it is judged whether Generate has a subset parameter subset, and if so, extracts the data output between the start position and the end position from the waveform segment data to be output; otherwise , to output the waveform segment data as a whole.

Preferably, the format of the loop control instruction is:

Repeat loop condition

Code snippet A

end Repeat

The code segment A is composed of instructions in the instruction set;

The cycle conditions include the following three situations:

1. the loop condition is N, and N is a positive integer, then the Repeat instruction realizes a finite number of loops, and the processor core executes the code segment A loop N times;

2. the loop condition is forever forever, then the Repeat instruction realizes an infinite number of loops, and the processor core loops the code segment A indefinitely until the processor core is powered down or reset;

③The loop condition is "until Trigger0", then the Repeat instruction realizes the script conditional loop, and the processor core loops the code segment A continuously until the processor detects that the Trigger0 is logic high.

Preferably, the format of the conditional jump instruction is:

If Trigger0

code snippet B

Else

code segment C

End if

Both the code segment B and the code segment C are composed of instructions in the instruction set;

When the processor core executes the conditional jump instruction, it first judges whether the Trigger0 is logic high, if so, executes the code segment B once, otherwise executes the code segment C once.

Preferably, the waiting instruction format is:

Wait waits for the end condition

The waiting end condition includes the following two situations:

1. The waiting end condition is N, and N is a positive integer; when the processor core executes the waiting instruction, the waiting delay counter is assigned a value N, and each processor clock cycle decrements the waiting delay counter by 1 and judges Whether it is 0, if it is not equal to 0, continue to perform minus 1 and judgment operations, if it is equal to 0, execute subsequent instructions;

② The waiting end condition is Trigger0; when the processor core executes the waiting instruction, it constantly judges the value of the Trigger0 signal, if it is low, it stays at the waiting instruction, and if it is high, it executes subsequent instructions.

Beneficial effect:

The self-defined processor designed by the present invention can support an instruction set composed of 5 instructions. Since there are few instruction types, the complexity of processor design is greatly reduced, and more complex arbitrary waveforms can be realized through the programming of such simple instructions. And any sequence function, the programming is simple, and the program segment is very short, which can further reduce the amount of data transmission between the control part and the hardware part of the waveform generation system.

Description of drawings

Figure 1 is a schematic diagram of the composition and structure of an arbitrary waveform generation system based on a custom processor.

Fig. 2 is a schematic diagram of the structure of the self-defined waveform processor of the present invention.

Detailed ways

The present invention will be described in detail below with reference to the accompanying drawings and examples.

Fig. 2 is the self-defined processor that the present invention is used for arbitrary waveform generation system, as shown in Fig. 2, this processor comprises: processor core, instruction buffer unit, number of cycles marking unit, Marker mark storage unit, external control condition input unit. This custom processor can be integrated in the FPGA.

The instruction buffer unit is used for buffering instruction sets from an external computer.

The processor core is used to read and execute each instruction one by one from the instruction set cached by the instruction buffer unit. In the present invention, the processor core supports an instruction set composed of the following five instructions, the five instructions are composed of a waveform generation instruction Generate, a loop control instruction, a conditional jump instruction, a wait instruction and a trigger condition clear instruction. The following introduces the functions of each instruction and the processing process of the processor core.

(1) The function of Generate is to generate an arbitrary waveform segment, and the data of the arbitrary waveform is extracted from the waveform memory of the arbitrary waveform generating system.

When the processor core executes the command Generate, the processor core extracts the name of the waveform segment from the waveform generation command, generates the calling command of the corresponding waveform segment, and sends it to the external storage control logic module; reads the storage control logic module from the waveform memory The acquired waveform segment data is output to the FIFO of the signal conditioning module outside the custom processor one by one in sequence. When the signal conditioning module detects that the internal FIFO is not empty, it performs digital-to-analog conversion on the data in the FIFO and outputs it.

The necessary parameter of Generate is the name of the waveform segment. If there is only the name of the waveform segment, the processor core will output the entire waveform data.

In order to improve the richness and flexibility of output signals, the Generate command supports subset output and tag output by setting subset parameters. Specifically,

Generate can carry a subset marker (<list of positions>), where list of positions is a list of output markers, which records which position or positions of the waveform segment need to output pulses in the process of outputting the waveform segment. The output tag list is stored in the Marker tag storage unit, each output tag is a numerical value, when the processor core outputs the waveform segment data, compare the current output data number with the value in the output tag list, if the two are the same, then output A pulse is given to the signal conditioning module, and the signal conditioning module generates a pulse analog quantity.

Generate can also carry the subset parameter subset (<start position>, <end position>); when the processor core executes the waveform generation command Generate, it is judged whether Generate has the subset parameter subset, if so, from the waveform segment data to be output Extract the data output between the start position and the end position; otherwise, output the waveform segment data as a whole.

Then the format expression of the Generate command can be completely expressed as:

Generate<wave segment name>subset(<start position>, <end position>) marker(<output marker list>).

(2) The function of the loop control instruction is to repeatedly execute a piece of code, which can support up to 16 layers of loop nesting.

When the processor core executes the loop control instruction, the processor core loops and executes the specified instruction according to the loop condition and the order and times specified by the loop control instruction; wherein the loop count mark is stored in the loop count mark unit.

In order to improve the flexibility of loop execution, the present invention provides various loop conditions. Then, the format of the loop control instruction can be:

Repeat loop condition

Instruction 1

...

Instruction M

end Repeat

Wherein, instruction 1 to instruction M are all selected from the instruction set.

The cycle conditions include the following three situations:

①The cycle condition is "N", and N is a positive integer, then the Repeat instruction realizes a limited number of cycles, and the processor core executes a total of M instructions from instruction 1 to instruction M for N times;

②The loop condition is "forever", then the Repeat instruction realizes an infinite loop, and the processor core loops a total of M instructions from instruction 1 to instruction M indefinitely until the processor core is powered off or reset;

③The loop condition is "until Trigger0 is logic high, that is, until Trigger0", then the Repeat instruction realizes the script conditional loop, and the processor core executes a total of M instructions from instruction 1 to instruction M in a non-stop cycle until the processor detects the Trigger0 to logic high. Wherein, Trigger0 is a trigger condition, which is input to the processor core through an external control condition input unit.

(3) The function of the conditional jump instruction is to select and execute a piece of code, and the nesting depth is only limited by the instruction storage space.

When the processor core executes a conditional jump instruction, it first judges whether the jump condition is true, and if the condition is true, executes the specified instruction.

Wherein, in order not to set a new variable, the present invention uses an externally input trigger condition Trigger0 as a jump condition. Then the format of the conditional jump instruction can be:

If Trigger0

Instruction 1

...

Instruction M

Else

  Instruction M+1

...

Instruction L

End if

When the processor core executes the conditional jump instruction, it first judges whether the Trigger0 is logic high, and if so, executes a total of M instructions from instruction 1 to instruction M, otherwise executes a total of M instructions from instruction M+1 to instruction L. L-M instructions are executed once.

(4) The function of the waiting instruction is to wait until the waiting end condition is satisfied.

When the processor core executes the waiting instruction, it continuously judges whether the waiting end condition specified by the waiting instruction is satisfied, and if it is satisfied, executes the next instruction, and if not, continues to judge.

The format of the jump instruction in the present embodiment is: Wait waits for the end condition

The waiting end condition includes waiting delay and waiting trigger condition Trigger0:

① The waiting end condition is N, and N is a positive integer; when the processor core executes the waiting instruction, the waiting delay counter is assigned a value N, and the waiting delay counter is decremented by 1 every processor clock cycle and judged whether it is 0, If it is not equal to 0, continue to perform minus 1 and judgment operations, and if it is equal to 0, execute the next instruction.

② The waiting end condition is Trigger0; when the processor core executes the waiting instruction, it continuously judges the value of the Trigger0 signal, if it is low, it stays at the waiting instruction, and if it is high, executes the next instruction.

(5) The function of the clear trigger condition instruction is to clear Trigger0.

When the processor core executes the clear trigger instruction, the trigger condition Trigger0 is set low.

The format of the clear trigger instruction can be:

Clear Trigger0

These are the functions of the processor core.

A marker storage unit, configured to cache the output marker list.

The external control condition input unit is used to transmit the externally input trigger condition Trigger0 to the processor core. As mentioned above, the trigger condition Trigger0 can be used as a waiting end condition, a loop condition, and a jump condition.

Here is a specific example.

First output a subset of waveformA (10, 1000), mark output 100 and 200; then repeatedly output waveformB 10 times; then clear the trigger signal Trigger0; then wait for 100 processor cycles; during this period, the outside world can choose to input through external control conditions The unit sets Trigger0 high or does nothing. This affects the final output. Finally, output waveformC or output waveformD according to the trigger condition of Trigger0.

Before this, waveformA~waveformD have been stored in the waveform memory.

To sum up, the above are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (5)

1. one kind is used for the processor that random waveform produces system, it is characterized in that, comprising: processor cores, instruction buffer unit, cycle index indexing unit, Marker flag memory cell, external control condition entry unit;

Instruction buffer unit is used for the instruction set of buffer memory from outer computer;

Processor cores is used for reading and carry out each bar instruction one by one from said instruction set; The instruction set that said processor cores is supported is made up of waveform generation instruction, loop control instruction, condition jump instruction, wait instruction and the instruction of removing trigger condition;

When processor cores is handled the waveform generation instruction, from the waveform generation instruction, extract the waveform segment title, produce the call instruction of respective waveforms section, and send to the store control logic module; The waveform segment data that the store control logic module is read output among the FIFO of self-defined processor external signal conditioning module one by one in order; Also comprise the output token tabulation in the waveform generation instruction; Said output token list storage is in the Marker flag memory cell; Each output token is a numerical value, during processor cores output waveform segment data, and the value in more current output data number and the output token tabulation; If the two is identical, then export a pulse;

When processor cores cycle of treatment steering order, carry out the instruction of appointment according to loop control instruction named order and number of cycles according to cycling condition; Wherein round-robin number of times marker stores is in said cycle index indexing unit;

When the jump instruction of processor cores treatment conditions, judge at first whether the redirect condition is set up, under the situation that condition is set up, carry out the instruction of appointment;

When processor cores is handled the wait instruction, constantly judge and wait for instructing the wait termination condition of appointment whether to satisfy, under situation about satisfying, to carry out subsequent instructions;

When processor cores is handled the instruction of removing trigger condition, be changed to trigger condition Trigger0 low; When said trigger condition Trigger0 when waiting for termination condition and/or cycling condition and/or redirect condition, processor cores judges according to the value of Trigger0 whether corresponding conditions is set up;

Said Marker flag memory cell is used for the said output token tabulation of buffer memory;

Said external control condition entry unit is used for the trigger condition Trigger0 of outside input is transferred to processor cores.

2. processor as claimed in claim 1 is characterized in that, said waveform generation instruction Generate belt collection parameter s ubset (< reference position >, < end position >);

When said processor cores is carried out waveform generation instruction Generate, judge whether belt collection parameter s ubset of Generate, if then export from said reference position of waveform segment extracting data to be exported and the data between the said end position; Otherwise, the waveform segment whole data is exported.

3. processor as claimed in claim 1 is characterized in that, said loop control instruction form is:

The Repeat cycling condition

Code segment A

end?Repeat

Said code segment A is made up of the instruction in the said instruction set;

Said cycling condition comprises following three kinds of situation:

1. said cycling condition is N, and N is a positive integer, and then the Repeat instruction realizes the limited number of time circulation, and said processor cores is carried out code segment A circulation N time;

2. said cycling condition is eternal forever, and then Repeat instruction realizes unlimited circulation, and said processor cores goes down the unconfined circulation of code segment A, up to the processor cores power down or be reset;

3. said cycling condition is " until Trigger0 ", and then Repeat instruction realizes the circulation of script condition, and said processor cores does not stop circulation with code segment A and goes down, till processor detects said Trigger0 and is logic high.

4. processor as claimed in claim 1 is characterized in that, said condition jump instruction form is:

If?Trigger0

Code segment B

Else

Code segment C

End?if

Said code segment B and code segment C form by the instruction in the said instruction set;

When said processor cores is carried out this condition jump instruction, judge at first whether said Trigger0 is logic high, if then code segment B is carried out one time, otherwise code segment C is carried out one time.

5. processor as claimed in claim 1 is characterized in that, said wait order format is:

Wait waits for termination condition

Said wait termination condition comprises following two kinds of situation:

1. said wait termination condition is N, and N is a positive integer; Said processor cores is carried out in the time of should waiting for instruction; To wait for delay counter assignment N; Each processor clock cycle should wait for that delay counter subtracted 1 and judge whether to be 0, if be not equal to 0 then continue to carry out and subtract 1 and decision operation, if equal 0 then carry out subsequent instructions;

2. said wait termination condition is Trigger0; Said processor cores execution is somebody's turn to do when waiting for instruction, does not stop to judge the value of Trigger0 signal, if be to hang down then rest on this wait to instruct always, if be high, then carries out subsequent instructions.

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