CN102067235A - NADN based NMOS NOR flash memory cell, a NADN based NMOS NOR flash memory array, and a method of forming a nand based nmos nor flash memory array - Google Patents

Abstract

A NOR flash nonvolatile memory device provides the memory cell size and a low current program process of a NAND flash nonvolatile memory device and the fast, asynchronous random access of a NOR flash nonvolatile memory device. The NOR flash nonvolatile memory device has an array of NOR flash nonvolatile memory circuits. Each NOR flash nonvolatile memory circuit includes a plurality of charge retaining transistors serially connected in a NAND string. A drain of a topmost charge retaining transistor is connected to a bit line associated with the serially connected charge retaining transistors and a source of a bottommost charge retaining transistor is connected to a source line associated with the charge retaining transistors. Each control gate of the charge retaining transistors on each row is commonly connected to a word line. The charge retaining transistors are programmed and erased with a Fowler- Nordheim tunneling process.

Description

NMOS NOR flash memory unit based on NAND, NMOS NOR flash memory array based on NAND and method for forming the unit and the array

technical field

The invention relates to a non-volatile memory array structure and operation, in particular to a component structure and operation of a NOR flash memory based on NAND.

Background technique

Non-volatile memory is state of the art in this technical field. Types of non-volatile memory include read-only memory (ROM), electronically programmable read-only memory (EPROM), electronically erasable programmable read-only memory (EEPROM), NOR flash memory, and NAND flash memory. Today, flash memory is one of the more prevalent non-volatile memories in applications such as personal digital assistants, cell phones, notebook and portable computers, voice recorders, and global positioning systems. Flash memory has the advantages of high density, small silicon area, low cost, and can be repeatedly programmed and erased using a single low voltage.

Flash memory structures known in the prior art use charge conservation structures such as charge storage and charge extraction. In non-volatile floating gate memory, charges representing digital data are stored on the floating gate of the device in a charge storage structure. The stored charge changes the threshold voltage of the floating gate memory cell to ensure that digital data is stored. In the charge-trapping structure in silicon oxynitride silicon (SONOS) or metal oxynitride silicon (MONOS) type cells, charges are extracted in a charge-trapping layer between double insulating layers. In SONOS and MONOS devices, the charge-trapping layer has a relatively high dielectric constant (k) like silicon nitride (SiNx).

The current non-volatile memory is divided into two categories of products: fast random access asynchronous NOR non-volatile flash memory and slower serial access synchronous NAND non-volatile flash memory. NOR non-volatile flash memory is currently designed as a large pin count memory with multiple external address and data pins and appropriate control signal pins. A disadvantage of the NOR non-volatile flash memory is that when the memory density is doubled, the number of external pins required will increase due to the addition of an external address pin. On the contrary, the advantage of NAND flash memory is that it has fewer pins than NOR and has no address input pins. NAND flash pin counts always remain the same as density increases. As the two mainstreams in today's production, the cell structure of NAND and NOR flash memory both use a charge retention (charge storage or charge extraction) transistor memory cell to store one bit of data as a charge, so it is also usually called It is called a single-level programming cell (SLC). The cell structures of the NAND and NOR flash memories are respectively called one-bit/single-transistor NAND cells or NOR cells, which are used to store single-layer programmed data in the cells.

The advantage of the NAND and NOR non-volatile flash memory is that it can be programmed and erased in the system and has an endurance cycle of at least 100,000 times. In addition, single-chip NAND and NOR flash both offer gigabit densities because the cell size is highly scalable. For example, the current one-bit/single-transistor NAND cell size is maintained at about 4λ ² (λ is the smallest characteristic size in semiconductor technology), while the NOR cell size is about 10λ ² . Also, in addition to storing data in single-level potential programming cells with two threshold voltages (Vt0 and Vt1), single-transistor NAND and NOR flash memory can have four multi-potential threshold voltages (Vt0, Vt1, Vt2) in one physical cell. and Vt3), at least two bits can be stored in each cell or two bits can be stored in each transistor.

Currently, the highest capacity of a single-chip double-layer polysilicon gate NAND non-volatile flash memory is 64Gb. In contrast, a double-layer polysilicon gate NOR non-volatile flash memory has a capacity of 2Gb. The large gap in capacity between NAND flash and NOR flash is due to the fact that the scalability of NAND flash cells is superior to that of NOR flash cells. The drain-to-source voltage (Vds) of a NOR flash memory cell must be 5.0V to maintain a high-current Channel-Hot-Electron (CHE) programming operation. On the contrary, a NAND flash memory cell only needs a drain-to-source voltage of 0.0V for a low-current Fowler-Nordheim tunneling programming operation. The above results make the size of a one-bit/single-transistor NAND cell only half that of a one-bit/single-transistor NOR cell, which makes NAND flash memory suitable for applications that require huge data storage, while NOR flash memory is widely used as a device that requires a small amount of Data is stored but programming code that requires fast and asynchronous random reads is stored in memory.

The two-transistor NOR flash memory cell is formed by two NMOS transistors, and its structure is equivalent to a single-level programming cell. The upper transistor in the transistor NOR cell is a floating gate transistor and the bottom transistor is a conventional NMOS select transistor. Only the upper transistor NAND cell is capable of storing data. A two-transistor NOR flash memory cell has only one transistor for storing data, and in the NOR flash memory cell, each NAND cell corresponds to a selection transistor.

US Patent No. 7,263,003 (Edahiro et al.) describes a two-transistor flash memory using a replica cell array to control the pre-charge/discharge and sense amplifier circuits of the main cell array.

US Patent No. 5,596,523 (Endoh et al.) provides a segment of an array of NOR cell type EEPROM memory cells. Every two adjacent NOR cells are connected to a corresponding bit line, wherein the drain of one memory cell transistor and the source of the other cell transistor are commonly connected to the bit line. Sources and drains of other cell transistors are commonly connected to a source line. The source line is provided by a select transistor.

US Patent No. 6,765,825 (Scott) describes a differential NOR memory cell including dual floating gate transistors. The drain terminal of each transistor is coupled to a corresponding differential bit line. The source terminal of the dual transistor is coupled to a shared current source or sink. Each control gate terminal is coupled to a corresponding word line, which may or may not be the same as the corresponding word lines to which the other control terminals are connected. The floating gate transistor may be a five-terminal device that includes an added well terminal, in which case the set of bit lines used to program the EEPROM memory cell is different from the set of bit lines used to read the EEPROM memory cell. While the drain terminals are coupled to differential read bit lines, each well terminal is coupled to a corresponding differential program bit line.

US Patent Application No. 2006/0181925 (Specht et al.) is an arrangement of non-volatile memory cells. The memory transistors are arranged in rows and columns. The source and drain terminals of the memory transistors of the first column are coupled to conductors of a different metal plane than the first source and drain terminals of the memory transistors of the second column. In this way, it is possible to make the memory transistors of adjacent columns in the memory close to each other.

Contents of the invention

The object of the present invention is to provide a NOR non-volatile flash memory, which has the characteristics of small size and low current programming operation of NAND non-volatile flash memory, and has the characteristics of fast and asynchronous random read operation of NOR non-volatile flash memory .

To achieve the aforementioned objectives, an embodiment of a NOR non-volatile flash memory circuit includes connecting a plurality of charge storage transistors in series to form a NAND string. The drain of the uppermost charge storage transistor is connected to a bit line associated with the series charge storage transistor, while the source of the bottommost charge storage transistor is connected to a source associated with the series charge storage transistor Wire. Each control gate of the plurality of charge conservation transistors on each row is connected to the same word line. The series charge storage transistors are formed in a well of the first conductivity type (P-type triple well). The well of the first type of conductivity is formed within a well of the second type of conductivity (deep N-type well). The deep well of the second type of conductivity is formed in a substrate of the first type of conductivity (P-type substrate).

The programming operation and the erasing operation of the charge storage transistor are operated by Fowler-Nordheim tunneling effect. In order to program a selected one of the charge storage transistors as a single-level programming unit, a voltage of about +15.0 V to about +20.0 V is applied to the selected charge in a gradually increasing manner. Between the control gate of the storage transistor and the bulk region of the charge storage transistor. Those unselected charge storage transistors are suppressed by an intermediate voltage of less than +10.0V applied between the control gates of the unselected charge storage transistors and the bulk region. The size of the NOR flash circuit layout is approximately four times the smallest feature size of the process technology for fabricating the NOR flash circuit.

To erase the selected charge storage transistor, a high voltage of about +15.0V to about +20.0V is applied between the bulk region of the selected charge storage transistor and the control gate. The unselected charge storage transistors are suppressed by biasing the unselected charge storage transistors so that the voltage between the control gates of the unselected charge storage transistors and the bulk region is about 0.0V. transistor.

When reading a selected charge storage transistor from the plurality of charge storage transistors performing programming operation in the single-level programming unit, the source line is connected to a voltage follower sensing circuit. The gate and drain voltages of the selected charge storage transistor are set to the potential of a voltage source (VDD), approximately 1.8V or approximately 3.0V. The gate voltages of all unselected charge storage transistors in the charge storage transistors are set to a first high read voltage greater than 6.0V. If the NOR flash memory circuit is not selected to perform the read operation, the voltage of the control gate of the non-selected charge storage transistor among the charge storage transistors is set to the ground reference voltage to turn off the charge storage transistor. The voltage following sensing circuit is a comparison circuit, and its reference terminal is connected to a reference voltage source. The reference voltage source is set at about 2.0V to differentiate the threshold voltage of the first logic level (0) from the threshold voltage of the second logic level (1).

The source line is connected to a voltage follower sensing circuit when reading a selected charge storage transistor from among the charge storage transistors performing a programming operation in the multi-level programming unit. The gate and drain voltages of the selected charge storage transistors are set to a mid to high potential of approximately 4.0V. The gate voltages of all unselected charge storage transistors in the charge storage transistors are set at a second high read voltage greater than 7.0V. The voltage following sensing circuit includes a plurality of comparison circuits, the number of which is equal to the number of threshold voltages representing data stored in the charge storage transistor minus one. The reference terminal of each comparison circuit is connected to one of a set of reference voltage sources. The reference voltage source is set to a voltage between each threshold voltage to distinguish the data represented by the threshold voltage stored in the charge storage transistor.

In another embodiment, a NOR non-volatile flash memory includes an array of NOR non-volatile flash memory circuits, wherein the charge storage transistors of the NOR flash memory circuits are arranged in columns and rows. Each NOR flash memory circuit includes a plurality of charge storage transistors serially connected in series to form a NAND string on a column. The drain of the uppermost charge storage transistor in each NOR flash memory circuit is connected to a local bit line corresponding to the column in which the NOR flash memory circuit is located. The source of the lowermost charge storage transistor in each NOR flash memory circuit is connected to a local source line corresponding to each NOR flash memory circuit. Each control gate of the charge retention transistors on each row is commonly connected to a word line.

NOR non-volatile flash memory includes an array of voltage control circuits. The column voltage control circuit is connected to a local bit line and a source line corresponding to each column of charge preserving transistors and provides a control signal to a local bit line associated with each column of charge preserving transistors and source lines. Each local bit line is connected to one of multiple global bit lines through a bit line selection transistor, and each local source line is connected to multiple global sources through a source line selection transistor One of the pole lines, the global bit line and the global source line, is connected to the column voltage control circuit to transmit control signals to the selected local bit line and the selected local source line, for NOR non-volatile flash memory Selected charge conservation transistors within the circuit perform read, program, and erase operations.

The NOR non-volatile flash memory includes a row of voltage control circuits. The row voltage control circuit is connected to the word line corresponding to each row of charge retaining transistors and provides a control signal to the word line associated with each row of charge retaining transistors, while the local bit line selects the transistor and the source line The gate of the select transistor is connected to each local bit line. The row control circuit transmits control signals to the word lines for reading, programming and erasing selected charge retention transistors in the NOR flash memory circuit. The row voltage control circuit also transfers control signals to selected bit line select transistors and selected source line transistors to transfer bit line and source line control signals from the column voltage control circuit to selected local bit lines and the selected local source line.

Programming and erasing of the multiple charge conservation transistors is performed by means of a Fowler-Nordheim tunneling effect. When programming a selected charge-storage transistor among the plurality of charge-storage transistors as a single-level potential programming unit, the row voltage control circuit provides a programming voltage applied between the control gate and the body region of the selected charge-storage transistor. voltage to the word line, the programming voltage is about +15.0V to about +20.0V. The row voltage control circuit provides an intermediate voltage less than +10.0V that is applied between the control gates of selected charge storage transistors and the bulk region to inhibit unselected charge storage transistors. The layout requirement of the NOR flash memory circuits is that the size of each NOR flash memory circuit is about four times the minimum characteristic size of the NOR flash memory circuit manufacturing process technology.

When programming a selected charge storage transistor among the plurality of charge storage transistors as a multi-layer potential programming unit, the row voltage control circuit is between the control gate of the selected charge storage transistor and the body region of the charge storage transistor A programming voltage of about +15.0V to about +20.0V is applied to the word line of the selected charge retaining transistor in a gradually increasing manner. The read data of the selected charge-holding transistor is verified each time the programming voltage is increased, until the correct threshold voltage is reached. Unselected ones of the plurality of charge storage transistors are suppressed by a medium to high voltage of less than +10.0V applied between the control gate of the selected charge storage transistor and the bulk region.

To erase the selected charge storage transistor, the row voltage control circuit applies a positive erase voltage of about +15.0V to about +20.0V between the bulk region and the control gate of the selected charge storage transistor. The row voltage control circuit applies a bias voltage on the unselected charge retaining transistors such that there is a voltage of about 0.0 V between the control gate and the bulk region to suppress the unselected ones of the charge retaining transistors.

When a selected charge storage transistor among the plurality of charge storage transistors of the selected NOR flash memory circuit is used as a single-layer potential programming unit to perform a read operation, the source line is connected to a voltage following induction in the column voltage control circuit. circuit. The row voltage control circuit sets the word line, ie, control gate, voltage of the selected charge retention transistor to the voltage source voltage (VDD) of about 1.8V or about 3.0V. The row voltage control enables local bit line select transistors to connect to the global bit line corresponding to the selected charge conservation transistor and the local bit line. Then, the column voltage control circuit sets the voltage of the global bit line, that is, the voltage of the local bit line connected to the drain of the selected charge storage transistor, to the voltage of the voltage source (VDD), the voltage of the voltage source About 1.8V or about 3.0V. The row voltage control circuit sets the word line and the voltage of the control gates of all unselected charge storage transistors in the selected NOR flash circuit to a first read voltage greater than 6.0V. The voltage following sensing circuit is a comparison circuit within the column voltage control circuit, and a reference terminal thereof is connected to a reference voltage source. The voltage of the reference voltage source is set to about 2.0V to distinguish a threshold voltage representing a first logic level (0) from a threshold voltage representing a second logic level (1). The row voltage control circuit sets the voltage of the word line, that is, the voltage of the control gate of the unselected charge storage transistor among the plurality of charge storage transistors in the unselected NOR flash memory circuit as the ground reference voltage, thereby closing the charge storage transistor.

When reading a selected charge storage transistor among the charge storage transistors performing programming operation with the multi-level potential programming unit, the source line is connected to a voltage follower sensing circuit. The gate and drain voltages of selected charge storage transistors are set to a moderately high voltage of about 4.0V. The gate voltages of all unselected charge retaining transistors among the plurality of charge retaining transistors are set to a second high read voltage greater than 7.0V. There are a plurality of comparison circuits in the voltage following sensing circuit, the number of which is equal to the number of threshold voltages representing data stored in the charge storage transistor minus one. A reference terminal of each comparison circuit is connected to one of a set of reference voltage sources. The reference voltage source is set to a voltage between each threshold voltage to distinguish the data represented by the threshold voltage present in the charge storage transistor.

In another embodiment, a method for forming a NOR non-volatile flash memory includes: providing a substrate; setting an array of NOR non-volatile flash memory circuits on the substrate, and making the charge storage transistors of the NOR flash memory circuits arranged in rows and List. Each NOR flash memory circuit is formed by serially connecting charge storage transistors on a column into a NAND string. The drain of the uppermost charge storage transistor in each NOR flash memory circuit is connected to a local bit line corresponding to the column in which the NOR flash memory circuit is located. The source of the lowermost charge storage transistor in each NOR flash memory circuit is connected to a local source line corresponding to the NOR flash memory circuit. Each control gate of the charge retention transistors on each row is commonly connected to a word line.

A method of forming a NOR flash memory includes forming a column voltage control circuit. The column voltage control circuit is used to provide control signals to local bit lines and source lines corresponding to each column of charge conservation transistors. Each local bit line is connected to one of the plurality of global bit lines through a bit line select transistor, and each local source line is connected to one of the plurality of global source lines through a source line select transistor one. In order to read, program and erase selected charge retention transistors within the NOR non-volatile flash memory circuit, the global bit line and the global source line are connected to the column voltage control circuit to transmit control signals to the selected local bit line and selected local source line.

A method of forming a NOR flash memory includes forming a row of voltage control circuits. The row voltage control circuit is used to provide control signals to the word line corresponding to each row of charge conservation transistors and the gates of the local bit line select transistor and source line select transistor connected to each local bit line. The row control circuit transmits control signals to the word lines for reading, programming and erasing selected charge retention transistors within the NOR non-volatile flash memory circuit. The row voltage control circuit also transfers control signals to selected bit line select transistors and selected source line transistors to transfer bit line and source line control signals from the column voltage control circuit to selected local bit line and the selected local source line.

The programming and erasing operations of the plurality of charge storage transistors are performed by means of a Fowler-Nordheim tunneling effect. When programming a selected charge storage transistor among the plurality of charge storage transistors as a single-level potential programming unit, the row voltage control circuit provides a high voltage of about 15.0V to about 20.0V to the word line, and the voltage is applied between the control gate of the selected charge storage transistor and the bulk region. The row voltage control circuit provides an intermediate voltage less than +10.0V that is applied between the control gates of selected charge storage transistors and the bulk region to inhibit a plurality of unselected charge storage transistors. The size of the NOR flash circuit layout is approximately four times the smallest feature size of the process technology for fabricating the NOR flash circuit.

When programming a selected charge retaining transistor among the plurality of charge retaining transistors as a multi-layer potential programming unit, the row voltage control circuit connects the control gate of the selected charge retaining transistor with the bulk region of the charge retaining transistor A programming voltage of about +15.0V to about +20.0V is applied to the word line of the selected charge retaining transistor in a gradually increasing manner. The read data of the selected charge-holding transistor is verified each time the programming voltage is gradually increased until the correct threshold voltage is reached. Unselected ones of the plurality of charge storage transistors are suppressed by an intermediate high voltage of less than +10.0V applied between the control gate of the selected charge storage transistor and the bulk region.

To erase the selected charge storage transistor, the row voltage control circuit applies a positive high erase voltage of about +15.0V to about +20.0V between the bulk region and the control gate of the selected charge storage transistor. The row voltage control circuit also applies a bias voltage on the unselected charge storage transistors so that there is a voltage of about 0.0 V between the control gates of the unselected storage transistors and the bulk region, thereby suppressing the unselected charge storage transistors. selected transistor.

When reading a selected charge storage transistor of a plurality of charge storage transistors in a NOR flash memory circuit as a single-layer potential programming unit, the source line is connected to a voltage follower sensing circuit in the column voltage control circuit. The row voltage control circuit sets the voltage of the word line, ie, the control gate of the selected charge storage transistor, to a voltage source (VDD) of about 1.8V or about 3.0V. The row voltage control circuit activates the local bit line selection transistor to connect the global bit line corresponding to the selected charge storage transistor to the local bit line. The column voltage control circuit then sets the voltage of the global bit line, i.e. the local bit line connected to the drain of the selected charge storage transistor, to a voltage source (VDD) of approximately 1.8V or About 3.0V. The row voltage control circuit also sets the voltage of the word line and the control gates of all unselected charge storage transistors of the plurality of charge storage transistors within the selected NOR flash memory circuit to a first read voltage greater than 6.0V. The row voltage control circuit sets the voltage of the word line, that is, the voltage of the control gate of the unselected charge storage transistors of the plurality of charge storage transistors of the unselected NOR flash memory circuit, to a ground reference voltage to turn off the charge storage transistors. The voltage following sensing circuit is a comparator circuit within the column voltage control circuit, which has a reference terminal connected to a reference voltage source. The voltage of the reference voltage source is set to about 2.0V to distinguish a threshold voltage representing a first logic level (0) from a threshold voltage representing a second logic level (1).

When reading a selected charge storage transistor programmed with a multi-level potential programming unit among the plurality of charge storage transistors, the source line is connected to a voltage follower sensing circuit. The gate and drain voltages of selected charge storage transistors are set to a moderately high voltage of about 4.0V. The gate voltages of all unselected charge storage transistors among the plurality of charge storage transistors are set to a second read voltage greater than 7.0V. The voltage following sensing circuit includes a plurality of comparison circuits, the number of which is equal to the number of threshold voltages representing data stored in the charge storage transistor minus one. A reference terminal of each comparison circuit is connected to one of a set of reference voltage sources. The reference voltage source is set to a voltage between each threshold voltage level to distinguish the data represented by the threshold voltage stored in the charge storage transistor.

Description of drawings

Figure 1a is a top view of a single-transistor floating-gate NMOS NAND flash cell;

Figure 1b is a cross-sectional view of a single-transistor floating-gate NMOS NAND flash cell;

Figure 1c is a schematic diagram of a single-transistor floating-gate NMOS NAND flash cell;

Figure 1d is a distribution diagram of two threshold voltages of a single-transistor floating-gate NMOS NAND flash cell with a negative erasing level and a positive single programming level;

Figure 1e is a distribution diagram of four threshold voltages of a single-transistor floating-gate NMOS NAND flash cell with a negative erasing level and three positive single programming levels;

Figure 2a is a top view of a single-transistor floating-gate NMOS NOR flash cell;

Figure 2b is a cross-sectional view of a single-transistor floating-gate NMOS NOR flash cell;

Figure 2c is a schematic diagram of a single-transistor floating-gate NMOS NOR flash cell;

Figure 2d is a distribution diagram of two threshold voltages of a single-transistor floating-gate NMOS NOR flash cell with a positive erasing level and a positive single programming level;

Figure 2e is a distribution diagram of four critical voltages of a single-transistor floating-gate NMOS NOR flash cell with a positive erasing level and three positive single programming levels;

Figure 3a is a top view of a dual-transistor floating-gate NMOS NOR flash cell with a drain contact connection in the prior art;

Fig. 3b is a sectional view of the double-transistor floating-gate NMOS NOR flash cell in the prior art Fig. 3a;

Fig. 3c is a schematic diagram of the dual-transistor floating-gate NMOS NOR flash cell in Fig. 3a of the prior art;

Figure 3d is a distribution diagram of two threshold voltages of a double-transistor floating-gate NMOS NOR flash cell with a positive erasing level and a positive single programming level;

Figure 3e is a distribution diagram of four critical voltages of a double-transistor floating-gate NMOS NOR flash cell with one positive erasing level and three positive single programming levels;

Fig. 4 a is the schematic diagram of an embodiment of the double-transistor floating gate NMOS NOR flash unit of the present invention;

Fig. 4b-1, Fig. 4b-2, Fig. 4c-1 and Fig. 4c-2 are the top view and cross-sectional view of an embodiment of the double transistor floating gate NMOS NOR flash unit of the present invention;

Fig. 5a-Fig. 5e are the connection schematic diagrams of a segment in the dual-transistor floating gate NMOS NOR flash cell array of the present invention;

6a-6d are critical voltage diagrams of various embodiments of the single-transistor floating-gate NMOS NOR flash unit of the present invention;

Figures 7a-7d are critical voltage diagrams of other embodiments of the double-transistor floating-gate NMOS NOR flash unit of the present invention;

FIG. 8 is a schematic diagram of a NOR non-volatile flash memory component including a dual-transistor floating-gate NMOS NOR flash unit in various embodiments of the present invention;

Fig. 9 is a circuit diagram of the row voltage control circuit of the NOR non-volatile flash memory in Fig. 8;

Fig. 10 is a circuit diagram of the column voltage control circuit of the NOR non-volatile flash memory in Fig. 8;

Fig. 11a is a schematic diagram of a single-layer potential programming voltage following sensing circuit in the double-transistor floating-gate NMOS NOR flash unit of the present invention;

Figure 11b is a single-layer potential programming reading bias table in the double-transistor floating-gate NMOS NOR flash unit of the present invention;

Fig. 11c is a schematic diagram of a multi-layer potential programming voltage following sensing circuit in the double-transistor floating-gate NMOS NOR flash unit of the present invention;

Figure 11d is a multi-layer potential programming reading bias table in the double-transistor floating-gate NMOS NOR flash unit of the present invention;

Figure 12a-Figure 12e is the erasing bias table of the double transistor floating gate NMOS NOR flash unit of the present invention;

Fig. 13a-Fig. 13b are the programming bias table of double transistor floating gate NMOS NOR flash unit of the present invention;

14a-14b are flow charts for forming NOR non-volatile flash memory components; and

FIG. 15 is a schematic diagram of an embodiment of a multi-transistor floating-gate NMOS NOR flash unit of the present invention.

Detailed ways

FIG. 1a is a top view of an NMOS NAND flash floating gate transistor 10. FIG. 1b is a cross-sectional view of the NMOS NAND flash floating gate transistor 10. FIG. 1c is a schematic diagram of the NMOS NAND flash floating gate transistor 10. In the common structure of the NAND cell string formed by the NMOS NAND flash floating gate transistor 10, the drain 15 or the source 20 of the NMOS NAND flash floating gate transistor 10 does not need a contact. In prior art NAND cell strings, the uppermost transistors are connected to a top select transistor and the lowest transistors are connected to a bottom select transistor. The contacts of the drain of the top selection transistor and the source of the bottom selection transistor are connected to a bit line (Bitline, BL) and a source line. The structure of this prior art NAND cell string makes the size of the NMOS NAND flash floating gate transistor 10 the smallest in the non-volatile flash memory structure.

The NMOS NAND flash floating gate transistor 10 is formed on the uppermost layer of a P-type substrate (PSUB) 40 . An N-type material is diffused to form a deep N-well (DNW) 35 on the surface of the P-type substrate 40 . Then a P-type material is diffused on the surface of the deep N-well 35 to form a P-well 30 (commonly called triple P-well, triple P-well TPW). Then an N-type material is diffused into the surface layer of the P well 30 to form the drain (D) 15 and the source (S) 20 . A first polysilicon layer forms floating gate 45 on P-well 30 over the bulk region between drain 15 and source 20 . A second polysilicon layer is formed over the floating gate 45 to form the control gate (G) 25 of the NMOS NAND flash floating gate transistor 10 . The gate length of the NMOS NAND flash floating gate transistor 10 is the channel of the body region of the P well 30 between the drain 15 and the source 20 . The channel width of the NMOS NAND flash floating gate transistor 10 is determined by the width of the N diffusion of the drain 15 and the source 20 . The general cell size of the NMOS NAND flash floating gate transistor 10 is about 4λ ² , wherein the X-axis is 2λ long and the Y-axis is 2λ long. Dimension Lambda (λ) is the smallest dimension of the geometry that can be achieved in manufacturing.

Electronic charges are stored in the floating gate layer 45 to change the threshold voltage of the NMOS NAND flash floating gate transistor 10 . The P-type substrate 40 is connected to a ground reference voltage source (GND) in operation. The deep N-well 35 is connected to a voltage source (VDD). In the current design of the NMOS NAND flash floating gate transistor 10, the power supply voltage is 1.3V or 3.0V. The triple P-well 30 is connected to a ground reference voltage source during normal read operation.

The NMOS NAND flash floating gate transistors 10 are arranged in rows and columns in the array. The second polysilicon layer, that is, the control gate 25 of the NMOS NAND flash floating gate transistor 10 is extended to form a word line, and the word line is connected to each NMOS NAND flash floating gate transistor 10 on the array row.

电子在福勒-诺德海姆(Fowler-Nordheim)通道编程和福勒-诺德海姆通道擦除期间穿过隧道氧化物50。福勒-诺德海姆通道擦除在现有技术的NAND操作中，储存的电子从浮栅45被射出并穿过隧道氧化物50到单元通道区32，最后进入三重P井30中。A tunnel oxide 50 is formed over the channel region 32 between the drain 15 and the source 20 and between the floating gate 45 . The typical thickness of the tunnel oxide 50 is

Electrons travel through the tunnel oxide 50 during Fowler-Nordheim channel programming and Fowler-Nordheim channel erasing. Fowler-Nordheim Channel Erase In prior art NAND operations, stored electrons are ejected from the floating gate 45 and pass through the tunnel oxide 50 to the cell channel region 32 and finally into the triple P-well 30 .

Figure 1d is a double-critical voltage distribution table for programming potential and erasing potential of a single-transistor floating-gate NMOS NAND flash cell. After the erasing operation on the floating gate 45 , the charge of the electrons decreases so that the threshold voltage of the NMOS NAND flash floating gate transistor 10 decreases. Normally, the critical voltage of the NMOS NAND flash floating gate transistor 10 after being erased is about -2.0V. In contrast, during Fowler-Nordheim channel programming, electrons are drawn to floating gate 45, causing the threshold voltage of NMOS NAND flash floating gate transistor 10 to increase to approximately +2.0V. Conventionally, a threshold voltage (Vt0) of approximately -2.0V after an erase operation is designated as a logic data value "1", and a threshold voltage (Vt1) of +2.0V after a programming operation is designated as a logic data value "0".

The removal of electrons is difficult to control, so in an array, the removal of electron charges from the floating gate during the erasing of the Fowler-Nordheim channel is generally done in one page (512B) or one sector (64KB) The cells perform collectively and the erase threshold voltage (Vt0) has a wider distribution. In contrast, the programming operation injects electrons into the floating gate in a controlled manner and is performed on a bit-by-bit basis (one NMOS NAND flash floating-gate transistor 10 at a time through the bit line connected to the drain 15 execution), so that the distribution of the programming threshold voltage (Vt1) is smaller than that of the erasing threshold voltage (Vt0) and is controlled within 0.5V. Since the widely distributed critical voltage (Vt0) of the erased state and the narrowly distributed critical voltage (Vt1) of the programmed state stored in each NAND cell are two obviously different critical voltages, if the NMOS NAND flash floating gate transistor 10 only stores A bit of binary data is called a single-level potential programming or SLC (Single-Level-Cell); NMOS NAND flash floating gate transistor 10 stores one bit of data, which is called a unit single transistor (single-bit-cell). one-transistor, 1b1T) NMOS NAND flash floating gate unit.

Figure 1e is a distribution table of four threshold voltages of a single-transistor floating-gate NMOS NAND flash cell with one erase potential and three program potentials. In the prior art, by changing the programming conditions, more than two critical voltages can be formed according to the charge quantity of the floating gate 45 in the NMOS NAND flash floating gate transistor 10, which generally refers to the multi-layer NMOS NAND flash floating gate unit. Potential programming or MLC (multi-level cell). In this embodiment, there are four threshold voltages that can be programmed in the NMOS NAND flash floating gate transistor 10. The most negative threshold voltage Vt0 is the erase voltage, which has a nominal value of -2.0V and is used to store a logic data value "11". The most negative threshold voltage Vt0 has the widest distribution among the threshold voltages (Vt0, Vt1, Vt2, and Vt3) since it is the only erase state, ie, removes electron charges. Since the other three threshold voltages (Vt1, Vt2 and Vt3) add electrons to the floating gate in a more controllable manner from the erased state, they have narrower distributions in the programmed state. Three positive, narrow programming threshold voltages are sufficiently separated to be detected. In this embodiment, the first Vt1 of the three threshold voltages has a nominal value of about +1.0V for storing a logic data value "10". The second Vt2 of the three threshold voltages Has a nominal value of approximately +2.0V for storing a logical data value "01". The third Vt3 of the three threshold voltages has a nominal value of approximately +3.0V for storing a logical data value of "00". Because each NMOS NAND flash floating gate transistor 10 stores four distinct critical voltage states, each NMOS NAND flash floating gate transistor 10 also stores two bits of binary data and is referred to as a two-bit single-transistor NMOS NAND Flash unit (2b/1T).

The standard values of the threshold voltages (Vt0, Vt1, Vt2 and Vt3) of the NMOS NAND flash floating gate transistor 10 may vary by more than 1.0V in different designs. The distribution between the two-bit data value and the four critical voltage states can also be changed between different NMOS NAND flash floating gate cell designs. For example, some NMOS NAND flash floating gate cell designs assign the logic data value "01" to the first positive threshold voltage Vt1, the logic data value "10" to the second positive threshold voltage Vt2, or the negative erase threshold voltage Vt0 may be assigned to a logic data value "00", and the threshold voltage Vt3 of the third positive electrode may be assigned to a logic data value "11".

FIG. 2 a is a top view of an NMOS NOR flash floating gate transistor 110 . FIG. 2b is a cross-sectional view of the NMOS NOR flash floating-gate transistor 110. FIG. 2c is a schematic diagram of the NMOS NOR flash floating gate transistor 110. The NMOS NOR flash floating gate transistor 110 is formed in the uppermost surface layer of the triple P-type substrate 140 . An N-type material diffuses into the surface layer of the P-type substrate 140 to form a deep N-well 135 . Then, a P-type material diffuses into the surface layer of the deep N-well 135 to form the P-well 130 (commonly referred to as triple P-well). Then, N-type material is diffused into the surface layer of the P-well 130 to form the drain (D) 115 and the self-aligned source (S) 120 . The first polysilicon layer forms a floating gate 145 on the P-well 130 over the bulk region between the drain 115 and the source 120 . A second polysilicon layer is formed over the floating gate 145 to form the control gate (G) 125 of the NMOS NOR flash floating gate transistor 110 . The self-aligned source 120 is self-aligned between two adjacent second polysilicon layers of the two control gates 125 of the two NMOS NOR flash floating gate transistors 110 . The self-aligned source 120 is generally used to reduce the distance between the source lines of the NMOS NOR flash floating gate transistor 110 .

The gate length of the NMOS NOR flash floating gate transistor 110 is equal to the channel region 132 of the body region on the P-well 130 between the drain 115 and the source 120 . The channel width of the NMOS NOR flash floating gate transistor 110 is determined by the width of the N diffusion of the drain 115 and the source 120 . The typical cell size of the NMOS NOR flash floating gate transistor 110 is about 10λ ² , where the X-axis is 2.5λ long and the Y-axis is 4λ long.

The floating gate 145 stores electron charges to change the threshold voltage of the NMOS NOR flash floating gate transistor 110 . The P-type substrate 140 is connected to a ground reference voltage source (GND) in operation. The deep N-well 135 is connected to a voltage source (VDD) during read and program operations, however, its voltage is around +10V during Fowler-Nordheim channel erase operations. In the current design of the NMOS NOR flash floating gate transistor 110, the power supply voltage is 1.3V or 3.0V. The triple P-well 130 is connected to a ground reference voltage during normal read and program operations, however, its voltage is approximately +10V during erase operations. In other words, during the Fowler-Nordheim channel erase operation, the deep N well 135 and the triple P well 130 have the same bias voltage, which is about +10V, to avoid the deep N well 135 and the triple P well 130 The forward leakage current of the P/N node between.

NMOS NOR flash floating gate transistors 110 are arranged in rows and columns in the array. The second polysilicon layer, the control gate 125 of the NMOS NOR flash floating gate transistor 110, extends to form a word line connected to each NMOS NOR flash floating gate transistor 110 on the array row.

电子电荷在高电流通道热电子编程过程和低电流的福勒-诺德海姆通道擦除过程中穿过隧道氧化物150。在现有技术的NOR操作中，福勒-诺德海姆通道擦除操作把储存的电子从浮栅145射出并穿过隧道氧化物150到单元通道区132，最后进入三重P井130中。A tunnel oxide 150 is formed over the channel region 132 between the drain 115 and the source 120 and between the floating gate 145 . The typical thickness of the tunnel oxide 150 is

Electron charges pass through the tunnel oxide 150 during hot electron programming for high current channels and erasing for Fowler-Nordheim channels at low currents. In the prior art NOR operation, the Fowler-Nordheim channel erase operation ejects the stored electrons from the floating gate 145 through the tunnel oxide 150 to the cell channel region 132 and finally into the triple P-well 130 .

After the erase operation, the reduction of electron charge stored in the floating gate 145 causes the first threshold voltage (Vt0) of the NMOS NOR flash floating gate transistor 110 to decrease to approximately less than 2.5V. In contrast, in a channel hot electron programming operation, electrons are drawn into the floating gate 145 such that the second threshold voltage (Vt1) of the NMOS NOR flash floating gate transistor 110 is set to approximately greater than 4.0V. Both the wide distribution of the first threshold voltage (Vt0) in the erase state and the narrow distribution of the second threshold voltage (Vt1) in the program state are set to positive to avoid any negative polarity due to NMOS NOR flash floating gate transistor 110. erroneous read operation caused by the threshold voltage.

Figure 2d is a dual-threshold voltage distribution table for a single-transistor floating-gate NMOS NOR flash cell with a single-layer programming potential. After the erasing operation on the floating gate 145 , the charge of electrons decreases so that the threshold voltage of the NMOS NOR flash floating gate transistor 110 decreases. Normally, after the NMOS NOR flash floating gate transistor 110 is erased, the maximum threshold voltage is about +2.5V. In contrast, in channel hot electron programming, electrons are drawn into floating gate 145 such that the threshold voltage of NMOS NOR flash floating gate transistor 110 is increased to at least about +4.0V. Conventionally, a critical voltage (Vt0) of approximately +2.5V after an erase operation is designated as a logic data value "1", and a critical voltage (Vt1) of +4.0V after a program operation is designated as a logic data value "0" . Like the NMOS NAND flash floating gate transistor, the NMOS NOR flash floating gate transistor 110 storing unit data is called a unit single transistor NMOS NOR flash floating gate unit (1b1T).

Figure 2e is a table of four threshold voltage distributions for a single-transistor floating-gate NMOS NOR flash cell with one erase potential and three program potentials. In the prior art, by changing the programming conditions and according to the amount of charge on the floating gate 145 in the NMOS NOR flash floating gate transistor 110, more than two critical voltages can be formed, which is generally called NMOS NOR flash floating gate Multilevel potential programming of cells or multilevel potential programming of cells. In this embodiment, there are four threshold voltages that can be programmed in the NMOS NOR flash floating gate transistor 110 . The minimum positive wide distribution threshold voltage Vt0 is the erase voltage, which has a maximum value of +2.5V and is used to store a logic data value “11”. The other three positive narrow programming threshold voltages are sufficiently separated to allow correct detection. In this embodiment, the first Vt1 of the three threshold voltages has a standard value of about +3.5V and is used to store a logic data value “10”. The second Vt2 of the three threshold voltages has a nominal value of about +4.5V and is used to store a logic data value "01". The third Vt3 of the three threshold voltages has a standard value of about +5.5V and is used to store a logic data value "00". Since each NMOS NOR flash floating gate transistor 110 stores four distinct positive threshold voltage states, and each NMOS NOR flash floating gate transistor 110 stores two binary data bits, it is called a dual-bit single transistor NMOS NOR flash unit (2b/1T).

The standard values of the threshold voltages Vt1 and Vt2 of the NMOS NOR flash floating gate transistor 110 may vary by more than 1.0V in different designs. The standard values of the threshold voltages Vt0 and Vt3 may have a wider threshold voltage distribution. For example, the first threshold voltage Vt0 may vary from about 1.0V to about 2.5V. The fourth threshold voltage Vt3 can have a wider distribution, but it must be greater than about 4.5V to ensure that the NMOS NOR flash floating gate transistor 110 is in a non-conducting state. As mentioned above for the NMOS NAND flash floating gate unit, the distribution of the two-bit data values corresponding to the four critical voltage states can also vary between different NMOS NOR flash floating gate unit designs.

"Intel StrataFlash ^™ Memory Technology Overview," by Atwood et al., Intel Technology Journal, Vol. 1, No. 2, Q41997, www.intel.com, April 23, 2007, "Intel StrataFlash ^™ Memory Technology Development and Implementation," Fazio et al., Intel Technical Journal, Vol. 1, No. 2, Q4 1997, www.intel.com, April 21, 2009, "ETOX ^TM Flash Memory Technology: Scaling and Integration Challenges," Fazio et al. Journal, Volume 6, Number 2, May 2002, www.intel.com, April 21, 2009, discusses a floating-gate ETOX ^TM flash memory transistor whose structure can be formed as shown in Figures 3a-3e NMOS NOR flash cells. Figure 3a is a top view of a two-transistor floating-gate NMOS NOR flash cell. FIG. 3b is a cross-sectional view of the dual-transistor floating-gate NMOS NOR flash cell. FIG. 3c is a schematic diagram of the dual-transistor floating-gate NMOS NOR flash cell. The two-transistor floating-gate NMOS NOR flash cell 210 is formed in the uppermost surface layer of the P-type substrate 240 . An N-type material is diffused into the surface layer of the P-type substrate 240 to form the drains (D) 215a, 215b and self-aligned sources (S) 220 of the double floating gate transistors 205a, 205b. Self-aligned source (S) 220 is shared by dual floating gate transistors 205a and 205b. A first polysilicon layer forms floating gates 245 a and 245 b over bulk regions 230 a and 230 b between drains 215 a and 215 b and self-aligned source 220 . A second polysilicon layer forms control gates (G) 225a and 225b of dual floating gate transistors 205a and 205b over floating gates 245a and 245b. The self-aligned source 220 is formed in self-alignment between two adjacent second polysilicon layers in the two control gates 225a and 225b of the pair of double floating gate transistors 205a and 205b. Self-aligned source 220 is generally used in NMOS NOR flash floating gate transistor 210 to reduce the distance between source lines.

Each drain 215a and 215b has a metal contact 250a and 250b, respectively. The two metal contacts 250 a and 250 b are commonly connected to a metal bit line 255 .

FIG. 3d is a double-threshold voltage distribution table for the dual-transistor floating-gate NMOS NOR flash cell 210 with a single-layer programming potential. The electron charge of the floating gate 245 is reduced after the erase operation, so that the threshold voltage of the dual floating gate transistors 205a and 205b is lowered. In contrast, during channel hot electron programming, electrons are drawn into the floating gates 245a and 245b, so that the threshold voltage of the dual floating gate transistors 205a and 205b increases. Conventionally, the threshold voltage (Vt0) after erasing is designated as a logic data value "1" and the threshold voltage (Vt1) after programming is designated as a logic data value "0". The dual floating gate transistors 205a and 205b store two bits of data, which is called a dual bit dual transistor NMOSNOR flash floating gate cell (2b2T).

FIG. 3e is a table of four threshold voltage distributions for a two-transistor floating-gate NMOS NOR flash cell 210 with one erase potential and three program potentials. In the prior art, by changing the programming conditions and according to the amount of charge on the floating gate 245 in the dual-transistor floating-gate NMOS NOR flash unit 210, more than two critical voltages can be formed, which is generally referred to as a dual-transistor floating-gate NMOS The multilevel potential programming of the NOR flash cell 210 or the multilevel potential programming unit. In this embodiment, there are four threshold voltages that can be programmed at the dual floating gate transistors 205a and 205b. The minimum positive threshold voltage Vt0 is the erasing voltage for storing a logic data value “11”. The other three positive programming threshold voltages are sufficiently separated to allow proper detection. In this embodiment, the first voltage Vt1 of the three threshold voltages stores a logic data value “10”. The second voltage Vt2 of the three threshold voltages stores a logic data value "01". The third voltage Vt3 of the three threshold voltages stores a logic data value "00". Since each dual-transistor floating-gate NMOS NOR flash cell 210 stores four distinct critical voltage states, and each dual-transistor floating-gate NMOS NOR flash cell 210 stores two bits of binary data, it is called a dual-bit single-transistor NMOS. NOR flash unit (2b/1T).

The standard values of the threshold voltages Vt1 and Vt2 of the two-transistor floating-gate NMOS NOR flash cell 210 may also vary in different designs. The standard values of the threshold voltages Vt0 and Vt3 can have a wider threshold voltage distribution. As mentioned above for the NMOS NAND flash floating gate unit, the distribution of the two-bit data values corresponding to the four critical voltage states can also vary between different NMOS NOR flash floating gate unit designs.

FIG. 4a is a schematic diagram of an NMOS NOR flash memory unit 400 of the present invention. 4b-1 and 4c-1 are top views of NMOS NOR flash memory unit 400. 4b-2 and 4c-2 are cross-sectional views of NMOS NOR flash memory cell 400. The floating gate type NMOS NOR flash memory cell 400 is formed on the uppermost surface layer of the P-type substrate 440 . An N-type material diffuses into the surface layer of the P-type substrate 440 to form the deep N-well 435 . Then, a P-type material diffuses into the surface layer of the deep N-well 435 to form the P-well 430 (commonly referred to as triple P-well). Then, the N-type material is diffused into the surface layer of the P well 430 to form the drain (D) 415 of the NMOS NAND flash floating gate transistor 405a, the source of the NMOS NAND flash floating gate transistor 405b and the self-aligned source/source Drain (S/D) 420 . The source/drain 420 is the source of the NMOS NAND flash floating gate transistor 405a and the drain of the NMOS NAND flash floating gate transistor 405b. A first polysilicon layer in the body region between the drain 415 and the source 420 of the NMOS NAND flash floating gate transistor 405a of the P well 430 and the drain 420 and the source 422 of the NMOS NAND flash floating gate transistor 405b Floating gates 445a and 445b are formed above. The second polysilicon layer forms the control gates (G) 425a and 425b of the NMOS NAND flash floating gate transistors 405a and 405b over the floating gates 445a and 445b. The self-aligned source/drain 420 is formed in self-alignment between the second polysilicon layer adjacent to the two control gates 425a and 425b of the NMOS NAND flash floating-gate transistors 405a and 405b. Self-aligned source 420 is commonly used for NMOS NAND flash floating gate transistors 405a and 405b to reduce the distance between source lines.

The gate lengths of the NMOS NAND flash floating gate transistors 405a and 405b are the drain 415 and the source 420 of the NMOS NAND flash floating gate transistor 405a in the P well 430 and the drains 420 of the NMOS NAND flash floating gate transistors 405a and 405b and source 422 in the body region of the channel. The channel width of the NMOS NOR flash floating gate transistor 410 is determined by the width of the drain 415 , source 422 and source/drain 420N diffusions. The typical cell size of the two-transistor NMOS NOR flash memory cell 400 is between about 12λ ² and about 14λ ² , so the effective size of a one-bit NOR cell is about 6λ ² . The effective size (6λ ² ) of the one-bit NOR cell is slightly larger than that of a prior art NAND cell. However, the effective size of the one-bit NOR cell is much smaller than that of the prior art NOR cell size (10λ ² ) using semiconductor fabrication technology larger than 50nm. The aforementioned NOR cell structure size is expected to increase to 15λ ² due to the scaling factors of sub-50nm semiconductor fabrication. The effective unit/single transistor size of the NMOS NOR flash memory cell 400 remains unchanged at an effective cell size of approximately ^6λ2 . The constant cell size is due to the same scaling as state-of-the-art NMOS NAND flash memory cells.

The floating gates 445a and 445b respectively store electron charges to change the threshold voltage of the NMOS NAND flash floating gate transistors 405a and 405b. In all operations such as read operations, program operations and erase operations, the P-type substrate 440 is always connected to the ground reference voltage (GND). The deep N-well 435 is connected to the supply voltage (VDD) during read and program operations, however, it is connected to approximately +20V during the Fowler-Nordheim channel erase operation. In the current design of NMOS NOR flash memory cell 400, the voltage source is 1.8V or 3.0V. Same as the deep N-well bias conditions, the triple P-well 430 is connected to a ground reference voltage source during normal read and program operations, but is connected to a voltage of approximately +20V.

NMOS NAND flash floating gate transistors 405a and 405b are arranged in columns and rows in their array. The second polysilicon layer, that is, the control gates 425a and 425b of the NMOS NAND flash floating gate transistors 405a and 405b are extended to form a word line connected to each NMOS NAND flash floating gate transistor 405a and 405b on a column in the array. 405b.

在福勒-诺德海姆通道编程操作和擦除操作期间，电子电荷流经隧道氧化物。在现有技术中的NOR操作中，福勒-诺德海姆通道擦除操作把储存的电子从浮栅445a和445b射出并穿过隧道氧化物到单元通道区432a和432b，最后进入三重P井430中。A tunnel oxide is above and floating on the channel regions 432a and 432b between the drain 415 and the source 420 of the NMOS NAND flash floating gate transistor 405a and the drain 420 and the source 422 of the NMOS NAND flash floating gate transistor 405b. between gates 445a and 445b. The typical thickness of the tunnel oxide is

During Fowler-Nordheim channel programming and erasing operations, electronic charges flow through the tunnel oxide. In prior art NOR operation, the Fowler-Nordheim channel erase operation ejects the stored electrons from the floating gates 445a and 445b through the tunnel oxide to the cell channel regions 432a and 432b, and finally into the triple P Well 430 in.

After the erase operation, the reduction of electronic charge stored in the floating gates 445a and 445b causes the first threshold voltage (Vt0) of the NMOS NAND flash floating gate transistors 405a and 405b to decrease. In contrast, in a Fowler-Nordheim channel programming operation, electrons are drawn into floating gates 445a and 445b, so that the second threshold voltage level (Vt1) of NMOS NAND flash floating gate transistors 405a and 405b is set to a relatively high voltage.

Fig. 5a-Fig. 5e are the top views of the line connection of one segment of the array formed by the serial connection of the double-transistor floating-gate NMOS NOR flash cells of the present invention. The segment contains four rows and twelve columns of two-transistor NMOS NOR flash memory cells 400, or eight rows of a matrix of NMOS NAND flash floating-gate transistors 405a and 405b. Each NMOS NOR flash memory cell 400 has N+ diffused drain 415, source/drain 420 and source 422 as shown in Figure 4a, Figure 4b-1, Figure 4b-2, Figure 4c-1 and Figure 4c-2. Control gates 425a and 425b are connected to word lines WL0 450a and WL1 450b. Bit lines 455a and 455b and source lines 460a and 460b are formed as the first level metal (455a and 460b) or the second level metal (455b and 460a) of FIGS. 4b-2 and 4c-2.

In FIG. 5b, the connection of the local Metal 1 bit line to the local Metal 2 bit line and the connection of the local Metal 1 source line to the local Metal 2 source line are realized through vias (Via1). In Figure 5c, the connection between the local Metal 2 bit line of the next layer and the local Metal 3 bit line and the connection between the local Metal 2 source line and the local Metal 3 source line are through vias (VIA2 ) realized. In Fig. 5d, the connection of the local Metal 3 bit line to the local Metal 4 bit line on the next layer and the connection of the local Metal 3 source line to the local Metal 4 source line are through via holes ( VIA3) achieved. In Figure 5e, the connection of the local Metal 4 bit line to the local Metal 5 bit line on the next layer and the connection from the local Metal 4 source line to the local Metal 5 source line are through vias (VIA4) Achieved. A matrix of NMOS NOR flash memory cells 400 of twelve local bit lines 455a, 455b and twelve local source lines 460a, 460b can be successfully connected using only five layers of metal with an effective cell size of about ^6λ2 together. Each global bit line and each global source line are shared by two local bit lines 455a and 455b and local source lines 460a and 460b, respectively.

In the structure depicted in Figures 5a-5e, there are five layers of metal lines to create a cell configuration such that the effective size of a unit cell transistor NOR cell is approximately ^6λ2 . The spacing between metal lines can be larger in the horizontal or x-axis direction, or the NAND string can include three or more floating gate transistors to reduce the metal layers to less than five. There is a trade-off between the number of metal layers and the number of NAND strings and the spacing of the metal lines in the horizontal or x-axis direction. The more the number of NAND strings and the looser the x-axis direction, the less the metal layer.

6a-6d are critical voltage diagrams of various embodiments of the single transistor of the double-transistor floating-gate NMOS NAND flash unit of the present invention. Fig. 6 a is the threshold of an embodiment of NMOS NAND flash floating gate transistors 405a and 405b in Fig. 4a, Fig. 4b-1, Fig. 4b-2, Fig. 4c-1 and Fig. 4c-2 performing programming operation and erasing operation Schematic diagram of voltage levels. In this embodiment, a positive programming threshold voltage (Vt1) has a narrow distribution, which represents logic data "0", and a negative programming threshold voltage (Vt0) also has a narrow distribution, which represents logic data "1". . Vt0 and Vt1 have superior narrow distribution threshold voltages in the programming state. In the erase operation of the NMOS NAND flash floating gate transistors 405a and 405b, a voltage of +20V is applied to the triple P-well 430 where the NMOS NAND flash floating gate transistors 405a and 405b are located, and the ground reference voltage (0V) is applied on the selected control gates 425a and 425b of the selected NMOS NAND flash floating gate transistors, and on the selected control gates 425a and 425b and the channel regions 432a and 425b of the selected NMOS NAND flash floating gate transistors 405a and 405b A voltage difference of 20V is formed between 432b to generate the negative Fowler-Nordheim channel tunneling effect. Since the erasing operation of the NOR flash memory array is customarily performed in units of 64 KB in the NOR flash memory array block, the negative critical voltage (Vt0) is generally considered to be a collective erasing state.

In the prior art, the threshold voltage (Vt0) of the NAND flash memory array has a wide voltage distribution. Conventionally, the negative threshold voltage (Vt0) has a voltage range of about 2.0V, that is, varies from -2.0V to about 0.0V. The programming voltage of the threshold voltage (Vt1) is about +2.5V, which varies from +2.0V to +3.0V. The positive threshold voltage (Vt1) does not need a narrow 0.5V distribution in circuit operation, as long as it is less than the 6.0V pass voltage of the unselected word lines in the selected NAND flash array block during the page program operation.

Unlike the synchronously slow 20us linear read speed specification of a page of 512-bit NAND flash memory array, the fast, random and asynchronous read speed of NOR flash memory devices is less than 100ns. In view of the above-mentioned requirements for the speed of the double-bit/double-transistor of the NMOS NOR flash memory unit 400, when the NMOS NAND flash floating-gate transistors 405a and 405b are connected in series, the optimal negative critical voltage (Vt0) and positive critical voltage (Vt1) The threshold voltage distribution is within about 0.5V. The threshold voltage (Vt0) of the negative electrode has a standard voltage of about -0.5V, and the threshold voltage (Vt1) of the positive electrode has a standard voltage of about +3.0V. In order to have a narrow threshold voltage distribution between the negative critical voltage (Vt0) and the positive critical voltage (Vt1), the negative critical voltage (Vt0) and the positive critical voltage (Vt1) can be adjusted by using bit by bit positive voltage The Le-Nordheim channel is programmed to operate. The threshold voltage (Vt0) state of the cathodes of the NMOS NAND flash floating gate transistors 405a and 405b can be achieved through two steps. The first step is to perform a negative Fowler-Nordheim channel collective erase with a wide negative threshold voltage (Vt0) distribution in a page or block, and the second step is to use a positive one-bit A Fowler-Nordheim channel is programmed to obtain a narrow negative threshold voltage (Vt0). According to the integrated circuit manufacturing process, the threshold voltage (Vt1) of the anodes of the selected NMOS NAND flash floating gate transistors 405a and 405b can be narrowed by a single step, that is, gradually increased from about +15.0V to about +20V. Select the programming voltage of the control gates 425a and 425b. For the NMOS NAND flash floating gate transistors 405a and 405b, both the negative threshold voltage (Vt0) and the positive threshold voltage (Vt1) have a narrow programming state distributed around 0.5V.

Fig. 6 b is the second embodiment of the programming operation and the erasing operation of NMOS NAND flash floating gate transistors 405a and 405b in Fig. 4a, Fig. 4b-1, Fig. 4b-2, Fig. 4c-1 and Fig. 4c-2 Threshold voltage graph. In this single potential cell (SLC) embodiment, both the first threshold voltage (Vt0) and the second threshold voltage (Vt1) are positive and have a threshold voltage distribution of about 0.5V. The first threshold voltage (Vt0) of the positive pole is also accomplished through two steps: the first step is to perform the Fowler-Nordheim channel collective erase operation of the negative pole, and the second step is to perform the Fu The Le Nordheim channel is programmed bit by bit. Both the first threshold voltage ( Vt0 ) and the second threshold voltage ( Vt1 ) are programmed states instead of an erased state and a programmed state.

The first threshold voltage (Vt0) is set to be positive with a standard value of 0.5V and a narrow 0.5V distribution, ie from about +0.75V to about +1.25V, for storing a logic data "1". The second threshold voltage ( Vt1 ) is positive with a standard value of 3.0V and a narrow distribution from about +2.75V to about +3.25V for storing a logic data "0". In some embodiments, NOR flash memory needs to have a wider threshold voltage distribution from +2.5V to +3.5V according to speed considerations in some applications.

Fig. 6c is the programming operation of NMOS NAND flash floating gate transistor 405a and 405b among Fig. 4a, Fig. 4b-1, Fig. 4b-2, Fig. 4c-1 and Fig. 4c-2 and another embodiment of erasing operation Threshold voltage graph. This embodiment is for a multi-potential cell (MLC) in which all four threshold voltage levels (Vt0, Vt1, Vt2 and Vt3) have a narrow distribution of about 0.5V whether they are positive or negative. In this embodiment, the first threshold voltage (VT0) is negative and is also entered into the programmed state by using the two-step write method as described earlier, meaning that the first threshold voltage level (VT0) has a margin of approximately 0.5V. Standard values and distributions varying from about -0.25V to about -0.75V are used to store a logical data "11". The second threshold voltage (VT1) is the second data state stored in the NMOS NAND flash floating gate transistors 405a and 405b, which has a nominal value of about +1.0v. The distribution of the second threshold voltage ( VT1 ) varies from about +0.75V to about +1.25V, and is used to store a logic data "10". The third threshold voltage (Vt2) is the third data state of the NMOS NAND flash floating gate transistors 405a and 405b, and has a nominal value of approximately +2.0V. The distribution of the third threshold voltage ( Vt2 ) varies from about +1.75V to about +2.25V, and is used to store a logic data “01”. The fourth threshold voltage (Vt3) is the fourth data state of the NMOS NAND flash floating gate transistors 405a and 405b, and has a nominal value of approximately +3.0V. The distribution of the fourth threshold voltage level (Vt3) varies from about +2.75V to about +3.25V, and is used to store logic data "00".

Fig. 6d is the threshold voltage of another embodiment of NMOS flash floating gate transistors 405a and 405b in Fig. 4a, Fig. 4b-1, Fig. 4b-2, Fig. 4c-1 and Fig. 4c-2 performing programming operation and erasing operation picture. The first threshold voltage ( VT0 ), the second threshold voltage ( VT1 ), the third threshold voltage ( Vt2 ) and the fourth threshold voltage ( Vt3 ) are all positive and the distribution of the threshold voltages is relatively narrow. In this embodiment, the first threshold voltage (VT0) has a nominal value of about +1.0V and is used to store logic data "11". The voltage distribution of the first critical voltage ( VT0 ) varies from +0.75V to +1.25V. The second threshold voltage ( VT1 ) has a standard value of about +2.0V and is used to store a logic data "10". The second threshold voltage ( VT1 ) varies from about +1.75V to about +2.25V. The third threshold voltage (Vt2) has a standard value of about +3.0V, and the distribution of the third threshold voltage (Vt2) for storing a logic data "01" varies from about +2.75V to about +3.25V. The fourth threshold voltage (Vt3) has a standard value of about 3.0V and is used to store a logic data "00". The distribution of the fourth threshold voltage (Vt3) varies from about +3.75V to about +4.25V.

7a-7d are critical voltage diagrams of other embodiments of the double-transistor floating-gate NMOS NOR flash unit of the present invention. Fig. 6a-Fig. 6d have described Fig. 4a, Fig. 4b-1, Fig. 4b-2, Fig. 4c-1 and Fig. 4c-2 NMOS NAND flash floating gate transistor 405a and 405b carry out the routine of programming operation and erasing operation Threshold voltage graph. Erase and program threshold voltage diagrams opposite to those in FIGS. 6a-6d are depicted in FIGS. 7a-7d. In FIG. 7a, the first threshold voltage (VT0) and the second threshold voltage (VT1) respectively represent logic data "0" and logic data "1", and have standard values of about -0.5V and about +3.0V, respectively. Similarly, in FIG. 7b, the first threshold voltage (VT0) represents logic data "0", and the second threshold voltage (VT1) represents logic data "1", and have standards of about +1.0V and about +3.0V respectively value. In Figure 7c, the first threshold voltage (VT0) has a standard value of about -0.5V and is used to store logic data "00"; the second threshold voltage (VT1) has a standard value of about +1.0V and is used to store logic data "10"; the third threshold voltage (Vt2) has a standard value of about +2.0V, and is used to store logic data "01"; the fourth critical voltage (Vt3) has a standard value of about +3.0V, and is used to store a logic Data "00". In Figure 7d, the first critical voltage (VT0) has a nominal value of approximately +1.0V and is used to store logic data "00"; the second critical voltage (VT1) has a nominal value of approximately +2.0V and is used to store logic data Data "10"; the third threshold voltage (Vt2) has a standard value of about +3.0V and is used to store the logic value "01"; the fourth threshold voltage (Vt3) has a standard value of about +4.0V and is used to store logic Data "00".

The state of the fourth threshold voltage ( Vt3 ), which is the highest threshold voltage of the multilayer potential cell, or the second threshold voltage ( Vt1 ) of the single layer potential cell is designated as the state of the erase operation. The first critical voltage (Vt0) of the single-layer potential cell and the first critical voltage (Vt0), the second critical voltage (Vt1), and the third critical voltage (Vt2) of the multi-layer potential cell are programming states. The erasing threshold voltage (the threshold voltage Vt3 of the multi-layer potential cell or the critical voltage Vt1 of the single-layer potential cell) is obtained through the positive Fowler-Nordheim channel tunneling effect of a page on the NOR non-volatile flash memory component. Obtained, the NOR flash memory component applies a voltage of about +20.0V to the selected NMOS NAND flash floating gate transistors 405a and 405b in FIG. 4a, FIG. 4b-1, FIG. 4b-2, FIG. 4c-1 and FIG. 4c-2 The selected control gates 425a and 425b, and a ground reference voltage (0.0V) is applied to the selected body regions. It should be noted that the erase state of the fourth threshold voltage (Vt3) of the multi-layer potential cell in Fig. 7c and Fig. 7d and the second threshold voltage (VT1) of the single-layer potential cell in Fig. 7a and Fig. 7b is set to A voltage value at which the collective effect of the Fowler-Nordheim channel can be realized. Since it is only necessary to check whether the erased state threshold voltage passes the minimum acceptable erased state threshold voltage, but the maximum erased state voltage does not need to be checked, therefore, the distribution of the threshold voltage varies greatly.

After the erase operation, the cells to be programmed are programmed to other logical data states through a bit-by-bit Fowler-Nordheim boundary programming process in which a negative voltage of approximately -10.0V is applied A selected word line in a page of NOR non-volatile flash memory devices and applying a voltage of about +5V to about +10V to the drains of the selected NMOS NAND flash floating gate transistors 405a and 405b. The sources of the selected NMOS NAND flash floating gate transistors 405a and 405b are then turned off to a floating state. As previously stated, the programming operation of the NMOS NAND flash floating gate transistors 405a and 405b has two steps, the first of which is to erase selected NOR flash components with a positive Fowler-Nordheim channel operation block, the second step is to trim the maximum threshold voltage to the desired voltage using a bit-by-bit Fowler-Nordheim boundary tunneling programming operation.

FIG. 8 is a schematic diagram of a NOR flash device 500 including embodiments of a two-transistor floating-gate NMOS NOR flash cell 510 of the present invention. NOR flash device 500 includes an array 505 of two-transistor floating-gate NMOS NOR flash cells 510 arranged in columns and rows. Each two-transistor floating-gate NMOS NOR flash cell 510 includes two NMOS NAND flash floating-gate transistors 515a and 515b. The two NMOS NAND flash floating gate transistors 515a and 515b are constructed and operated like the NMOS NAND flash floating gate transistors 405a and 405b in FIGS. 405b. The drain of the NMOS NAND flash floating gate transistor 515a is connected to one of the local bit lines 520a, 520b, . . . , 520n-1 and 520n. The source of NMOS NAND floating gate transistor 515b is connected to one of source lines 530a, 530b, . . . , 530n-1 and 530n. The source of the NMOS NAND flash floating gate transistor 515a is connected to the drain of the NMOS NOR flash floating gate transistor 515b.

Local bitlines 520a, 520b, . ..., 525n. Local source lines 530a, 530b, . Lines 540a, . . . , 540n. The global bit lines 525a, . . . , 525n and the global source lines 540a, . Column voltage control circuit 555 generates the appropriate voltages to selectively read, program and erase two-transistor floating-gate NMOS NOR flash cells 510.

Each control gate of NMOS NAND flash floating gate transistors 515a and 515b of two transistor floating gate NMOS NOR flash cells 510 on each row in array 505 is connected to one of word lines 545a, 545b, . . . , 545m. In the row voltage control circuit (row voltage control circuit, ROW V CTL CKT) 550, the word lines 545a, 545b, ..., 545m are connected to the word line voltage control circuit (word line voltage control circuit, WORD LINE VOLTAGE CTL) 552.

Each gate of the bit line selection transistors 560a, ..., 560n is connected to a bit line selection control sub-circuit (bit line select control sub-circuit, BL SEL CTL) 551 in the row voltage control circuit 550, to provide a selection signal enabling bit Line selection transistors 560a, . . . , 560n, thereby connecting a selected local bit line 520a, 520b, . Each gate of the source line selection transistors 565a, ..., 565n is connected to a source line selection control sub-circuit (source line voltage control sub-circuit, SOURCE LINE VOLTAGE CTL) 553 within the row voltage control circuit 550, to Local source lines 530a, 530b, ..., 530n-1 and 530n are connected to their corresponding global source lines 540a, ..., 540n.

Each gate of the source line selection transistors 565a, . Thus, a selected local source line 530a, 530b, . . . , 530n-1 and 530n is connected to its corresponding global source line 540a, . Each gate of the source line selection transistor 565a, . and 530n are connected to source lines 540a, . . . , 540n of the universe corresponding thereto.

FIG. 9 is a schematic diagram of the row voltage control circuit 550 . The row voltage control circuit 550 includes a control decoder (CTRL DCDR) 605 for receiving programming timing and control signals 610 , erasing timing and control signals 615 and reading timing and control signals 620 . The control decoder 605 decodes program timing and control signals 610 , erase timing and control signals 615 , and read timing and control signals 620 to establish the operation of the NOR flash memory component 500 . The row voltage control circuit 550 includes an address decoder (address decoder, ADDR DCDR) 625 for receiving and decoding an address signal 630 to provide the selected double transistor floating Gate NMOS NOR flash cell 510 location.

The bit line selection control subcircuit 551 receives the decoded program operation, erase operation and read operation timing and control signals from the control decoder 605 , and also receives the decoded address from the address decoder 625 . The bit line selection control subcircuit 551 selects one of the bit line selection signals 570a, . . . , 570n to activate the bit line selection transistors 560a, . . . . , 520n-1 and 520n are connected to bit lines 525a, . . . , 525n of the corresponding universe.

The source line selection control subcircuit 553 receives the decoded program operation, erase operation and read operation timing and control signals from the control decoder 605 , and also receives the decoded address from the address decoder 625 . The source line selection control subcircuit 553 selects one of the source line selection signals 575a, . . . , 575n to activate the source line selection transistors 565a, . Lines 530a, 530b, ..., 530n-1, and 530n are connected to corresponding global source lines 540a, ..., 540n.

The word line voltage control sub-circuit 552 includes a program voltage generator 635 , an erase voltage generator 640 , a read voltage generator 645 and a row selection switch 650 . The programming voltage generator 635 includes a pulse increasing voltage generator (V _PGMR ) 636 to provide a pulse voltage gradually increasing from about 15.0V to about +20.0V, so that the NMOS in FIG. 8 can be set more accurately and stably. Threshold voltage values of NAND floating gate transistors 515a and 515b. In the first embodiment, a positive programming voltage generator ( _VPGM+ ) 637 is used to provide a voltage of about +5.0V; in the second embodiment, the positive programming voltage generator 637 is used to provide a voltage of about +2.5V to prevent the programming operation of the unselected NMOS NAND flash floating gate transistors 515a and 515b in FIG. 8 from being inhibited. In a second embodiment, the erase and program conditions are reversed as described in Figures 7a-7d. According to the voltage distribution relationship in FIG. 7a-FIG. 7d, the negative programming voltage generator (V _PGM- ) 638 provides a negative voltage of about -10.0V to the non-selected NMOS NAND flash floating gate transistors 515a and 515b in FIG. Perform programming operations. A ground reference voltage source 639 is used to insulate all dual NMOS NAND flash floating gate transistors 515a and 515b within a NOR flash memory device 500 from each other to prevent the NMOS NAND flash floating gate transistors 515a and 515b described in FIG. The established programming in is corrupted.

The erase voltage generator 640 includes a positive erase voltage generator (V _ERS+ ) 642 for providing the necessary positive voltage to erase the non-selected word lines of the NOR non-volatile flash memory device 500 in the first embodiment. , thereby preventing the programming in the unselected NMOS NAND flash floating gate transistors 515a and 515b in FIG. 8 from being damaged. In the second embodiment, the positive erase voltage generator 642 is used to provide the required voltage to perform the erase operation on the NMOS NAND flash floating gate transistors 515 a and 515 b in FIG. 8 . In the first embodiment, the erase voltage generator 640 includes a negative erase voltage generator (V _ERS− ) 643 for erasing the NMOS NAND flash floating gate transistors 515 a and 515 b in FIG. 8 . In the second embodiment, the voltage of the unselected word lines is set to the ground reference voltage source 644 .

In order to read single-level cell data, the read voltage generator 645 includes a first high read voltage generator (V _H ) 646, which is used to provide the necessary read voltage VH Control gates for selected word lines of NMOS NAND flash floating gate transistors 515a and 515b in FIG. 8 . For reading multi-level cell data, the read voltage generator 645 also includes a second and third high read voltage generators (V _H0 and V _H1 ) 647 and 648, the second and third high read voltage The generators 647 and 648 are respectively used to provide the necessary read voltages VH1 and VH2 to the selected control gates of the NMOS NAND flash floating gate transistors 515 a and 515 b in FIG. 8 . The read voltage generator 645 also provides a voltage source generator (V _DD ) 649 to the control gates of the NMOS NAND flash floating gate transistors 515 a and 515 b in FIG. 8 to read single-level cell data.

The row voltage control circuit includes a row selection switch to transmit the programming voltage, erasing voltage and reading voltage of the programming voltage generator 635, the erasing voltage generator 640 and the reading voltage generator 645 to the selected word line 545a, 545b, ..., 545m.

Referring to Figure 10, the column voltage control circuit 555 is depicted. The column voltage control circuit 555 includes a control decoder 705 for receiving program timing and control signals 710 , erase timing and control signals 715 , and read timing and control signals 720 . The control decoder 705 is also used to decode the program timing and control signal 710 , the erase timing and control signal 715 , and the read timing and control signal 720 to operate the NOR flash memory device 500 . The column voltage control circuit 555 also includes an address decoder 725, which is used to receive and decode an address signal 730 to provide the address of the selected two-transistor floating gate NMOS NAND flash unit 510, thereby performing its program, erase or read operation.

The column voltage control circuit 555 also includes a program voltage generator 735 , an erase voltage generator 740 , a read voltage generator 745 and a column selection switch 750 . The programming voltage generator 735 includes a programming voltage source (V _PGM ) 736. In the first embodiment, the programming voltage source 736 is used to provide a programming inhibit voltage of about +10.0V to the unselected NMOS NAND in FIG. The drains and sources of the flash floating gate transistors 515a and 515b are used to inhibit the programming operation of the unselected NMOS NAND flash floating gate transistors 515a and 515b. In the second embodiment, the programming voltage source 736 is used to provide a voltage of approximately +5.0V to the drains of the selected NMOS NAND flash floating gate transistors 515a and 515b in FIG. 8 during programming operations. In the first embodiment, a ground reference voltage source 737 is also provided to the drains and sources of the selected NMOS NAND flash floating gate transistors 515a and 515b in FIG. 8 during programming operations. For some unselected NMOS NAND flash floating gate transistors 515a and 515b in FIG. .

The erasing voltage generator 740 includes an erasing voltage source (V _ERS ) 742 , which is used to provide the necessary anode voltage to implement the erasing operation of the NOR flash memory device 500 in the first embodiment. The drain and source voltages of the unselected NMOS NAND flash floating gate transistors 515 a and 515 b in FIG. 8 are then set to the ground reference voltage source 743 .

In order to read multi-layer potential cell data, the read voltage generator 745 includes a moderate high read voltage source (V _DD ) 747, which is used to provide the necessary read voltage VHD to The drains of the selected NMOS NAND flash floating gate transistors 515a and 515b in FIG. 8 . To read single-level cell data, the read voltage generator 745 further includes a voltage source generator for providing voltages to the drains of the NMOS NAND flash floating gate transistors 515 a and 515 b in FIG. 8 .

The column voltage control circuit 555 includes a column selection switch 750, and the column selection switch 750 is used to set the program voltage, erase voltage and read voltage of the program voltage generator 735, erase voltage generator 740 and read voltage generator 745 to Transfer to the selected bit lines 525a, 525b, ..., 525n and source lines 540a, 540b, ..., 540n.

FIG. 11a is a schematic diagram of a single-layer potential programming voltage following sensing circuit in various embodiments of the NMOS NOR flash memory cell 400 in FIG. 4a. The schematic depicts two NMOS NAND flash floating gate transistors 405a and 405b in a column of NMOS NAND flash floating gate transistors. The drain 415 of the uppermost transistor of the NAND flash floating gate transistors 405 a and 405 b is connected to the local bit line 805 and then connected to the global bit line 815 through the bit line select transistor 810 . The global bit line 815 is connected to the column voltage control circuit 555 in FIG. 8 . The gate of the bit line selection transistor 810 is connected to the bit line selection control subcircuit 551 of FIG. Source VDD.

The source 422 of the bottommost NMOS NAND flash floating gate transistor 405 b is connected to the local source line 825 . The local source line 825 is connected to the global bit line 835 through a source line select transistor 830 . The global bit line 835 is connected to the sense amplifier 755 in the column voltage control circuit 555 in FIG. 10 . The sense amplifier 755 includes a comparison circuit 850 , one end of the comparison circuit 850 is connected to the global source line 835 , and the other end is connected to the reference voltage source 855 . The voltage of the reference voltage source 855 is set between threshold voltages representing logic "1" and logic "0". The gate of the source line selection transistor 830 is connected to the source line voltage control sub-circuit 553 of the column voltage control circuit 555 in FIG. 8 . The source line voltage control subcircuit 553 is used to provide the voltage necessary to activate the source line selection transistor 830, thereby connecting the local source line 825 to the global bit line 835, which is the source of the NMOS NOR flash memory unit 400 422. When the NMOS NAND flash floating gate transistors 405a and 405b are enabled, their operation behavior is similar to that of a voltage follower. The voltage of the source line capacitor 845 is equal to the voltage source minus the programming threshold voltage of the NMOS NAND flash floating gate transistor 405a or 405b (Vs=VDD−VtMSEL). The unselected NMOS NAND flash floating gate transistor 405a or 405b is driven like a voltage follower. The voltage on the source line capacitance 845 is equal to the voltage source minus the programming threshold voltage of the selected floating-gate transistor 405a or 405b (Vs=VDD-Vt _MSEL ). Depending on the programming threshold voltage of the selected NMOS NAND flash floating gate transistor 405a or 405b, the output voltage of the comparison circuit 850 will represent a logic "1" or a logic "0" represented by the programming threshold voltage.

Referring to FIG. 11b, bias voltages for reading single-level programming of NMOS NOR flash memory cell 400 are described. To read the SLC stored value of the uppermost transistor in NMOS NAND flash floating gate transistors 405a and 405b, the voltage of the first word line WL0 450a is set to the voltage of the voltage source VDD. The voltage of the voltage source VDD is about +1.8V or about +3.0V. The voltage of the second word line WL1 450b is set to a higher read voltage greater than +6.0V to turn on the NMOS NAND flash floating gate transistor 405b. The voltage of the drain of the uppermost NMOS NAND flash floating gate transistor 405a is set to the voltage of the voltage source VDD through the local bit line 805 and the global bit line 815 . If the NMOS NAND flash floating gate transistor 405a is programmed to have a first threshold voltage Vt0 (from about -0.75V to about -0.25V), the source 422 of the lowermost NMOS NAND flash floating gate transistor 405b, that is The voltage value VSO of the first input terminal of the comparison circuit 850 is approximately equal to the voltage value of the voltage source VDD. If the floating gate transistor 405a is programmed to have the second critical voltage Vt1 (greater than +3.0V), the source 422 of the NMOS NAND flash floating gate transistor 405b at the lower end, that is, the voltage value VS1 of the first input terminal of the comparison circuit 850 A voltage value approximately equal to the ground reference voltage (0.0V). In this way, the logic value of the output terminal of the comparison circuit 850 is specified by the threshold voltage value programmed by the uppermost NMOS NAND flash floating gate transistor 405a.

In order to read the SLC storage value of the lowermost transistor in the NMOS NAND flash floating gate transistors 405a and 405b, the voltage value of the second word line WL1 450b is set as the voltage value of the voltage source VDD. The voltage value of the first word line WL0 450a is set to a higher read voltage greater than +6.0V to turn on the NMOS NAND flash floating gate transistor 405a. The drain voltage of the lowermost NMOS NAND flash floating gate transistor 405b is set as the voltage source VDD through the uppermost NMOS NAND flash floating gate transistor 405a, the global bit line 815 and the local bit line 805. If the lowermost NMOS NAND flash floating gate transistor 405b is programmed to have a first threshold voltage Vt0 (from about -0.75V to about -0.25V), the source 422 of the lowermost NMOS NAND flash floating gate transistor 405b, That is, the voltage value VSO of the first input terminal of the comparison circuit 850 is approximately equal to the voltage value of the voltage source VDD. Since the gate voltage VDD of the NMOS NAND flash floating gate transistor 405b is less than Vt1, if the NMOS NAND flash floating gate transistor 405b is programmed to have a second critical voltage Vt1 (greater than +3.0V), the lowermost NMOS NAND flash The voltage value VS1 of the source 422 of the floating gate transistor 405b, that is, the first input terminal of the comparison circuit 850 is approximately equal to the voltage value of the ground reference voltage (0.0V). In this way, the bottom NMOS NAND flash floating gate transistor 405b is in a non-conductive state, and no voltage is transmitted from the local bit line 805 to the local source line selection transistor 830, so VS1=0V. In this way, the output logic value of the comparison circuit 850 is specified by the threshold voltage value programmed by the bottommost NMOS NAND flash floating gate transistor 405b.

In an array of NMOS NOR flash memory units 400, if an NMOS NOR flash memory unit 400 is not selected for reading and another NMOS NOR flash memory unit is selected for reading, the unselected NMOS NOR flash memory unit 400 The control gates of the non-selected NMOS NAND flash floating gate transistors 405a and 405b are set to a ground reference voltage to turn off the charge conservation transistors.

FIG. 11c is a schematic diagram of a specific embodiment of a voltage-following sensing circuit for multilayer potential programming of the NMOS NOR flash memory cell 400 in FIG. 4a. A column of NMOS NAND flash floating gate transistors as depicted in FIG. 11a, the schematic diagram illustrates that the voltages of the two NMOS NAND flash floating gate transistors 405a and 405b are set to a first comparison except for the global bit line. High read voltage source VHD.

In this particular embodiment, the global bit line 835 is connected to the sense amplifier 755 in the column voltage control circuit 555 in FIG. 10 . In this embodiment, the sense amplifier 755 includes three comparison circuits 860 , 870 and 880 . The first input terminal of each circuit of the three comparison circuits 860, 870 and 880 is connected to the global bit line 835, and the second input terminal is connected to the reference voltage source, wherein the second input terminal of the first comparison circuit 860 is connected to to the first reference voltage source 865 REFV0; the second input terminal of the second comparison circuit 870 is connected to the second reference voltage source 875 REFV1; the second input terminal of the third comparison circuit 880 is connected to the third reference voltage source 885 REFV2. The voltage values of the three reference voltage sources 865, 875 and 885 are set between critical voltage values representing logic values (“00”, “01”, “10”, “11”) of data. The gate of the source line selection transistor 830 is connected to the source line voltage control sub-circuit 553 in the row voltage control circuit in FIG. 8 . The source line voltage control subcircuit 553 is used to provide the necessary voltage so that the source line selection transistor 830 is connected to the local source line 825, that is, the source 422 of the NMOS NOR flash memory unit 400 is connected to the global bit line 835. When the NMOS NAND flash floating gate transistors 405a and 405b are enabled, they act like a voltage follower. The voltage on the source line capacitance 845 is equal to the voltage source minus the programming threshold voltage of the selected NMOS NAND flash floating-gate transistor 405a or 405b (Vs=VDD-Vt _MSEL ). The unselected NMOS NAND flash floating gate transistor 405a or 405b is driven to have the minimum voltage drop. According to the programming threshold voltage level of the selected NMOS NAND flash floating gate transistor 405a or 405b, the output voltage of the comparison circuit 850 will represent the data logic value ("00", "01", "10", "11") with the programmed threshold voltage "). It should be noted that the structure described in this embodiment is applicable to a two-bit multi-level unit. It can be understood that any number of data logic values can be stored by NMOS NAND flash floating gate transistors 405a and 405b without departing from the spirit of the present invention.

Figure 11d discusses the bias voltages for reading NMOS NOR flash memory cell 400 multilayer potential programming. The voltage of the first word line WL0 450a is set to a first higher read voltage VH0 to read the uppermost transistors of the NMOS NAND flash floating gate transistors 405a and 405b. The first higher read voltage VH0 is about 4.0V. The voltage of the second word line WL1 450b is set to a second higher read voltage VH1 greater than +7.0V to turn on the NMOS NAND flash floating gate transistor 405b. The voltage at the drain of the uppermost NMOS NAND flash floating gate transistor 405a is set to a third higher voltage source VHD (>4.0V) through the local bit line 805 and the global bit line 815.

If the voltage of the NMOS NAND floating gate transistor 405a is set to the first critical voltage Vt0 (from about -0.75V to about -0.25V), then the source 422 of the lowermost NMOS NAND flash floating gate transistor 405b, that is The voltage VSO of the first input terminal of the comparison circuit 850 is approximately the third high read voltage VHD. If the voltage of the NMOS NAND flash floating gate transistor 405a is programmed to have the second critical voltage Vt1 (about +1.0V), the voltage VS1 of the source 422 of the lowermost NMOS NAND flash floating gate transistor 405b, that is, the comparison circuit The voltage at the first input of 850 is about 3.0V. If the voltage of the NMOS NAND flash floating gate transistor 405a is programmed to have the third critical voltage Vt2 (about 2.0V), the voltage VS2 of the source 422 of the lowermost NMOS NAND flash floating gate transistor 405b, that is, the comparison circuit 850 The voltage at the first input terminal of , is about 2.0V. If the voltage of the NMOS NAND flash floating gate transistor 405a is programmed to have the second critical voltage Vt3 (about +3.0V), the voltage VS3 of the source 422 of the lowermost NMOS NAND flash floating gate transistor 405b, that is, the comparison circuit The voltage at the first input terminal of 850 is about a ground reference voltage (1.0V). Then the output terminal of the comparison circuit 850 is set to a logic state determined by the threshold voltage programmed by the uppermost NMOS NAND flash floating gate transistor 405a.

In order to read the multilayer potential programming of the lowermost transistor of the NMOS NAND flash floating gate transistors 405a and 405b, the voltage of the second word line WL1 450b is set to the voltage of VHD. The voltage of the first word line WL0 450a is set to a higher read voltage greater than +6.0V to turn on the NMOS NAND flash floating gate transistor 405a. The voltage GSL of the global source line of the lowermost select transistor controlled by the gate of SLG[n] is passed through the lowermost NMOS NAND flash floating gate transistor 405b, the uppermost NMOS NAND flash floating gate transistor 405a, the local The bit line 805, the uppermost selection transistor Msel controlled by the BLG[n] gate, and the global bit line 815 are set to ground. The gate voltages of the top and bottom select transistors must be coupled to the sum of the high read voltage and the threshold voltage (VHD+Vt) to fully transfer sufficient VHD voltage from GBL to GSL.

If the voltage of the NMOS NAND flash floating gate transistor 405b is programmed to have a first threshold voltage Vt0 (from about -0.75V to about -0.25V), the voltage of the source 422 of the lowermost NMOS NAND flash floating gate transistor 405b VSO, that is, the voltage at the first input terminal of the comparison circuit 850 is approximately equal to a third high read voltage source VHD. If the voltage of the NMOS NAND flash floating gate transistor 405b is programmed to have a second threshold voltage Vt1 (about +1.0V), and VHD is approximately equal to 4.0V, then the source of the lowermost NMOS NAND flash floating gate transistor 405b The voltage VS1 of 422, that is, the voltage of the first input terminal of the comparison circuit 850 is approximately equal to 3.0V. If the voltage of the NMOS NAND flash floating gate transistor 405b is programmed to have the third critical voltage Vt2 (about 2.0V), then the voltage VS2 of the source 422 of the lowermost NMOS NAND flash floating gate transistor 405b, that is, the comparison circuit The voltage at the first input of 850 is about 2.0V. If the voltage of the NMOS NAND flash floating gate transistor 405b is programmed to have the second critical voltage Vt3 (about +3.0V), the voltage VS3 of the source 422 of the lowermost NMOS NAND flash floating gate transistor 405b is also the comparison The voltage at the first input of circuit 850 is about 1.0V. Next, the output terminal of the comparison circuit 850 is set to a logic state determined by the threshold voltage programmed by the bottommost NMOS NAND flash floating gate transistor 405b.

In both embodiments of the read operation of the NMOS NOR flash memory cell 400 of FIG. 11a and FIG. Well 435 is then connected to voltage source VDD.

In an array of NMOS NOR flash memory units 400, if an NMOS NOR flash memory unit 400 is not selected for a read operation, and another NMOS is selected for a read operation, no NMOS NOR flash memory unit 400 in this unselected The control gate voltages of the selected NMOS NAND flash floating gate transistors 405a and 405b are then set to a ground reference voltage to turn off the charge conservation transistors.

Figures 12a-12e are tables of erase bias voltages for the two-transistor floating-gate NMOS NOR flash cells in Figures 4a, 4b-1, 4b-2, 4c-1, and 4c-2. Referring to Fig. 12b-Fig. 12e, the erase bias voltages of the four tables are used to provide an erase condition so that the drains 415, 420 and The voltage drop between the bulk region channel regions 432a and 432b between the sources 420, 422 and the control gate 425a or 425b is set to a voltage of approximately +20.0V during Fowler-Nordheim channel erase. In FIG. 12a, the selected word line 450a or 450b, that is, the voltage of the control gate 425a or 425b is set to a negative erase voltage of about -10.0V. The drains 415 and 420, sources 420 and 422, triple P-well 430 and deep N-well 435 are set to a positive erase voltage of about +10.0V. The voltage of the unselected word line 450a or 450b, that is, the unselected control gate 425a or 425b is set to an inhibit erase voltage of about +10.0V.

In FIG. 12b, the negative erase voltage is about -15.0V, the positive erase voltage is about +5.0V, and the positive shade voltage is about +5.0V. In FIG. 12c, the negative erasing voltage is about -20.0V, the positive erasing voltage is about 0.0V, and the positive suppression voltage is about 0.0V. In Figure 12d, the voltage levels are reversed, the negative erase voltage is about 0.0V, and the positive erase voltage is about +20.0V. Each voltage in FIGS. 12a-12d produces a Fowler-Nordheim channel tunneling effect to reduce the threshold voltage of the selected NMOS NAND flash floating gate transistor 405a or 405b.

The unselected two-transistor floating-gate NMOS NAND flash cells in FIGS. 4a , 4b-1 , 4b-2 , 4c-1 , and 4c-2 do not share the same triple P-well 430 and deep N-well 435 . The voltage of the unselected word line 450a or 450b, that is, the control gate 425a or 425b, the drains 415 and 420, the sources 420 and 422, and the triple P-well 430 is set approximately equal to the ground reference voltage. The voltage of the deep N-well 435 is set to the voltage of the voltage source VDD.

For sub-arrays in an array of floating-gate NMOS NAND flash cells (usually 512Kb or 4Kb blocks), the voltage of the deep N-well of the unerased sub-array is set to +20V, and its character The voltages of the line, drain, source and triple P diffusion wells are then set as ground reference voltages. The voltages of the word lines, drains, sources, triple P wells and deep N diffusion wells of the unselected sub-arrays in different deep N diffusion wells are then set as ground reference voltages.

Another erase operation when the erase and program threshold voltages are inverted is discussed in FIG. 12e. In this case, the selected word line 450a or 450b, that is, the voltage of the control gate 425a or 425b is set to a positive programming voltage of about +20.0V. The voltages of the control gate 425a or 425b, the drains 415 and 420, the sources 420 and 422, and the triple P-well 430 are set to a ground reference voltage (0.0V). The voltage of the deep N-well 435 is set to the voltage of the voltage source. The conditions for setting the threshold voltage for erasing to the positive voltage and the conditions for setting the programming threshold voltage to the negative voltage are shown in FIGS. 7 a - 7 d.

Figures 13a and 13b are programming bias voltage tables for the programming operation of the dual-transistor floating-gate NMOS NOR flash cells in Figure 4a, Figure 4b-1, Figure 4b-2, Figure 4c-1 and Figure 4c-2. Programming the selected NMOS NAND flash floating-gate transistor 405a or 405b in the two-transistor floating-gate NMOS NAND flash cell in FIGS. 4a, 4b-1, 4b-2, 4c-1, and 4c-2 Before operation, the cell must be erased as described above. In an array of two-transistor floating-gate NMOS NAND flash cells as shown in FIG. 8, the erase operation is performed on a page or a block of cells.

When the selected NMOS NAND flash floating gate transistor 405a or 405b in Fig. 4a, Fig. 4b-1, Fig. 4b-2, Fig. 4c-1 and Fig. 4c-2 is programmed, the selected word line 450a or 450b, that is, the voltage of control gate 425a or 425b is set to a positive programming voltage of approximately +15.0V to +20.0V. The voltages of the drains 415 and 420 , the sources 420 and 422 , and the channel regions 432 a and 432 b are set to a ground reference voltage (0.0 V) through the triple P-well 430 . The word line 450a or 450b of the unselected NMOS NAND flash floating gate transistor 405a or 405b is connected to its control gate 425a or 425b to set its voltage to an inhibit programming voltage of about +5.0V. In an array as shown in FIG. 8, the drain and source voltages of the unselected floating-gate NMOS NAND flash cells on the selected word line 450a or 450b are set to a voltage ranging from approximately +7.0 V to a positive program inhibit voltage of approximately +10.0V. In an array as shown in FIG. 8, the voltages of the word lines 450a and 450b of the unselected floating-gate NMOS NAND flash cells having shared bit lines 455a, 455b and source lines 460a, 460b of the positive suppression voltage are Set to a positive inhibit programming voltage of +5.0V. The voltage of the non-selected floating gate NMOS NOR flash cells that are not connected to the positive programming voltage or the positive programming inhibiting voltage in the word lines 450a, 450b or bit lines 455a, 455b or source lines 460a, 460b is set to Ground Reference Voltage (0.0V). It is known in the prior art that when the positive programming voltage applied to the control gate 425a or 425b is higher, the threshold voltage Vt after the programming operation is also higher. During programming operations, in order to maintain precise control over the threshold voltage of NMOS NAND flash cells, the gate is applied with an initial positive programming voltage from about +15.0V to about +16.0V. Afterwards, the positive programming voltage is repeatedly incremented by a small amount during each programming operation. The above-mentioned programming voltage is suitable for programming single-layer potential cells or multi-layer potential cells, and the critical voltages thereof are shown in FIGS. 6a-6d.

This is an iterative program operation and program verify step by gradually increasing the negative gate voltage by small amounts with the drain voltage and the floating source preferably fixed optimal voltage of the selected programmed cells in the selected block. For example, the drain (local BL) voltage is coupled to a fixed +5V and the local SL is floating. FIG. 8f is a preferred bias condition for programming the selected cell M0. A gate voltage of -10V is applied to WL0 of the selected cell M0. The -10V gate voltage can start at -5V and gradually decrease to -10V. In other words, the voltage value Vt of the cell can be precisely controlled to a desired voltage value.

Referring to FIG. 13b, the programming voltages for the reversed program and erase conditions as shown in FIGS. 7a-7b are described. In this embodiment, the selected NMOS NAND flash floating gate transistor 405a or 405b has the selected word line 450a or 450b set to a negative programming voltage of approximately -10.0V. The voltage at drains 415 and 420 ramps down to a positive drain voltage of approximately +5.0V. The voltage of the source 420 stops floating. The selected NMOS NOR flash cell is repeatedly programmed and verified so that the cell threshold voltage can be accurately reached after the programming operation. In this embodiment, the programming condition is based on the Fowler-Nordheim boundary tunneling programming operation. A common FN boundary programming operation is used to reduce the voltage Vt of the selected cells after programming. However, the final voltage Vt of the selected programming cells after FN boundary programming must be positive to avoid misreading due to BL leakage through unselected cells in the selected block. The FN boundary occurs at the boundary between the drain point and the gate point of the selected NAND cells in the selected block of the present invention.

In addition, the negative programming voltage can be gradually increased from about -7.0V to about -10.0V. The positive-drain voltage in the middle is fixed at approximately +5.0V. In this embodiment, the negative programming voltage is gradually increased by approximately 0.3V in each repeated step.

The voltage of the unselected word line 450a or 450b is set to a positive inhibit voltage of about +2.5V to inhibit the unselected NMOS NAND flash floating gate transistor 405a or 405b from being programmed. The drain 415 of the unselected NMOS NAND flash floating gate transistor 405a or 405b and the voltage of the triple P well 430 are set to the ground reference voltage (0.0V), and the voltage of the deep N well 435 is set to Voltage source VDD.

Electrons in the floating gate of the selected floating gate NMOS NOR flash cell are expelled from floating gate 445a or 445b. Therefore, the threshold voltage of selected floating-gate NMOS NOR flash cells can be controlled very precisely in single-level cells and multi-level cells.

FIG. 14 is a flow chart of forming a NOR flash memory device by applying the present invention. An array of floating gate transistors is formed on a substrate (shown as block 905). The floating gate transistors are arranged in a matrix of rows and columns. At least two adjacent floating gate transistors are connected in series in a column to form a NAND string of NOR memory cells (block 910). The drain of the uppermost floating gate transistor in each column of NAND-based NOR flash memory cells is connected to a corresponding bit line (block 915). The source of the bottommost floating-gate transistor in each column of NAND-based NOR flash memory cells is connected to a corresponding source line (block 920).

The local bit line is connected to a corresponding global bit line through an uppermost bit line select transistor (block 925). The source of the uppermost bit line select transistor is connected to the local bit line, and the drain of the uppermost bit line select transistor is connected to the global bit line. The local source line is connected to a corresponding global source line through a lowermost source line select transistor (block 930). The source of the lowermost source line selection transistor is connected to the local source line, and the drain of the lowermost source line selection transistor is connected to the global source line.

A bit line gate select control line is connected to the gate of the uppermost bit line select transistor (block 935). A source line gate select control line is connected to the gate of the lower source line select transistor (block 940). In each row of the NAND-based NOR flash memory array, the control gate of each floating gate transistor is connected to a corresponding word line (block 945). Each word line in each row of floating-gate transistors is connected to a word line voltage controller (block 950) to provide the necessary voltage for programming, erasing, and reading the NAND-based NOR flash memory array. required bias. Each bitline select control line is connected to the bitline select controller (block 955) so that the bitline select transistor can selectively connect a selected local bitline to a global bitline. Likewise, each source line select control line is connected to a source line select controller (block 960), so that the source line select transistor can selectively connect a selected local source line to a Global source line.

Each global and column bit line is connected to a column voltage controller (block 965). As mentioned above, the word line voltage controller and the column voltage controller are used to provide appropriate voltages to the NAND-based NOR flash memory cells for programming, erasing and reading operations on the NOR flash memory cells.

FIG. 15 is a schematic diagram of an embodiment of a NAND-based multi-transistor floating-gate NMOS NOR flash memory array. In the NAND-based NMOS NOR flash memory array shown in Figure 8, each floating-gate NMOS NOR flash cell includes two floating-gate transistors. In FIG. 15, at least two of the floating-gate transistors 1010a, 1010b, ..., 1010n in each floating-gate NMOS NOR flash unit 1005 are connected in series with each other, just like the embodiment of the double-transistor series connection described in FIG. 8 . The drain of the uppermost floating gate transistor 1010 a is connected to the local bit line 1015 , and the source of the lowermost floating gate transistor 1010 n is connected to the local source line 1020 . Each word line 1025a, 1025b, . . . , 1025n is connected to the control gate of a floating gate transistor 1010a, 1010b, . The number of bits stored in a single-level cell in a floating-gate NMOS NOR flash cell is one bit per transistor, so that the floating-gate NMOS NOR flash cell can be designated as an n-bit/n-transistor cell. In a multi-level cell, the number of bits depends on the number of threshold voltages stored in each floating gate transistor 1010a, 1010b, . . . , 1010n.

The current requirement for NOR flash device technology is a read time between about 20uS to about 100nS. The number of transistors determines the performance of NAND-based NOR flash memory cells. For example, in the embodiment of the double-transistor floating gate NMOS NOR flash cell in Fig. 4a, Fig. 4b-1, Fig. 4b-2, Fig. 4c-1 and Fig. 4c-2, for the NAND based on the capacity from 1Gb to 4Gb The read time of the NMOS NOR flash array is about 100nS. In addition, the NMOS NOR flash memory array based on NAND with 1Mb to 4Mb capacity has a read time of 20ns to 50ns. In an array, the random read operation is performed in units of one byte (8 bits), one character (16 bits) or one double character (32 bits); the programming unit is a page of 512 bytes or half The programming operation is performed in units of 256 bytes on a page; the erasing operation is performed in units of sectors (a small sector of 4K bytes or a large sector of 64K bytes).

In other embodiments, the NAND-based NMOS NOR flash memory cell has 16 or 32 transistors connected in series. The read time is reduced to about 20us for a longer aligned array with capacities ranging from 1Gb to 32Gb. In this embodiment, the read operation is sequentially read in units of half page (256 bytes) or one page (512 bytes). Likewise, the program operation is performed in units of 512 bytes for a full page or 256 bytes for a half page. The erase operation is performed in units of 512 bytes x 16 (8K bytes) or 512 bytes x 32 (16K bytes) in a segment.

In various embodiments, the NAND-based floating-gate NMOS NOR flash memory cell may contain any number of transistors as previously described. However, to ensure compliance with current performance requirements for floating-gate NMOS NOR flash memory cells, typically as many as 15 transistors are used in a NAND-based floating-gate NMOS NOR flash memory cell.

As mentioned above, NAND-based NMOS NOR flash memory cells contain floating gate transistors that are used to store charge. NAND based on floating-gate NMOS NOR flash memory cells includes SONOS charge-trapping NAND transistors in each NAND string of NOR flash memory cells.

An integrated circuit including an array of NAND-based flash memory cells may include a NAND flash memory array and an array of NAND-based NMOS NOR flash memory cells using the concepts of the present invention. The NAND-based NMOS NOR flash memory cell array can be further combined with volatile memory to form a memory function on a single integrated circuit. Furthermore, the NAND-based NMOS NOR flash memory cell may include peripheral circuitry to make the NAND-based NMOS NOR flash memory cell suitable for applications such as Programmable Logic Devices (PLD) or Field Programmable Gate Arrays (FPGA).

In summary, the present invention meets the requirements of an invention patent, so a patent application is filed according to law. The above descriptions are only preferred embodiments of the present invention. For those skilled in the art, equivalent modifications or changes made in accordance with the spirit of the present invention shall all fall within the protection scope of the following claims.

Claims (95)

1. non-volatile flash memory circuit of NOR comprises:

A plurality of electric charges are preserved strings of transistors and are linked to be NAND string, it is characterized in that:

The electric charge of one the top is preserved transistor, and its drain electrode is connected to a plurality of electric charges of described polyphone and preserves the relevant bit line of transistors;

One bottom electric charge is preserved transistor, and its source electrode is connected to a plurality of electric charges of described polyphone and preserves the relevant one source pole line of transistors; And

Described a plurality of electric charge is preserved transistorized each control gate and all is connected to a character line.

2. the non-volatile flash memory circuit of NOR as claimed in claim 1 is characterized in that, described a plurality of electric charges are preserved transistor and are formed in the well of a first kind conductivity type.

3. the non-volatile flash memory circuit of NOR as claimed in claim 2 is characterized in that the well of this first kind conductivity type is formed in the deep-well of one second class conductivity type.

4. the non-volatile flash memory circuit of NOR as claimed in claim 3 is characterized in that the deep-well of this second class conductivity type is formed in the substrate of a first kind conductivity type.

5. the non-volatile flash memory circuit of NOR as claimed in claim 1 is characterized in that, described electric charge is preserved transistor and adopted Fowler-Nordheim (Fowler-Nordheim) tunneling effect to carry out programming operation and erase operation.

6. the non-volatile flash memory circuit of NOR as claimed in claim 1, it is characterized in that, apply the program voltage of one+15.0V by preserving at a selecteed electric charge between transistorized control gate and the interior body region, be programmed for the individual layer programming unit with a selecteed electric charge preservation transistor of will described a plurality of electric charges preserving in the transistors to+20.0V in the mode that increases gradually.

7. the non-volatile flash memory circuit of NOR as claimed in claim 6, it is characterized in that, preserve and apply the voltage less than 10.0V between transistorized control gate and the interior body region by preserve in the transistors other non-selected electric charge at described a plurality of electric charges, preserve transistor to suppress described non-selected electric charge.

8. the non-volatile flash memory circuit of NOR as claimed in claim 1 is characterized in that, it is to make four times to six times of characteristic dimension of minimum of the technology of NOR flash memory circuit that the layout of this NOR flash memory circuit requires the size of this NOR flash memory circuit.

9. the non-volatile flash memory circuit of NOR as claimed in claim 1, it is characterized in that, apply the anodal erasing voltage of one+15.0v between transistorized interior body region and the control gate by preserving, carry out erase operation so that this selecteed electric charge is preserved transistor to+20.0V at selecteed electric charge.

10. the non-volatile flash memory circuit of NOR as claimed in claim 1, it is characterized in that, preserve the bias voltage that applies a 0.0V between transistorized control gate and the interior body region by other non-selected electric charge in described a plurality of electric charges preservation transistors, preserve transistor to suppress described non-selected electric charge.

11. the non-volatile flash memory circuit of NOR as claimed in claim 1 is characterized in that, the described a plurality of electric charges that are programmed to an individual layer programming unit are preserved in the transistors selected electric charge and are preserved transistor and be read by following steps:

Connect source electrode line to a voltage follow sensor circuit;

The voltage of setting interior selecteed electric charge preservation transistor drain of this NOR flash memory circuit and grid is the voltage of voltage source;

Described a plurality of electric charge is preserved non-selected electric charge in the transistor and is preserved the voltage of transistorized grid and be set to one first height and read voltage; And

Voltage and the reference voltage source that produces at source electrode line in this voltage follow sensor circuit relatively, this reference voltage source is set to 2.0V, to distinguish a critical voltage and the critical voltage in second logical value in first logical value.

12. the non-volatile flash memory circuit of NOR as claimed in claim 11 is characterized in that, this first height reads voltage greater than 6.0V.

13. the non-volatile flash memory circuit of NOR as claimed in claim 11 is characterized in that, this reference voltage source is 2.0V.

14. the non-volatile flash memory circuit of NOR as claimed in claim 11, it is characterized in that, if the not selected read operation of the non-volatile flash memory circuit of NOR, and when the selected read operation of the non-volatile flash memory circuit of another NOR, described a plurality of electric charges in non-selected this NOR flash memory circuit are preserved the voltage that non-selected this electric charge is preserved transistorized control gate in the transistor and are set to the ground connection reference voltage, preserve transistor to close this electric charge.

15. the non-volatile flash memory circuit of NOR as claimed in claim 1 is characterized in that, the described a plurality of electric charges that are programmed to a multilayer programming unit are preserved in the transistors selected electric charge and are preserved transistor and be read by following steps:

Connect source electrode line to a voltage follow sensor circuit;

The voltage of setting this selecteed electric charge preservation transistor drain and grid is a middle high voltage;

Described a plurality of electric charges are preserved all non-selected electric charges within the transistors to be preserved the voltage of transistorized grid and is set at one second height and reads voltage; And

Voltage and a plurality of reference voltage source that produces at source electrode line in this voltage follow sensor circuit relatively preserved the data in the transistor to determine a critical voltage value to be used to represent to be stored in electric charge.

16. the non-volatile flash memory circuit of NOR as claimed in claim 15 is characterized in that the high voltage of this centre is+4.0V.

17. the non-volatile flash memory circuit of NOR as claimed in claim 15 is characterized in that, this second height reads voltage greater than 7.0V.

18. the non-volatile flash memory circuit of NOR as claimed in claim 15 is characterized in that, this reference voltage source is set between each critical voltage and is stored in the critical voltage that electric charge is preserved the data in the transistor with difference.

19. the non-volatile flash memory circuit of NOR as claimed in claim 15, it is characterized in that, do not read if the NOR flash memory circuit is selected, the NOR flash memory circuit is selected when reading and when another, described a plurality of electric charges in this non-selected NOR flash memory circuit are preserved non-selected electric charge in the transistors and are preserved the voltage of transistorized control gate and be set to the ground connection reference voltage, preserve transistor to close this electric charge.

20. the non-volatile flash memory component of NOR comprises:

One comprises the array of the non-volatile flash memory circuit of a plurality of NOR, and this array is arranged to row and column, it is characterized in that, each non-volatile flash memory circuit comprises:

A plurality of electric charges in each row are preserved transistor and are connected into NAND string by polyphone;

Topmost electric charge is preserved transistor drain and is connected to bit line with the corresponding this locality of row at each NOR flash memory circuit place in each NOR flash memory circuit;

Bottom electric charge is preserved transistorized source electrode and is connected to source electrode line with the corresponding this locality of row at each NOR flash memory circuit place in each NOR flash memory circuit; And

Electric charge on each row is preserved transistorized each control gate and jointly is connected to a character line.

21. the non-volatile flash memory component of NOR as claimed in claim 20 is characterized in that, this bit line is corresponding with the row at the non-volatile flash memory circuit of this NOR place with source electrode line and be parallel.

22. the non-volatile flash memory component of NOR as claimed in claim 20 is characterized in that, also comprises a column voltage control circuit, is used to provide control signal to arrive bit line and the source electrode line of preserving the corresponding this locality of transistor with each row electric charge.

23. the non-volatile flash memory component of NOR as claimed in claim 22 is characterized in that, each local bit line sees through a bit line selection transistor and one of is connected in a plurality of universe bit lines.

24. the non-volatile flash memory component of NOR as claimed in claim 23 is characterized in that, each local source electrode line sees through one source pole line options transistor and one of is connected in a plurality of universe source electrode lines.

25. the non-volatile flash memory component of NOR as claimed in claim 24, it is characterized in that, this universe bit line and universe source electrode line are connected to this column voltage control circuit,, be used for that the selecteed electric charge of the non-volatile flash memory circuit of NOR is preserved transistor and carry out read operation, programming operation and erase operation to bit line of selecteed this locality and the source electrode line of selecteed this locality with transmission of control signals.

26. the non-volatile flash memory component of NOR as claimed in claim 20 is characterized in that, also comprises delegation's voltage control circuit, is used to provide control signal to arrive with each row electric charge and preserves the corresponding character line of transistor.

27. the non-volatile flash memory component of NOR as claimed in claim 26, it is characterized in that, this line control circuit transmission of control signals carries out read operation, programming operation and erase operation to character line so that selecteed electric charge in the non-volatile flash memory circuit of this NOR is preserved transistor.

28. the non-volatile flash memory component of NOR as claimed in claim 25 is characterized in that, also comprises:

One bit line is selected control circuit, connects the grid of local bit line selection transistor; And

Source electrode line is selected transistor, and described source electrode line selects transistor to be connected to each local bit line.

29. the non-volatile flash memory component of NOR as claimed in claim 20, it is characterized in that, this line control circuit is used for the transmission character line control signal to character line, so that being preserved transistor, selecteed electric charge in the non-volatile flash memory circuit of this NOR carries out read operation, programming operation and erase operation, this line control circuit also is used for transmitting respectively bit line select signal and source electrode line selects signal to selecteed bit line selection transistor and selecteed source electrode line transistor, so that bit line and source electrode line control signal are transferred to bit line of selecteed this locality and the source electrode line of selecteed this locality from the column voltage control circuit.

30. the non-volatile flash memory component of NOR as claimed in claim 20 is characterized in that, described a plurality of electric charges are preserved transistor and are adopted a Fowler-Nordheim tunneling effect to carry out programming operation and erase operation.

31. the non-volatile flash memory component of NOR as claimed in claim 20, it is characterized in that, preserve and apply the program voltage of one+15.0V between transistorized control gate and the interior body region by preserve a selecteed electric charge in the transistors at described a plurality of electric charges, being programmed for the individual layer programming unit by selecteed electric charge preservation transistor to+20.0V.

32. the non-volatile flash memory component of NOR as claimed in claim 31, it is characterized in that, preserve and apply the voltage less than 10.0V between transistorized control gate and the interior body region by preserve in the transistors other non-selected electric charge at described a plurality of electric charges, preserve transistor to suppress described non-selected electric charge.

33. the non-volatile flash memory component of NOR as claimed in claim 20 is characterized in that, it is to make four times to six times of characteristic dimension of the minimum of NOR flash memory circuit technology that this NOR flash memory circuit layout requires the size of this NOR flash memory circuit.

34. the non-volatile flash memory component of NOR as claimed in claim 20, it is characterized in that, apply the anodal erasing voltage of one+15.0V between transistorized interior body region and the control gate by preserving, carry out erase operation so that this selecteed electric charge is preserved transistor to+20.0V at selecteed electric charge.

35. the non-volatile flash memory component of NOR as claimed in claim 20, it is characterized in that, preserve and apply a 0.0V bias voltage between transistorized control gate and the interior body region by preserve in the transistors other non-selected electric charge at described a plurality of electric charges, preserve transistor to suppress described non-selected electric charge.

36. the non-volatile flash memory component of NOR as claimed in claim 20 is characterized in that, the described a plurality of electric charges that are programmed to an individual layer programming unit are preserved in the transistors selected electric charge and are preserved transistor and be read by following steps:

Connect source electrode line to a voltage follow sensor circuit;

The voltage of setting interior selecteed electric charge preservation transistor drain of this NOR flash memory circuit and grid is the voltage of voltage source;

Described a plurality of electric charges are preserved non-selected electric charge in the transistors to be preserved the voltage of transistorized grid and is set to first height and reads voltage; And

Voltage and the reference voltage source that produces at source electrode line in this voltage follow sensor circuit relatively, wherein this reference voltage source is set to 2.0V, to distinguish a critical voltage and the critical voltage in second logical value in first logical value.

37. the non-volatile flash memory component of NOR as claimed in claim 36 is characterized in that, this first height reads voltage greater than 6.0V.

38. the non-volatile flash memory component of NOR as claimed in claim 36 is characterized in that, this reference voltage source is 2.0V.

39. the non-volatile flash memory component of NOR as claimed in claim 36, it is characterized in that, the a plurality of electric charges of character line and non-selected NOR flash memory circuit are preserved non-selected electric charge in the transistors and are preserved the voltage of transistorized control gate and be set to the ground connection reference voltage, preserve transistor to close electric charge.

40. the non-volatile flash memory component of NOR as claimed in claim 20 is characterized in that, the described a plurality of electric charges that are programmed to a multilayer programming unit are preserved in the transistors selected electric charge and are preserved transistor and be read by following steps:

Connect source electrode line to a voltage follow sensor circuit;

The voltage of setting this selecteed electric charge preservation transistor drain and grid is a middle high voltage;

Described electric charge is preserved all non-selected electric charges within the transistor to be preserved the voltage of transistorized grid and is set at one second height and reads voltage; And

Voltage and a plurality of reference voltage source that produces at source electrode line in this voltage follow sensor circuit relatively preserved the data in the transistor to determine a critical voltage value to be used to represent to be stored in electric charge.

41. the non-volatile flash memory component of NOR as claimed in claim 40 is characterized in that the high voltage of this centre is+4.0V.

42. the non-volatile flash memory component of NOR as claimed in claim 40 is characterized in that, this second height reads voltage greater than 7.0V.

43. the non-volatile flash memory component of NOR as claimed in claim 40 is characterized in that, this reference voltage source is set between each critical voltage and is stored in the critical voltage that electric charge is preserved the data in the transistor with difference.

44. the non-volatile flash memory component of NOR as claimed in claim 40, it is characterized in that, the described a plurality of electric charges of character line and non-selected NOR flash memory circuit are preserved non-selected electric charge in the transistors and are preserved the voltage of transistorized control gate and be set to the ground connection reference voltage, preserve transistor to close electric charge.

45. a method that forms the non-volatile flash memory component of NOR may further comprise the steps:

One substrate is provided; And

The non-volatile flash memory circuit of a plurality of NOR is formed an array that comprises row and column, it is characterized in that the formation of the non-volatile flash memory circuit of described NOR comprises the steps:

Form a plurality of electric charges and preserve transistor, and described electric charge preservation transistor is placed to row and row;

A plurality of electric charges in the polyphone row are preserved transistor to form NAND string;

Connect in each NOR flash memory circuit electric charge topmost preserve transistor drain to the bit line of the corresponding this locality of row at each NOR flash memory circuit place;

Connect in each NOR flash memory circuit bottom electric charge preserve transistorized source electrode to the source electrode line of the corresponding this locality of row at each NOR flash memory circuit place; And

The described electric charge that connects on each row is preserved transistorized each control gate to a character line.

46. method as claimed in claim 45 is characterized in that, also comprises:

The non-volatile flash memory circuit of NOR in each row is associated with described bit line and source electrode line; And

Bit line and source electrode line are be arranged in parallel.

47. method as claimed in claim 45 is characterized in that, it is to make four times to six times of characteristic dimension of the minimum of NOR flash memory circuit technology that this NOR flash memory circuit layout requires the size of this NOR flash memory circuit.

48. method as claimed in claim 45 is characterized in that, also comprises:

Form a column voltage control circuit; And

Connect this column voltage control circuit, arrive bit line and the source electrode line of preserving the corresponding this locality of transistor with each row electric charge so that control signal to be provided.

49. method as claimed in claim 48 is characterized in that, also comprises:

The bit line that each is local sees through a bit line selection transistor and one of is connected in a plurality of universe bit lines.

50. method as claimed in claim 45 is characterized in that, also comprises:

The source electrode line that each is local sees through one source pole line options transistor and one of is connected in a plurality of universe source electrode lines.

51. method as claimed in claim 46 is characterized in that, also comprises:

Universe bit line and universe source electrode line are connected to the column voltage control circuit,, be used for that the selecteed electric charge of NOR flash memory circuit is preserved transistor and carry out read operation, programming operation and erase operation to bit line of selecteed this locality and the source electrode line of selecteed this locality with transmission of control signals.

52. method as claimed in claim 46 is characterized in that, also comprises:

Form delegation's voltage control circuit.

53. method as claimed in claim 52 is characterized in that, also comprises:

Connect this row voltage control circuit, to provide at least one control signal to preserving the corresponding character line of transistor with each row electric charge.

54. method as claimed in claim 52 is characterized in that, also comprises:

Connect local selected transistorized grid of bit line and the local selected transistorized grid that links to each other with each local bit line of source electrode line.

55. method as claimed in claim 54 is characterized in that, also comprises:

Transmit signals to character line from this row voltage control circuit, carry out read operation, programming operation and erase operation so that selecteed electric charge in the non-volatile flash memory circuit of NOR is preserved transistor.

56. method as claimed in claim 55, it is characterized in that, also comprise: select control signal to select transistor from this line control circuit transmission, be used for bit line and source electrode line control signal are transferred to bit line of selecteed this locality and the source electrode line of selecteed this locality from the column voltage control circuit to selecteed bit line selection transistor and selecteed source electrode line.

57. method as claimed in claim 45 is characterized in that, described a plurality of electric charges are preserved transistor application one Fowler-Nordheim tunneling effect and are carried out programming operation and erase operation.

58. method as claimed in claim 45, it is characterized in that, preserve between transistorized control gate and the interior body region in the mode that increases gradually and apply the program voltage of one+15.0V by preserve a selecteed electric charge in the transistors at described a plurality of electric charges, being programmed for the individual layer programming unit by selecteed electric charge preservation transistor to+20.0V.

59. method as claimed in claim 45, it is characterized in that, preserve and apply a programming less than 10.0V between transistorized control gate and the interior body region and suppress voltage by preserve in the transistors other non-selected electric charge at described a plurality of electric charges, preserve transistor to suppress described non-selected electric charge.

60. method as claimed in claim 45, it is characterized in that, apply the negative pole erasing voltage of one+15.0v between transistorized interior body region and the control gate by preserving, carry out erase operation so that this selecteed electric charge is preserved transistor to+20.0V at selecteed electric charge.

61. method as claimed in claim 45, it is characterized in that, preserve the bias voltage that applies a 0.0V between transistor controls grid and the interior body region by other non-selected electric charge in described a plurality of electric charges preservation transistors, preserve transistor to suppress described non-selected electric charge.

62. method as claimed in claim 45 is characterized in that, a plurality of electric charges that are programmed to an individual layer programming unit are preserved in the transistors selected electric charge and are preserved transistor and be read by following steps:

Connect source electrode line to a voltage follow sensor circuit;

The voltage of setting interior selecteed electric charge preservation transistor drain of this NOR flash memory circuit and grid is the voltage of voltage source;

Described a plurality of electric charge is preserved non-selected electric charge in the transistor and is preserved the voltage of transistorized grid and be set to one first height and read voltage; And

Comparative voltage is followed a voltage and a reference voltage source that produces at source electrode line in the sensor circuit, and this reference voltage source is set to 2.0V, to distinguish a critical voltage and the critical voltage in second logical value in first logical value.

63. method as claimed in claim 62 is characterized in that, this first height reads voltage greater than 6.0V.

64. method as claimed in claim 62 is characterized in that, this reference voltage source is 2.0V.

65. method as claimed in claim 62, it is characterized in that, the a plurality of electric charges of character line and non-selected NOR flash memory circuit are preserved non-selected electric charge in the transistors and are preserved the voltage of transistorized control gate and be set to the ground connection reference voltage, preserve transistor to close electric charge.

66. method as claimed in claim 45 is characterized in that, a plurality of electric charges that are programmed to a multilayer programming unit are preserved in the transistors selected electric charge and are preserved transistor and be read by following steps:

Connect source electrode line to a voltage follow sensor circuit;

The voltage of setting this selecteed electric charge preservation transistor drain and grid is a middle high voltage;

Preserving within the transistors all non-selected electric charges at a plurality of electric charges preserves transistorized grid voltage and is set to second height and reads voltage; And

Comparative voltage is followed in the sensor circuit voltage and a plurality of reference voltage source that produces at source electrode line, preserves the data in the transistor to determine a critical voltage value to be used to represent to be stored in electric charge.

67., it is characterized in that the high voltage of this standard is+4.0V as the described method of claim 66.

68., it is characterized in that this second height reads voltage greater than 7.0V as the described method of claim 66.

69., it is characterized in that this reference voltage source is set between each critical voltage as the described method of claim 66, be stored in the critical voltage that electric charge is preserved the data in the transistor with difference.

70. as the described method of claim 66, it is characterized in that, the a plurality of electric charges of character line and non-selected NOR flash memory circuit are preserved non-selected electric charge in the transistors and are preserved the voltage of transistorized control gate and be set to the ground connection reference voltage, preserve transistor to close this electric charge.

71. an integrated circuit (IC) apparatus is characterized in that, comprising:

One comprises the array of the non-volatile flash memory circuit of a plurality of NAND, and the non-volatile flash memory circuit of each NAND comprises:

A plurality of electric charges are preserved transistor, are arranged in rows and columns, and wherein each electric charge that lists is preserved transistor to be concatenated into NAND string, and each NAND string has a upper end to select a transistor and a lower end to select transistor;

One comprises the array of the non-volatile flash memory circuit of a plurality of NOR, and wherein the non-volatile flash memory circuit of each NOR comprises:

A plurality of electric charges are preserved transistors, are arranged in rows and columns, and wherein each electric charge that lists is preserved transistor and constituted at least one group and every group of electric charge and preserve strings of transistors and be linked to be NAND string;

Wherein topmost electric charge is preserved the bit line of corresponding this locality in the row that transistor drain is connected to each NOR flash memory circuit place in each NOR flash memory circuit;

Wherein bottom electric charge is preserved the source electrode line of corresponding this locality in the row that transistorized source electrode is connected to each NOR flash memory circuit place in each NOR flash memory circuit; And

Wherein each control gate in a plurality of electric charges preservation transistors on each row is connected to a character line.

72., it is characterized in that in the non-volatile flash memory circuit of each NOR, its neutrality line is corresponding with the row at the non-volatile flash memory circuit of NOR place with source electrode line and be parallel as the described integrated circuit (IC) apparatus of claim 71.

73., it is characterized in that the non-volatile flash memory circuit of each NOR comprises a column voltage control circuit as the described integrated circuit (IC) apparatus of claim 71, be used for providing control signal to preserving the bit line and the source electrode line of the corresponding this locality of transistor with each row electric charge.

74., it is characterized in that in the non-volatile flash memory circuit of each NOR, each local bit line sees through a bit line selection transistor and one of is connected in a plurality of universe bit lines as the described integrated circuit (IC) apparatus of claim 71.

75., it is characterized in that in the non-volatile flash memory circuit of each NOR, each local source electrode line sees through one source pole line options transistor and one of is connected in a plurality of universe source electrode lines as the described integrated circuit (IC) apparatus of claim 74.

76. as the described integrated circuit (IC) apparatus of claim 75, it is characterized in that, in the non-volatile flash memory circuit of each NOR, universe bit line and universe source electrode line are connected to the column voltage control circuit,, be used for that the selecteed electric charge of the non-volatile flash memory circuit of NOR is preserved transistor and carry out read operation, programming operation and erase operation to bit line of selecteed this locality and the source electrode line of selecteed this locality with transmission of control signals.

77., it is characterized in that the non-volatile flash memory circuit of each NOR comprises delegation's voltage control circuit as the described integrated circuit (IC) apparatus of claim 74, be used to provide control signal to arrive and preserve the corresponding character line of transistor with each row electric charge.

78. as the described integrated circuit (IC) apparatus of claim 77, it is characterized in that, in the non-volatile flash memory circuit of each NOR, this line control circuit transmits signals to character line, carries out read operation, programming operation and erase operation so that selecteed electric charge in the non-volatile flash memory circuit of NOR is preserved transistor.

79. as the described integrated circuit (IC) apparatus of claim 78, it is characterized in that, the non-volatile flash memory circuit of each NOR also comprises bit line selection control circuit, this bit line selects control circuit to connect the grid of all local bit line selection transistors, and the multiple source polar curve selects transistor then to be connected to each local bit line.

80. as the described integrated circuit (IC) apparatus of claim 71, it is characterized in that, in the non-volatile flash memory circuit of each NOR, line control circuit transmission character line control signal is to character line, so that being preserved transistor, selecteed electric charge in the non-volatile flash memory circuit of NOR carries out read operation, programming operation and erase operation, this line control circuit also transmits bit line select signal and source electrode line respectively selects signal to selecteed bit line selection transistor and selecteed source electrode line transistor, so that bit line and source electrode line control signal are transferred to bit line of selecteed this locality and the source electrode line of selected this locality from the column voltage control circuit.

81. as the described integrated circuit (IC) apparatus of claim 71, it is characterized in that, in the non-volatile flash memory circuit of each NOR, described a plurality of electric charges are preserved transistor and are adopted one (Fowler-Nordheim) Fowler-Nordheim tunneling effect to carry out programming operation and erase operation.

82. as the described integrated circuit (IC) apparatus of claim 71, it is characterized in that, in the non-volatile flash memory circuit of each NOR, preserve between transistorized control gate and the interior body region in the mode that increases gradually and apply the program voltage of one+15.0V by preserve a selecteed electric charge in the transistors at a plurality of electric charges, be programmed for the individual layer programming unit so that this electric charge is preserved transistor to+20.0V.

83. as the described integrated circuit (IC) apparatus of claim 82, it is characterized in that, in the non-volatile flash memory circuit of each NOR, preserve and apply a programming less than 10.0V between transistorized control gate and the interior body region and suppress voltage by preserve in the transistors other non-selected electric charge at a plurality of electric charges, preserve transistor to suppress described non-selected electric charge.

84. as the described integrated circuit (IC) apparatus of claim 71, it is characterized in that, in the non-volatile flash memory circuit of each NOR, it is to make four times to six times of characteristic dimension of the minimum of NOR flash memory circuit technology that this NOR flash memory circuit layout requires the size of this NOR flash memory circuit.

85. as the described integrated circuit (IC) apparatus of claim 71, it is characterized in that, in the non-volatile flash memory circuit of each NOR, apply the negative pole erasing voltage of one+15.0V between transistorized interior body region and the control gate by preserving, carry out erase operation so that this selecteed electric charge is preserved transistor to+20.0V at selecteed electric charge.

86. as the described integrated circuit (IC) apparatus of claim 71, it is characterized in that, in the non-volatile flash memory circuit of each NOR, preserve the bias voltage that applies a 0.0V between transistorized control gate and the interior body region by other non-selected electric charge in described a plurality of electric charges preservation transistors, preserve transistor to suppress described non-selected electric charge.

87., it is characterized in that in the non-volatile flash memory circuit of each NOR, a plurality of electric charges are preserved the selected electric charge preservation transistor that is programmed to an individual layer programming unit in the transistor and are read by following steps as the described integrated circuit (IC) apparatus of claim 71:

Connect source electrode line to a voltage follow sensor circuit;

The voltage of setting interior selecteed electric charge preservation transistor drain of this NOR flash memory circuit and grid is the voltage of voltage source;

These a plurality of electric charges are preserved non-selected electric charge in transistors and are preserved the voltage of transistorized grid and be set to one first height and read voltage; And

Voltage and the reference voltage source that produces at source electrode line in this voltage follow sensor circuit relatively, this reference voltage source is set to 2.0V, to distinguish a critical voltage and the critical voltage in second logical value in first logical value.

88., it is characterized in that in the non-volatile flash memory circuit of each NOR, this first height reads voltage greater than 6.0V as the described integrated circuit (IC) apparatus of claim 87.

89., it is characterized in that in the non-volatile flash memory circuit of each NOR, the voltage of this reference voltage source is 2.0V as the described integrated circuit (IC) apparatus of claim 87.

90. as the described integrated circuit (IC) apparatus of claim 87, it is characterized in that, the described electric charge of character line and non-selected NOR flash memory circuit is preserved non-selected electric charge in the transistor and is preserved the voltage of transistorized a plurality of control gates and be set to the ground connection reference voltage, preserves transistor to close electric charge.

91. as the described integrated circuit (IC) apparatus of claim 71, it is characterized in that, in the non-volatile flash memory circuit of each NOR, a plurality of electric charges that wherein are programmed to a multilayer programming unit are preserved in the transistors selected electric charge and are preserved transistor and be read by following steps:

Connect source electrode line to a voltage follow sensor circuit;

The voltage of setting this selecteed electric charge preservation transistor drain and grid is a middle high voltage;

A plurality of electric charges are preserved all non-selected electric charges within the transistors to be preserved the voltage of transistorized grid and is set at one second height and reads voltage; And

Voltage and a plurality of reference voltage source that produces at source electrode line in this voltage follow sensor circuit relatively preserved the data in the transistor to determine a critical voltage value to be used to represent to be stored in electric charge.

92., it is characterized in that in the non-volatile flash memory circuit of each NOR, the high voltage of this centre is+4.0V as the described integrated circuit (IC) apparatus of claim 91.

93., it is characterized in that in the non-volatile flash memory circuit of each NOR, this second height reads voltage greater than 7.0V as the described integrated circuit (IC) apparatus of claim 91.

94., it is characterized in that in the non-volatile flash memory circuit of each NOR, this reference voltage source is set between each critical voltage and is stored in the critical voltage that electric charge is preserved the data in the transistor with difference as the described integrated circuit (IC) apparatus of claim 91.

95. as the described integrated circuit (IC) apparatus of claim 91, it is characterized in that, the described a plurality of electric charges of character line and non-selected NOR flash memory circuit are preserved non-selected electric charge in the transistors and are preserved the voltage of transistorized a plurality of control gates and be set to the ground connection reference voltage, preserve transistor to close electric charge.

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