CN101866308A - Picosatellite Star Management System Based on FPGA Expansion - Google Patents

Abstract

The invention discloses a Picosatellite satellite management system based on FPGA expansion, which includes: (a) two satellite computers, one of which is running, and the other is in a warm backup state; (b) a star computer switching module , used to switch between two star computers; (c) analog I2C bus module, used for data acquisition and command transmission of each peripheral subsystem; (d) internal watchdog module, used to monitor the running star computer Whether it works in a normal state and re-initializes the pico-satellite management system; (e) an interrupt module, used for detection and processing of interrupt signals when the star computer communicates with each peripheral subsystem. The pico-satellite management system of the invention can complete the expansion of multi-buses, the sharing of modules, the switching of dual star-service computers and the monitoring of sub-systems.

Description

Picosatellite Star Management System Based on FPGA Expansion

technical field

The invention relates to the field of computers, in particular to an improvement of a pico-satellite management system.

Background technique

Traditional satellites generally adopt fault-tolerant control strategies such as star computer hot backup, cold backup, and mutual backup due to their relatively sufficient size and power consumption. Although the hot backup method has the best real-time performance, it has an arbitration module and the circuit is complicated. When the hot backup comparison of the two machines is inconsistent, it is still impossible to judge the faulty machine. The cold backup method has a monitoring module, and small satellites also need analog circuits to achieve a safe mode. When a failure occurs, they do not have autonomous real-time recovery capabilities and require manual intervention on the ground to recover. The real-time performance is the worst.

The pico-satellite star management system has a high degree of integration, and under the constraints of factors such as volume and power consumption, it is obviously impossible to simply copy the fault-tolerant design method of traditional satellites. It is necessary to adopt a fault-tolerant control strategy that is more suitable and reduces overhead according to the characteristics of the Picosatellite’s satellite management functions.

Contents of the invention

The invention provides a highly reliable, safe and real-time pico-satellite management system based on FPGA expansion, which can realize data expansion, sharing, switching and monitoring of two star computing computers and peripheral subsystems.

A pico-satellite management system based on FPGA expansion, including:

(a) Two star computers, one of which is running and the other is in warm backup state;

(b) star computer switching module, used for switching between two star computers;

The two satellite computers adopt the warm backup method, and when the first computer has problems, all functions and bus connections can be switched to the second computer;

(c) Analog I2C bus module, used for data acquisition and command transmission of each peripheral subsystem;

Each peripheral sub-system can be set according to actual needs, and all of them are connected to the star management system through the analog I2C bus module, so as to realize the data transmission with the star computer;

(d) The internal watchdog module is used to monitor whether the running star computer (including the first star computer and the second star computer) is working in a normal state, and can reset the star management of the Picosatellite The system makes it reinitialize;

(e) The interrupt module is used for detecting and processing the interrupt signal when the satellite computer communicates with each peripheral subsystem.

Described analog I2C bus module comprises:

I2C configuration register (i2ccf), used to set the bus communication rate of the analog I2C bus module and select the communication channel;

I2C control register (i2ccon), used to control the bus transmission of the analog I2C bus module and provide status information;

And the I2C data register (i2cdat), which is used to hold the transmitted or received data bytes.

The internal watchdog module includes:

Overflow times counter (cnt_wdt), used to record the number of times reset and cleared;

Reset and clear the control register (cnt_clrcon), which is used to clear the overflow times counter (cnt_wdt), and the state of the total overflow counter (cnt_rst) is also reflected in it;

The total overflow counter (cnt_rst) is used to output the overflow reset signal cnt_rst_ov to the star service computer switching module (recv_sel) when the number of times of reset and clearing recorded by the overflow count counter (cnt_wdt) reaches 5 times, indicating that the star service computer needs to be switched;

and two registers for temporary storage of data.

The pico-satellite management system of the present invention adopts a warm backup mode, which does not require an arbitration circuit. Although the switching time between the two machines is slightly longer than that of the hot backup mode, this kind of fault-tolerant mode is suitable for pico-satellites whose attitude changes are relatively slow under the control of flywheels and magnetic torque devices. The control strategy is suitable enough, and it can be switched automatically when a fault occurs, which improves the reliability and safety of the pico-satellite, and the real-time performance is also good.

Picosatellite management system is a key subsystem of satellite system monitoring management and data collection, which can monitor the operating status of each subsystem in real time, and regularly collect and store the status data of each subsystem and sensor data during the satellite’s in-orbit process , in the measurement and control arc, the data is sent back under the command of the ground. In addition, the star computer has a comprehensive test interface, which is used as a data channel for the whole star test. It can be seen that the star management system is the key core of the whole star. In order to complete the expansion of multi-buses, the sharing of modules, the switching of dual star computers, and the monitoring of subsystems, the star must necessarily need a comprehensive link between the star computers and the underlying systems. Very functional parts.

FPGA sets up modules in Picosatellite management system according to needs, and programming solves complex logic functions. At the same time, all aspects of design are based on the guarantee of system reliability for the needs of on-board work, and it is very easy to use FPGA. It meets the characteristics of low power consumption, small size and low cost pico-satellite.

The pico-satellite management system of the present invention combines the specific characteristics of pico-satellites "light weight, small size, low cost, and short development cycle", and builds a fault-tolerant structure of the system with a dual-mode redundancy scheme in the fault-tolerant design of the hardware. Operational requirements implement FPGA-based scaling, sharing, switching, and monitoring for pico-satellites. The expansion of multi-bus, the sharing of modules, the switching of dual satellite computers, the monitoring of sub-systems, etc. have been completed, and the good results have been verified through the comprehensive test software in the pico-satellite prototype and ground tests.

Description of drawings

Fig. 1 is the overall structural block diagram of pico-satellite star service management system of the present invention;

Fig. 2 is the state diagram (finite state machine FSM) of the logical state change of the I2C of pico-satellite star affairs management system of the present invention;

Fig. 3 is the sequence diagram of reading data by the star computer of the present invention by simulating the I2C bus module;

Fig. 4 is the sequence diagram of writing data by the star computer of the present invention through the simulation I2C bus module;

Fig. 5 is the interface schematic diagram of star affairs computer switch module;

Fig. 6 is a schematic diagram of calling the internal watchdog module signal to realize switching by the switching module of the star computer;

Fig. 7 is a schematic diagram of the realization of signals full_rstn and mcu_rst in the switch module of the star computer;

Fig. 8 is a schematic diagram of the interface of the star computer switching module;

Fig. 9 is the realization schematic diagram of star affairs computer switching module;

Figure 10 is a schematic diagram of the interface of the interrupt module;

Figure 11 is the composition of the interrupt register in the interrupt module;

Figure 12 is a schematic diagram of the implementation of the interrupt module;

Fig. 13 is a schematic diagram of the working mode of the SPI interface in the SPI interface selection module;

FIG. 14 is a schematic diagram of a chip selection generation module.

Detailed ways

Referring to Fig. 1, the pico-satellite pico-satellite of the present invention is based on the FPGA-extended star service management system including:

Two star computers

As shown in Fig. 1, when one of the satellite computer A and the satellite computer B is running, the other is in a warm backup state.

In addition, referring to the solid line frame in Figure 1, the star management system also includes:

Analog I2C bus module

It is used for data acquisition and command transmission of each peripheral subsystem. Each peripheral subsystem is connected to the management system through an analog I2C bus module, and then realizes data transmission with two star computers. The analog I2C bus module includes:

(1) I2C configuration register (i2ccf)

The I2C configuration register is used to enable the analog I2C bus module to set the bus communication rate and the selection of the communication channel. The relevant signs are as follows:

I2CEN RSV I2CCS3 I2CCS2 I2CCS1 I2CCS0 I2CCD1 I2CCD0

I2CEN enables the analog I2C-bus module when set.

I2CCS[3:0] is used to select the I2C communication channel, and each status value corresponds to the I2C communication line.

I2CCD[1:0] sets the bus communication speed.

(2) I2C control register (i2ccon)

The I2C control register is used to control the bus transmission of the analog I2C bus module and provide status information. The upper 5 bits in i2ccon can form a status information. The star computer can use the status vector to transfer to the corresponding service program. The identification of i2ccon is as follows:

SI I2CBUSY TXM STA STO RSV ACK RSV

SI is the interrupt flag bit. When the following situations occur: send a byte and receive ACK/NACK, receive a byte and send ACK/NACK, the hardware will set SI, and it will be cleared by software. It should be noted that the SI setting will not generate an interrupt signal to the star computer, and it needs to be operated by querying.

I2CBUSY is the I2C communication busy flag. When the I2C module performs serial communication, this bit is set by hardware, and when the communication ends, this bit is cleared by hardware. The I2CBUSY bit is read-only and cannot be written to I2CBUSY.

TXM is the sending status flag bit. When TXM is 1, it means that the I2C module is in the sending status. When TXM is 0, it means that the I2C module is in the receiving status. The TXM bit is a read-only bit and cannot be written to TXM.

STA is the start flag bit. When STA is set, it sends a start signal or sends a repeated start signal after receiving ACK; STA must be cleared by software.

STO is the stop flag bit. When STO is set, a stop signal is sent. If both STA and STO are set, a repeated start signal is generated.

ACK is an acknowledgment flag bit, ACK is defined as the ACK level to be sent is the received ACK level, 0 means "non-acknowledgement" bit, 1 means "acknowledgement" bit.

(3) I2C data register (i2cdat)

The I2C data register i2cdat holds the serial data byte to be sent or just received. Data is stable when the SI flag is set to '1', at which point software can safely read/write the data register. Software should not access the i2cdat register when I2C is enabled but the SI flag is cleared to logic '0' as the hardware may be shifting data bytes in or out of this register. Data in i2cdat is always shifted out MSB first. After a byte is received, the first bit of the received data is in the MSB of i2cdat.

The entire analog I2C bus module is realized by a finite state machine, and the framework of the finite state machine is shown in Figure 2:

FSM has nine working states, which are idle (IDLE), send start condition (START), send stop condition (STOP), send address (X_ADDR), send data (X_DATA), receive data (R_DATA), interrupt wait (INT ), send acknowledgment (X_ACK), receive acknowledgment (R_ACK).

BIT_CNT in the FSM is a digit counter, which is used to control the transmission of 8-bit data, and the rest of the trigger information is the control bit of the I2C control register.

Fig. 3 and Fig. 4 are when the mission computer reads and writes data through the I2C bus, the mission computer and the expansion FPGA work.

Internal watchdog module:

Overflow count counter (cnt_wdt)

Reset and clear control register (cnt_clrcon);

total overflow counter (cnt_rst);

register(cnt_clrcon_buf);

and register (cnt_clrcon).

The overflow counter directly reflects the function of the watchdog. Once it overflows, the watchdog will perform its proper reset function. The reset clearing control register is the way and channel for the star computer to clear the overflow times counter.

Under normal circumstances, the mission computer (referring to the execution mechanism of mission computer A and or mission computer B is exactly the same, and they all operate in this way) clears the overflow times counter by writing the reset and clear control register every 1s, and the overflow times counter is It will not overflow; but if the overflow counter is not cleared within 3s, an internal watchdog overflow flag signal (cnt_wdt_ov) will be generated.

The total overflow counter (cnt_rst), as shown in Figure 6, belongs to the internal watchdog module. The overflow count counter (cnt_wdt) is counted by time. When the time is not reset, an overflow flag signal cnt_wdt_ov will be generated. The total overflow counter (cnt_rst) will respond to the overflow flag signal cnt_wdt_ov counts, when the number of counts reaches 5 times, that is, when the internal watchdog module resets 5 times (resetting the internal watchdog module 5 times means that the overflow counter overflows 5 times), an overflow reset signal cnt_rst_ov is generated, the signal It can control the switch between two star computers. The overflow times counter (cnt_wdt) and the total overflow counter (cnt_rst) are also reflected in the register (cnt_clrcon_buf). When the star mission computer does not perform read and write operations on the register (cnt_clrcon), the data in the register (cnt_clrcon_buf) will be updated to register (cnt_clrcon) (implemented in parallel_bus.v). The star computer can know the reset situation in the FPGA by reading the register (cnt_clrcon), see Figure 5 and Figure 6.

In addition, the internal watchdog module also generates a comprehensive reset signal full_rstn, which is the synthesis of the internal watchdog overflow flag signal cnt_wdt_ov, the switching flag signal sel_ov, and the global reset signal sys_rstn. When the above three signals are generated, the synthesis will be triggered at the same time. The generation of the reset signal full_rstn, with this comprehensive reset signal, the system state can be re-initialized once, which will be very safe for the system operation, see Figure 7.

The overflow count counter (cnt_wdt) enables the 3Hz signal as a clock, and when the clock enable is 1, it counts the global clock, otherwise, it remains unchanged. When the overflow times counter (cnt_wdt) counts to 9, that is, when 3s arrives, the watchdog overflows, and the overflow flag signal cnt_wdt_ov is valid, which makes the counter cnt_rst count by 1. When the overflow flag signal cnt_wdt_ov makes the total overflow counter (cnt_rst) When the number of counts reaches 5 times, another reset overflow signal cnt_rst_ov is valid, and the signal is transmitted to the star computer switching module (recv_sel) for switching control.

When the rising edge of the comprehensive signal (!sys_rstn)||sel_ov||cnt_wdt_ov) is detected, a 250-ary counter is triggered to start counting the global clock signal. During the counting process, the signal full_rstn outputs a low level, and the signal mcu_rst outputs a high level, when the counter counts over, the signal full_rstn outputs a high level, and the signal mcu_rst outputs a low level.

Star computer switching module:

It is used for switching between two satellite computers. The two satellite computers adopt warm backup mode. When the first computer has problems, all functions and bus connections can be switched to the second computer.

The mission computer switching module can generate the switching control signal sel, the switching flag signal sel_ov, and the status flag of the mission computer are all reflected in the mission computer status buffer register mcusta_buf.

There are two control methods for switching:

The internal watchdog module of the star expansion FPGA is reset 5 times (hereinafter referred to as: mode 1, and the related signal is cnt_rst_ov);

and the switching command of the remote control command (hereinafter referred to as: mode 2, and the related signal is back_cha).

In order to prevent star computer A from switching back to star computer A after switching to star computer B, the switching quasi-prohibit enable control line back_chaen is added.

When the sel signal changes, the star computer switching module will output a high-level pulse signal sel_ov that lasts for 5 global clock cycles.

The status buffer register mcusta_buf of the mission computer can be used to indicate the number of switching times, the status of the currently working mission computer and the switching quasi-forbidden signal. The upper 4 bits ([7:4]) are used to indicate the switching times, the next 2 bits ([3:2]) indicate the label of the current working computer (00 means star computer A, 11 means star computer B), and the last 2 bits Bits ([1:0]) indicate switching quasi-forbidden signal status (00 means forbidden, 11 means quasi).

Referring to Fig. 8 and Fig. 9, there are two control modes for star computer switching: switching mode 1: obc_cha, this switching mode is controlled by back_chaen, and only when flag==1'b0 is satisfied, this mode works; Switching method 2: back_cha, this switching method is not limited by other signals, and when this method works, the flag will be cleared. Regardless of the switching method, as long as the star mission computer switches, the sel signal must be inverted, the cnt_sel register must be incremented by 1, and sel_ov must output a high-level pulse that lasts for 5 global clock cycles. At the same time, the star computer status buffer register mcusta_buf will also change accordingly.

Interrupt module:

It is used for the detection and processing of interrupt signals when the satellite computer communicates with various peripheral subsystems (in Figure 1, only an arrow coming in from the outside is drawn and written "5 external interrupts", indicating that the peripheral The management system interrupts operation).

The interrupt module has 5 external interrupt sources, which are the interrupt signal of the attitude control subsystem, the interrupt signal of the modem module of the analog measurement and control transponder, the interrupt signal of the modem module of the digital measurement and control transponder, the interrupt signal of the separation moment of the front cover separation switch, The rear cover separation switch disconnects the momentary interrupt signal. After the interrupt module detects the interrupt signal, it generates an interrupt signal to the satellite computer according to the permission of the interrupt, so that the satellite computer executes the corresponding program.

The corresponding register of the interrupt module is the interrupt control register interrupt (as shown in Figure 11), which is divided into an interrupt enable control bit and an interrupt flag bit. The five bits FADCS, FDPSKA, FDPSKD, FSEFP, and FSEPB are interrupt flag bits. When the interrupt module detects an interrupt signal, the corresponding interrupt flag bit is set; ESEFP, ESEFB, and EA are interrupt enable bits. Interrupt flag bits need to be cleared by software, see Figure 10.

Among the five external interrupt sources shown in Figure 11, the interrupt signal at the moment of separation of the front cover separation switch and the momentary interruption signal of the separation of the rear cover separation switch remain low after the falling edge occurs, and the other three interrupt signals are It is to give a high level pulse, but the duration of the high level is different. In order to unify the follow-up processing of the interrupt signal, the interrupt signal is passed through the intneg_intn.v module when the front and rear cover separation switches are separated, and the other three interrupt signals are processed by the intpos_intpulse.v module. The output of the interrupt signal is 5 global Low or high pulse of the clock cycle.

Refer to Figure 12, Figure 12 shows that the three interrupt sources of adcs_int, digital_int, and analog_int set the corresponding interrupt flag position after passing through the intpos_intpulse module, and the interrupt sources of backf_intn and backb_intn pass through the intneg_intn module, and then pass the logical negation to the corresponding interrupt When the flag bit is set, when FADCS, FDPSKA, and FDPSKD are set, as long as the EA bit in interrupt is 1, the star computer will receive the interrupt signal. When FSEFP or FSEPB is set, ESEFP or ESEFB and EA in interrupt are required If it is 1, the star computer will receive the interrupt signal.

In order to further improve the functions of the pico-satellite management system of the present invention, the pico-satellite management system is also provided with an SPI interface selection module, a chip selection generation module, a clock generation module, and an LED display module.

SPI interface selection module:

Referring to Figure 1, there are three sets of SPI interfaces in the SPI interface selection module in Figure 1, which refer to: the common SPI interface for two measurement and control transponders, the SPI interface for attitude control, the SPI interface for four EEPROMs and the CPLD for cameras.

According to the chip selection control register cscon to determine which group of SPI interface to use, the star computer only sets one bit in cscon.

The SPI interface (referring to the three groups of SPI interfaces mentioned above) has 4 working modes, as shown in Figure 13.

CPOL: Clock polarity selection bit. When this bit is 1, SCLOCK outputs high level when idle; when cleared, SCLOCK outputs low level when idle.

CPHA: Clock phase selection bit. When this bit is set to 1, data is sent on the leading edge of SCLOCK; when it is cleared to 0, data is sent on the trailing edge of SCLOCK.

The mode adopted by the SPI interface of the slave device is: CPOL=0, CPHA=0.

Therefore, the host computer should also be consistent with it, namely: CPOL=0, CPHA=0.

Therefore, when writing a program, the SCLK of the SPI interface that is not selected should output a low level.

Chip selection generation module:

The chip selection generation module is mainly used to output chip selection (synchronization) signals when the star computer and each slave device perform SPI communication. The slave devices involved include: digital measurement and control transponder modem module DSP, analog measurement and control transponder modem Module DSP, attitude control system DSP, payload CPLD, data storage EEPROM1, EEPROM2, EEPROM3 and EEPROM4. There are 8 chip select signals, which are used to distinguish different communication lines.

The star computer controls which slave device to communicate with by writing the chip select control register cscon, and the FPGA is responsible for corresponding each bit in cscon with the corresponding chip select output. It should be noted that some of the slave device chip select signals output from the FPGA are active at high levels and some are active at low levels, while in cscon it is set to indicate that the device is selected. The chip select signal needs to be cleared by software. See Figure 14.

Clock generation module:

Realize the frequency division of the global clock.

Through frequency division, the payload CPLD clock is given;

Through frequency division, the star computer clock is given.

LED display module:

The LED register data in the star CPLD is displayed on the LED, which is convenient for debugging and observation.

Data expansion, sharing, switching and monitoring.

See Figure 1, Figure 1 reflects the connection relationship diagram of all electrical systems of the entire pico-satellite centered on the star management system. The entire electrical system includes the following subsystems:

Star mission subsystem: including star mission computer and FPGA with extended functions;

Measurement and control subsystem: including digital measurement and control and analog measurement and control two measurement and control transponders;

Attitude control subsystem: the subsystem that controls the attitude of the satellite;

Payload subsystem: including temperature sensor, accelerometer and gyroscope, CMOS camera, etc.;

Power supply subsystem: the subsystem that controls the power supply of the whole star.

Claims (2)

1. the Picosat house-keeping system based on the FPGA expansion is characterized in that, comprising:

(a) two Star Service computing machines, wherein when operation, another is in the warm spare state;

(b) Star Service computing machine handover module is used for the switching of two Star Service computing machines;

(c) Simulation with I 2C bus module, the data acquisition and the order that are used for each peripheral subsystem transmit;

(d) inner watchdog module is used to monitor the Star Service computing machine that is moving and whether is operated in normal condition and described Picosat house-keeping system is reinitialized;

(e) interrupt module, the detection and the processing of look-at-me when being used for the Star Service computing machine and communicating by letter with each peripheral subsystem.

2. Picosat house-keeping system as claimed in claim 1 is characterized in that, described Simulation with I 2C bus module comprises:

The I2C configuration register is used to be provided with the bus communication speed of Simulation with I 2C bus module and selects communication channel;

The I2C control register is used to control the bus transfer of Simulation with I 2C bus module and status information is provided;

And the I2C data register, be used to preserve the data byte that sends or receive.

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