CN101833432B - Tri-valued, thermal-insulating and low-power adder unit and adder - Google Patents

Tri-valued, thermal-insulating and low-power adder unit and adder Download PDF

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CN101833432B
CN101833432B CN2010101542930A CN201010154293A CN101833432B CN 101833432 B CN101833432 B CN 101833432B CN 2010101542930 A CN2010101542930 A CN 2010101542930A CN 201010154293 A CN201010154293 A CN 201010154293A CN 101833432 B CN101833432 B CN 101833432B
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nmos pipe
nmos
input signal
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sampled value
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CN101833432A (en
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汪鹏君
李昆鹏
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Ningbo University
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Ningbo University
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Abstract

本发明公开了一种三值绝热低功耗加法器单元及加法器，首先用钟控时钟信号控制输入信号采样电路中的各个NMOS管对各输入信号进行采样，然后采样得到的各采样值按照要求实现的加法逻辑关系通过自举操作的NMOS管构建相应的四个求和电路模块和交叉存贮型结构的进位输出电路，功率时钟Φ1、Φ通过四个求和电路模块和进位输出电路完成对输出负载的赋值和能量回收，能够实现正确的逻辑功能；与由门电路实现的三值全加器相比，本发明的加法器单元的电路延迟和面积更小、功耗更低；与DPL三值加法器相比，本发明的加法器在0.9μs时间内，本发明的加法器能够节省能耗约90％左右，具有明显的低功耗特性。

The invention discloses a ternary adiabatic low power consumption adder unit and an adder. Firstly, each NMOS tube in the input signal sampling circuit is controlled by a clock-controlled clock signal to sample each input signal, and then each sampling value obtained by sampling is according to The addition logic relationship required to be realized is constructed through the NMOS tube of the bootstrap operation corresponding four summation circuit modules and the carry output circuit of the interleaved memory structure, and the power clock Φ 1 and Φ pass through the four summation circuit modules and the carry output circuit Completing the assignment of the output load and energy recovery can realize correct logic functions; compared with the ternary full adder realized by the gate circuit, the circuit delay and area of the adder unit of the present invention are smaller, and the power consumption is lower; Compared with the DPL ternary adder, the adder of the present invention can save about 90% of energy consumption within 0.9 μs, and has obvious low power consumption characteristics.

Description

A kind of tri-valued, thermal-insulating and low-power adder unit and totalizer
Technical field
The present invention relates to a kind of totalizer, especially relate to a kind of tri-valued, thermal-insulating and low-power adder unit and totalizer.
Background technology
Adder unit (being full adder) is the elementary cell of computing circuit, is one of critical component of digital circuitry, and optimizing its design is the key that obtains the high performance computation circuit.So far existing multiple full adder design proposal; Like disclosed in the electronic letters, vol " 45nm low-power consumption, the design of high-performance Zipper CMOS domino full adder " (author: Wang Jinhui, palace Na, Geng Shuqin etc.); It has utilized electric charge self compensation technical design Zipper CMOS domino full adder, with the discharge of P type domino circuit dynamic node the mode that N type domino circuit dynamic node charges is reduced power consumption; Disclosed in microelectronics and the computing machine " the complementary transfer tube totalizer of the non-full swing of low-power consumption " (author: Wang Zongjing, Qi Jiayue); It has adopted two differential configuration designs C PL (Complementary Pass-transistor Logic) full adder, utilizes the low amplitude of oscillation of internal signal to realize high speed and low-power consumption characteristic etc.But these full adders all are to adopt the DC power supply mode; Energy always transforms to the irreversible form of heat energy with electric energy; Though can adopt methods such as reduction supply voltage and node capacitor, the redundant saltus step of minimizing switch to reduce power consumption, the amplitude of its Power Cutback is very limited.
Yet in IC design, area and power consumption are two important indicators of decision-making circuit combination property.Along with the progress of semiconductor process techniques, the area that gate circuit etc. take sharply descends, and has silicon area more than 70% to be used for wiring on the contrary, limited thus integrated circuit integrated level, improved production cost.MULTI-VALUED LOGIC CIRCUIT (like many-valued full adder) is carried the ability of information and the information density of integrated circuit owing to can improve single line, therefore can reduce the line between IC system, saves the relevant chip area.But present MULTI-VALUED LOGIC CIRCUIT great majority realize that through adopting the two-value element circuit structure is quite complicated, power hungry.
Summary of the invention
Technical matters to be solved by this invention provides a kind of guaranteeing to have under the prerequisite of correct logic functions, can effectively reduce the tri-valued, thermal-insulating adder unit and the totalizer of power consumption.
The present invention solves the problems of the technologies described above the technical scheme that is adopted: a kind of tri-valued, thermal-insulating and low-power adder unit; The input signal of this adder unit comprises addend input signal, summand input signal, low level carry input signal, complementary addend input signal, complementary summand input signal and complementary low level carry input signal; This adder unit comprises input signal sample circuit, summation output circuit and carry output circuit; The signal input part of described input signal sample circuit is imported the summand input signal of described addend input signal, described summand input signal, described low level carry input signal, the addend input signal of described complementation, described complementation and the low level carry input signal of described complementation; Described input signal sample circuit inserts the clock clock signal of amplitude level counterlogic 2; The clock clock signal of described amplitude level counterlogic 2 is controlled described input signal sample circuit the summand input signal of described addend input signal, described summand input signal, described low level carry input signal, the addend input signal of described complementation, described complementation and the low level carry input signal of described complementation is sampled, and the signal output part of described input signal sample circuit is exported the summand input signal of described addend input signal, described summand input signal, described low level carry input signal, the addend input signal of described complementation, described complementation and each self-corresponding one group of sampled value of low level carry input signal of described complementation;
Described summation output circuit mainly is made up of four summing circuit modules; The signal input part of four described summing circuit modules is all imported the corresponding sampled value of the addend input signal of the corresponding sampled value of described addend input signal, the sampled value that described summand input signal is corresponding, described complementation and the corresponding sampled value of summand input signal of described complementation; Four described summing circuit modules all insert the power clock signal of amplitude level counterlogic 2 and the power clock signal of amplitude level counterlogic 1 respectively, and four described summing circuit modules are designated as S respectively 0,
Figure GSA00000075646500021
S 2With
Figure GSA00000075646500022
Described S 0The signal output part of summing circuit module and described
Figure GSA00000075646500023
The feedback signal input end of summing circuit module is connected, and is described The signal output part of summing circuit module and described S 0The feedback signal input end of summing circuit module is connected, described S 2The signal output part of summing circuit module and described
Figure GSA00000075646500025
The feedback signal input end of summing circuit module is connected, and is described
Figure GSA00000075646500026
The signal output part of summing circuit module and described S 2The feedback signal input end of summing circuit module is connected, described S 0The signal output part of summing circuit module and described summation output circuit are used to export between the signal output part of summation output signal and are provided with NMOS pipe, the source electrode and the described S of described NMOS pipe 0The signal output part of summing circuit module is connected; The drain electrode of described NMOS pipe and described summation output circuit are used to export the signal output part that summation exports signal and are connected; The grid of described NMOS pipe inserts the corresponding sampled value of low level carry input signal of described complementation, and is described
Figure GSA00000075646500027
The signal output part of summing circuit module and described summation output circuit are used to export between the signal output part of complementary summation output signal and are provided with the 2nd NMOS pipe, the source electrode of described the 2nd NMOS pipe and described
Figure GSA00000075646500028
The signal output part of summing circuit module is connected; The drain electrode of described the 2nd NMOS pipe and described summation output circuit are used to export the signal output part that complementary summation exports signal and are connected; The grid of described the 2nd NMOS pipe inserts the corresponding sampled value of low level carry input signal of described complementation, described S 2The signal output part of summing circuit module and described summation output circuit are used to export between the signal output part of summation output signal and are provided with the 3rd NMOS pipe, the source electrode and the described S of described the 3rd NMOS pipe 2The signal output part of summing circuit module is connected; The drain electrode of described the 3rd NMOS pipe and described summation output circuit are used to export the signal output part that summation exports signal and are connected; The grid of described the 3rd NMOS pipe inserts the corresponding sampled value of described low level carry input signal, and is described The signal output part of summing circuit module and described summation output circuit are used to export between the signal output part of complementary summation output signal and are provided with the 4th NMOS pipe, the source electrode of described the 4th NMOS pipe and described
Figure GSA00000075646500032
The signal output part of summing circuit module is connected; The signal output part that the drain electrode of described the 4th NMOS pipe and described summation output circuit are used to export complementary summation output signal is connected, and the grid of described the 4th NMOS pipe inserts the sampled value of described low level carry input signal correspondence;
The signal input part of described carry output circuit is imported the corresponding sampled value of the summand input signal of the corresponding sampled value of the addend input signal of the corresponding sampled value of described addend input signal, the sampled value that described summand input signal is corresponding, the sampled value that described low level carry input signal is corresponding, described complementation, described complementation and the corresponding sampled value of low level carry input signal of described complementation; Described carry output circuit inserts the power clock signal of amplitude level counterlogic 2, the signal output part output carry output signal and the complementary carry output signals of described carry output circuit.
Be provided with the 5th NMOS pipe, the 6th NMOS pipe, the 7th NMOS pipe and the 8th NMOS pipe in the described summation output circuit, the source electrode of described the 5th NMOS pipe respectively with described S 0Summing circuit module and described The input end that the summing circuit module is used to insert the power clock signal of described amplitude level counterlogic 2 is connected, the source electrode of described the 6th NMOS pipe respectively with described S 2Summing circuit module and described
Figure GSA00000075646500034
The input end that the summing circuit module is used to insert the power clock signal of described amplitude level counterlogic 2 is connected; The drain electrode of the drain electrode of described the 5th NMOS pipe and described the 6th NMOS pipe all inserts the power clock signal of described amplitude level counterlogic 2, and the source electrode of described the 7th NMOS pipe is respectively with described
Figure GSA00000075646500035
Summing circuit module and described S 0The input end that the summing circuit module is used to insert the power clock signal of described amplitude level counterlogic 1 is connected, and the source electrode of described the 8th NMOS pipe is respectively with described
Figure GSA00000075646500036
Summing circuit module and described S 2The input end that the summing circuit module is used to insert the power clock signal of described amplitude level counterlogic 1 is connected; The drain electrode of the drain electrode of described the 7th NMOS pipe and described the 8th NMOS pipe all inserts the power clock signal of described amplitude level counterlogic 1; The grid of the grid of described the 5th NMOS pipe and described the 7th NMOS pipe interconnects with the grid of described NMOS pipe and the grid of described the 2nd NMOS pipe respectively, and the grid of the grid of described the 6th NMOS pipe and described the 8th NMOS pipe interconnects with the grid of described the 3rd NMOS pipe and the grid of described the 4th NMOS pipe respectively.
Described S 0The summing circuit module comprises a NMOS pipe group, the 2nd NMOS pipe group, the 3rd NMOS pipe group, the 4th NMOS pipe group, the 5th NMOS pipe group, the 6th NMOS pipe group, the 9th NMOS pipe and PMOS pipe; A described NMOS pipe group mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; Described the 2nd NMOS pipe group mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes and drain electrode head and the tail serial connection; Described the 3rd NMOS pipe group mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes and drain electrode head and the tail serial connection; Described the 4th NMOS pipe group mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; Described the 5th NMOS pipe group mainly is made up of the four NMOS pipe; And the source electrode of four NMOS pipe and drain electrode head and the tail serial connection; Described the 6th NMOS pipe group mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; The drain electrode of the drain electrode of the drain electrode of first NMOS pipe of a described NMOS pipe group, first NMOS pipe of described the 2nd NMOS pipe group and first NMOS pipe of described the 3rd NMOS pipe group inserts the power clock signal of described amplitude level counterlogic 1 respectively; The source electrode of the source electrode of the source electrode of last NMOS pipe of a described NMOS pipe group, last NMOS pipe of described the 2nd NMOS pipe group and last NMOS pipe of described the 3rd NMOS pipe group is connected with the signal output part of described S0 summing circuit module respectively; The grid of two NMOS pipes of a described NMOS pipe group is imported corresponding sampled value of described addend input signal and the corresponding sampled value of described summand input signal respectively; The grid of three NMOS pipe of described the 2nd NMOS pipe group is imported the corresponding sampled value of the addend input signal of the corresponding sampled value of described addend input signal, described complementation and the corresponding sampled value of summand input signal of described complementation respectively; The grid of three NMOS pipe of described the 3rd NMOS pipe group is imported the corresponding sampled value of the summand input signal of the corresponding sampled value of described summand input signal, described complementation and the corresponding sampled value of addend input signal of described complementation respectively; The drain electrode of the drain electrode of the drain electrode of first NMOS pipe of described the 4th NMOS pipe group, first NMOS pipe of described the 5th NMOS pipe group and first NMOS pipe of described the 6th NMOS pipe group inserts the power clock signal of described amplitude level counterlogic 2 respectively, the source electrode of the source electrode of the source electrode of last NMOS pipe of described the 4th NMOS pipe group, last NMOS pipe of described the 5th NMOS pipe group and last NMOS pipe of described the 6th NMOS pipe group respectively with described S 0The signal output part of summing circuit module is connected; The grid of two NMOS pipes of described the 4th NMOS pipe group is imported the corresponding sampled value of summand input signal of corresponding sampled value of described addend input signal and described complementation respectively; The grid of the four NMOS pipe of described the 5th NMOS pipe group is imported corresponding sampled value, the sampled value of described summand input signal correspondence and the corresponding sampled value of summand input signal of described complementation of addend input signal of the corresponding sampled value of described addend input signal, described complementation respectively; The grid of two NMOS pipes of described the 6th NMOS pipe group is imported the corresponding sampled value and the corresponding sampled value of described summand input signal of addend input signal of described complementation respectively; The drain electrode of described PMOS pipe inserts the power clock signal of described amplitude level counterlogic 2, the drain electrode of the source electrode of described PMOS pipe and described the 9th NMOS pipe respectively with described S 0The signal output part of summing circuit module is connected, the grid of described PMOS pipe respectively with the grid and the described S of described the 9th NMOS pipe 0The feedback signal input end of summing circuit module is connected, and the source electrode of described the 9th NMOS pipe connects power supply ground;
Described
Figure GSA00000075646500051
summing circuit module comprises the 7th NMOS pipe group, the 8th NMOS pipe group, the 9th NMOS pipe group, the tenth NMOS pipe group, the 11 NMOS pipe group, the 12 NMOS pipe group, the tenth NMOS pipe and the 2nd PMOS pipe; Described the 7th NMOS pipe group mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes and drain electrode head and the tail serial connection; Described the 8th NMOS pipe group mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes and drain electrode head and the tail serial connection; Described the 9th NMOS pipe group mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; Described the tenth NMOS pipe group mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes and drain electrode head and the tail serial connection; Described the 11 NMOS pipe group mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes mainly is made up of two NMOS pipes with drain electrode head and the tail serial connection, described the 12 NMOS pipe group, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; The drain electrode of the drain electrode of the drain electrode of first NMOS pipe of described the 7th NMOS pipe group, first NMOS pipe of described the 8th NMOS pipe group and first NMOS pipe of described the 9th NMOS pipe group inserts the power clock signal of described amplitude level counterlogic 2 respectively; The source electrode of the source electrode of the source electrode of last NMOS pipe of described the 7th NMOS pipe group, last NMOS pipe of described the 8th NMOS pipe group and last NMOS pipe of described the 9th NMOS pipe group is connected with the signal output part of described
Figure GSA00000075646500052
summing circuit module respectively, and the grid of three NMOS pipes of described the 7th NMOS pipe group is imported the corresponding sampled value of the corresponding sampled value of described summand input signal, described addend input signal and the corresponding sampled value of addend input signal of described complementation respectively, and the grid of three NMOS pipes of described the 8th NMOS pipe group is imported the corresponding sampled value of the corresponding sampled value of described addend input signal, described summand input signal and the corresponding sampled value of summand input signal of described complementation respectively; The grid of two NMOS pipe of described the 9th NMOS pipe group is imported the corresponding sampled value of the addend input signal of described complementation and the corresponding sampled value of summand input signal of described complementation respectively; The drain electrode of the drain electrode of the drain electrode of first NMOS pipe of described the tenth NMOS pipe group, first NMOS pipe of described the 11 NMOS pipe group and first NMOS pipe of described the 12 NMOS pipe group inserts the power clock signal of described amplitude level counterlogic 1 respectively, and the source electrode of the source electrode of the source electrode of last NMOS pipe of described the tenth NMOS pipe group, last NMOS pipe of described the 11 NMOS pipe group and last NMOS pipe of described the 12 NMOS pipe group is connected with the signal output part of described summing circuit module respectively, and the grid of three NMOS pipes of described the tenth NMOS pipe group is imported the corresponding sampled value of the summand input signal of the corresponding sampled value of described summand input signal, described complementation and the corresponding sampled value of addend input signal of described complementation respectively; The grid of three NMOS pipe of described the 11 NMOS pipe group is imported the corresponding sampled value of the addend input signal of the corresponding sampled value of described addend input signal, described complementation and the corresponding sampled value of summand input signal of described complementation respectively; The grid of two NMOS pipes of described the 12 NMOS pipe group is imported corresponding sampled value of described addend input signal and the corresponding sampled value of described summand input signal respectively, and the drain electrode of described the 2nd PMOS pipe inserts the power clock signal of described amplitude level counterlogic 2, and the source electrode of described the 2nd PMOS pipe is connected with the signal output part of described
Figure GSA00000075646500061
summing circuit module respectively with the drain electrode of described the tenth NMOS pipe; The grid of described the 2nd PMOS pipe is connected with the grid of described the tenth NMOS pipe and the feedback signal input end of described
Figure GSA00000075646500062
summing circuit module respectively, and the source electrode of described the tenth NMOS pipe connects power supply ground;
Described S 2The summing circuit module comprises the 13 NMOS pipe group, the 14 NMOS pipe group, the 15 NMOS pipe group, the 16 NMOS pipe group, the 17 NMOS pipe group, the 18 NMOS pipe group, the 11 NMOS pipe and the 3rd PMOS pipe; Described the 13 NMOS pipe group mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; Described the 14 NMOS pipe group mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes and drain electrode head and the tail serial connection; Described the 15 NMOS pipe group mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes mainly is made up of two NMOS pipes with drain electrode head and the tail serial connection, described the 16 NMOS pipe group, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; Described the 17 NMOS pipe group mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes mainly is made up of three NMOS pipes with drain electrode head and the tail serial connection, described the 18 NMOS pipe group, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection; The drain electrode of the drain electrode of the drain electrode of first NMOS pipe of described the 13 NMOS pipe group, first NMOS pipe of described the 14 NMOS pipe group and first NMOS pipe of described the 15 NMOS pipe group inserts the power clock signal of described amplitude level counterlogic 1 respectively, the source electrode of the source electrode of the source electrode of last NMOS pipe of described the 13 NMOS pipe group, last NMOS pipe of described the 14 NMOS pipe group and last NMOS pipe of described the 15 NMOS pipe group respectively with described S 2The signal output part of summing circuit module is connected; The grid of two NMOS pipe of described the 13 NMOS pipe group is imported the corresponding sampled value of the addend input signal of described complementation and the corresponding sampled value of summand input signal of described complementation respectively; The grid of three NMOS pipes of described the 14 NMOS pipe group is imported the sampled value of the corresponding sampled value of described addend input signal, described summand input signal correspondence and the corresponding sampled value of summand input signal of described complementation respectively; The grid of three NMOS pipes of described the 15 NMOS pipe group is imported the sampled value of the corresponding sampled value of described summand input signal, described addend input signal correspondence and the corresponding sampled value of addend input signal of described complementation respectively; The drain electrode of the drain electrode of the drain electrode of first NMOS pipe of described the 16 NMOS pipe group, first NMOS pipe of described the 17 NMOS pipe group and first NMOS pipe of described the 18 NMOS pipe group inserts the power clock signal of described amplitude level counterlogic 2 respectively, the source electrode of the source electrode of the source electrode of last NMOS pipe of described the 16 NMOS pipe group, last NMOS pipe of described the 17 NMOS pipe group and last NMOS pipe of described the 18 NMOS pipe group respectively with described S 2The signal output part of summing circuit module is connected; The grid of two NMOS pipes of described the 16 NMOS pipe group is imported corresponding sampled value of described addend input signal and the corresponding sampled value of described summand input signal respectively; The grid of three NMOS pipe of described the 17 NMOS pipe group is imported the corresponding sampled value of the addend input signal of the corresponding sampled value of described addend input signal, described complementation and the corresponding sampled value of summand input signal of described complementation respectively; The grid of three NMOS pipe of described the 18 NMOS pipe group is imported the corresponding sampled value of the summand input signal of the corresponding sampled value of described summand input signal, described complementation and the corresponding sampled value of addend input signal of described complementation respectively; The drain electrode of described the 3rd PMOS pipe inserts the power clock signal of described amplitude level counterlogic 2, the drain electrode of the source electrode of described the 3rd PMOS pipe and described the 11 NMOS pipe respectively with described S 2The signal output part of summing circuit module is connected, the grid of described the 3rd PMOS pipe respectively with the grid and the described S of described the 11 NMOS pipe 2The feedback signal input end of summing circuit module is connected, and the source electrode of described the 11 NMOS pipe connects power supply ground;
Described
Figure GSA00000075646500071
summing circuit module comprises the 19 NMOS pipe group, the 20 NMOS pipe group, the 21 NMOS pipe group, the 22 NMOS pipe group, the 23 NMOS pipe group, the 24 NMOS pipe group, the 12 NMOS pipe and the 4th PMOS pipe; Described the 19 NMOS pipe group mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; Described the 20 NMOS pipe group mainly is made up of the four NMOS pipe; And the source electrode of four NMOS pipe and drain electrode head and the tail serial connection; Described the 21 NMOS pipe group mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; Described the 22 NMOS pipe group mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes and drain electrode head and the tail serial connection; Described the 23 NMOS pipe group mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes mainly is made up of two NMOS pipes with drain electrode head and the tail serial connection, described the 24 NMOS pipe group, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; The drain electrode of the drain electrode of the drain electrode of first NMOS pipe of described the 19 NMOS pipe group, first NMOS pipe of described the 20 NMOS pipe group and first NMOS pipe of described the 21 NMOS pipe group inserts the power clock signal of described amplitude level counterlogic 2 respectively; The source electrode of the source electrode of the source electrode of last NMOS pipe of described the 19 NMOS pipe group, last NMOS pipe of described the 20 NMOS pipe group and last NMOS pipe of described the 21 NMOS pipe group is connected with the signal output part of described
Figure GSA00000075646500072
summing circuit module respectively, and the grid that two NMOS of described the 19 NMOS pipe group manage is imported the corresponding sampled value of addend input signal of corresponding sampled value of described summand input signal and described complementation respectively, and the grid of the four NMOS pipe of described the 20 NMOS pipe group is imported corresponding sampled value, the sampled value of described summand input signal correspondence and the corresponding sampled value of summand input signal of described complementation of addend input signal of the corresponding sampled value of described addend input signal, described complementation respectively; The grid of two NMOS pipes of described the 21 NMOS pipe group is imported the corresponding sampled value of summand input signal of corresponding sampled value of described addend input signal and described complementation respectively; The drain electrode of the drain electrode of the drain electrode of first NMOS pipe of described the 22 NMOS pipe group, first NMOS pipe of described the 23 NMOS pipe group and first NMOS pipe of described the 24 NMOS pipe group inserts the power clock signal of described amplitude level counterlogic 1 respectively, and the source electrode of the source electrode of last NMOS pipe of the source electrode that last NMOS of described the 22 NMOS pipe group manages, described the 23 NMOS pipe group and last NMOS pipe of described the 24 NMOS pipe group is connected with the signal output part of described
Figure GSA00000075646500081
summing circuit module respectively, and the grid of three NMOS pipes of described the 22 NMOS pipe group is imported the sampled value of the corresponding sampled value of described summand input signal, described addend input signal correspondence and the corresponding sampled value of addend input signal of described complementation respectively; The grid of three NMOS pipes of described the 23 NMOS pipe group is imported the sampled value of the corresponding sampled value of described addend input signal, described summand input signal correspondence and the corresponding sampled value of summand input signal of described complementation respectively; The grid of two NMOS pipe of described the 24 NMOS pipe group is imported the corresponding sampled value of the addend input signal of described complementation and the corresponding sampled value of summand input signal of described complementation respectively, and the drain electrode of described the 4th PMOS pipe inserts the power clock signal of described amplitude level counterlogic 2, and the source electrode of described the 4th PMOS pipe is connected with the signal output part of described
Figure GSA00000075646500082
summing circuit module respectively with the drain electrode of described the 12 NMOS pipe; The grid of described the 4th PMOS pipe is connected with the grid of described the 12 NMOS pipe and the feedback signal input end of described
Figure GSA00000075646500083
summing circuit module respectively, and the source electrode of described the 12 NMOS pipe connects power supply ground.
Described carry output circuit comprises carry output module and complementary carry output module; The signal output part of described carry output module is exported described carry output signals; The signal output part of described complementary carry output module is exported the carry output signals of described complementation; Described carry output module mainly is made up of the 25 NMOS pipe group, the 26 NMOS pipe group, the 27 NMOS pipe group, the 15 NMOS pipe and the 5th PMOS pipe; Described the 25 NMOS pipe group mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; Described the 26 NMOS pipe group mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; Described the 27 NMOS pipe group mainly is made up of the 13 NMOS pipe, a NMOS route of pipe line, the 2nd NMOS route of pipe line and the 3rd NMOS route of pipe line; A described NMOS route of pipe line and described the 2nd NMOS route of pipe line are formed by a NMOS pipe; Described the 3rd NMOS route of pipe line is made up of two NMOS pipes and the source electrode of two NMOS pipes and the head and the tail serial connection that drains; The source electrode of described the 13 NMOS pipe is connected with the drain electrode of first NMOS pipe of the drain electrode of the NMOS pipe of the drain electrode of the NMOS pipe of a described NMOS route of pipe line, described the 2nd NMOS route of pipe line and described the 3rd NMOS route of pipe line respectively; The drain electrode of the drain electrode of the drain electrode of first NMOS pipe of described the 25 NMOS pipe group, first NMOS pipe of described the 26 NMOS pipe group, the drain electrode of described the 13 NMOS pipe and described the 5th PMOS pipe all inserts the power clock signal of described amplitude level counterlogic 2; The drain electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of last NMOS pipe of described the 25 NMOS pipe group, last NMOS pipe of described the 26 NMOS pipe group, the NMOS pipe of a described NMOS route of pipe line, the NMOS pipe of described the 2nd NMOS route of pipe line, last NMOS pipe of described the 3rd NMOS route of pipe line, the source electrode of described the 5th PMOS pipe and described the 15 NMOS pipe all is connected with the signal output part of described carry output module; The grid of two NMOS pipes of described the 25 NMOS pipe group is imported corresponding sampled value of described addend input signal and the corresponding sampled value of described summand input signal respectively; The grid of two NMOS pipes of described the 26 NMOS pipe group is imported corresponding sampled value of described addend input signal and the corresponding sampled value of described summand input signal respectively, and the grid of described the 13 NMOS pipe is imported the corresponding sampled value of described low level carry input signal, and the grid of the NMOS pipe of a described NMOS route of pipe line is imported the corresponding sampled value of described addend input signal; The grid of the NMOS pipe of described the 2nd NMOS route of pipe line is imported the corresponding sampled value of described summand input signal; The grid of two NMOS pipes of described the 3rd NMOS route of pipe line is imported corresponding sampled value of described addend input signal and the corresponding sampled value of described summand input signal respectively, and the grid of described the 5th PMOS pipe is connected with the grid of described the 15 NMOS pipe and the signal output part of described complementary carry output module respectively, and the source electrode of described the 15 NMOS pipe connects power supply ground;
Described complementary carry output module mainly is made up of the 28 NMOS pipe group, the 29 NMOS pipe group, the 30 NMOS pipe group, the 16 NMOS pipe and the 6th PMOS pipe; Described the 28 NMOS pipe group mainly is made up of the 14 NMOS pipe, the 4th NMOS route of pipe line, the 5th NMOS route of pipe line and the 6th NMOS route of pipe line; Described the 4th NMOS route of pipe line is made up of two NMOS pipes and the source electrode of two NMOS pipes and the head and the tail serial connection that drains; Described the 5th NMOS route of pipe line and described the 6th NMOS route of pipe line are formed by a NMOS pipe; Described the 29 NMOS pipe group mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; Described the 30 NMOS pipe group mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; The source electrode of described the 14 NMOS pipe is connected with the drain electrode of the NMOS pipe of the drain electrode of the NMOS pipe of the drain electrode of first NMOS pipe of described the 4th NMOS route of pipe line, described the 5th NMOS route of pipe line and described the 6th NMOS route of pipe line respectively; The drain electrode of the drain electrode of first NMOS pipe of the drain electrode of described the 14 NMOS pipe, described the 29 NMOS pipe group, first NMOS pipe of described the 30 NMOS pipe group and the drain electrode of described the 6th PMOS pipe all insert the power clock signal of described amplitude level counterlogic 2; The drain electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of last NMOS pipe of described the 4th NMOS route of pipe line, the NMOS pipe of described the 5th NMOS route of pipe line, the NMOS pipe of described the 6th NMOS route of pipe line, last NMOS pipe of described the 29 NMOS pipe group, last NMOS pipe of described the 30 NMOS pipe group, the source electrode of described the 6th PMOS pipe and described the 16 NMOS pipe all is connected with the signal output part of described complementary carry output module; The grid of two NMOS pipe of described the 4th NMOS route of pipe line is imported the corresponding sampled value of the addend input signal of described complementation and the corresponding sampled value of summand input signal of described complementation respectively; The grid of the NMOS pipe of described the 5th NMOS route of pipe line is imported the corresponding sampled value of summand input signal of described complementation; The grid of the NMOS pipe of described the 6th NMOS route of pipe line is imported the corresponding sampled value of addend input signal of described complementation; The grid of two NMOS pipe of described the 29 NMOS pipe group is imported the corresponding sampled value of the addend input signal of described complementation and the corresponding sampled value of summand input signal of described complementation respectively; The grid of two NMOS pipe of described the 30 NMOS pipe group is imported the corresponding sampled value of the addend input signal of described complementation and the corresponding sampled value of summand input signal of described complementation respectively; The grid of described the 14 NMOS pipe is imported the corresponding sampled value of low level carry input signal of described complementation; The grid of described the 6th PMOS pipe is connected with the grid of described the 16 NMOS pipe and the signal output part of described carry output module respectively, and the source electrode of described the 16 NMOS pipe connects power supply ground.
Described input signal sample circuit comprises original input signal sample circuit module and complementary input signal sample circuit module; Described original input signal sample circuit module mainly is made up of one group of NMOS pipe; The source electrode of each NMOS pipe in the described original input signal sample circuit module is imported described addend input signal, described summand input signal and described low level carry input signal respectively; The drain electrode of each NMOS pipe in the described original input signal sample circuit module is respectively as former sampling node; Export one group of sampled value and one group of corresponding sampled value of described low level carry input signal of one group of corresponding sampled value of described addend input signal, described summand input signal correspondence, the grid of each NMOS pipe in the described original input signal sample circuit module inserts the clock clock signal of described amplitude level counterlogic 2; Described complementary input signal sample circuit module mainly is made up of another group NMOS pipe; The source electrode of each NMOS pipe in the described complementary input signal sample circuit module is imported the summand input signal of the addend input signal of described complementation, described complementation and the low level carry input signal of described complementation respectively; The drain electrode of each NMOS pipe in the described complementary input signal sample circuit module is respectively as complementary sampling node; Export one group of corresponding sampled value of the summand input signal of one group of corresponding sampled value of the addend input signal of described complementation, described complementation and one group of corresponding sampled value of low level carry input signal of described complementation, the grid of each NMOS pipe in the described complementary input signal sample circuit module inserts the clock clock signal of described amplitude level counterlogic 2.
The power clock signal of described amplitude level counterlogic 2 is identical with the phase place of the power clock signal of described amplitude level counterlogic 1, and with 180 ° of the phasic differences mutually of the clock clock signal of described amplitude level counterlogic 2.
A kind of tri-valued, thermal-insulating and low-power totalizer that constitutes by above-mentioned tri-valued, thermal-insulating and low-power adder unit; Comprise a plurality of tri-valued, thermal-insulating and low-power adder units; Described tri-valued, thermal-insulating and low-power adder unit comprises input signal sample circuit, summation output circuit and carry output circuit; The signal input part of described input signal sample circuit is imported the summand input signal of described addend input signal, described summand input signal, described low level carry input signal, the addend input signal of described complementation, described complementation and the low level carry input signal of described complementation; Described input signal sample circuit inserts the clock clock signal of amplitude level counterlogic 2; The clock clock signal of described amplitude level counterlogic 2 is controlled described input signal sample circuit the summand input signal of described addend input signal, described summand input signal, described low level carry input signal, the addend input signal of described complementation, described complementation and the low level carry input signal of described complementation is sampled, and the signal output part of described input signal sample circuit is exported the summand input signal of described addend input signal, described summand input signal, described low level carry input signal, the addend input signal of described complementation, described complementation and each self-corresponding one group of sampled value of low level carry input signal of described complementation;
Described summation output circuit mainly is made up of four summing circuit modules; The signal input part of four described summing circuit modules is all imported the corresponding sampled value of the addend input signal of the corresponding sampled value of described addend input signal, the sampled value that described summand input signal is corresponding, described complementation and the corresponding sampled value of summand input signal of described complementation; Four described summing circuit modules all insert the power clock signal of amplitude level counterlogic 2 and the power clock signal of amplitude level counterlogic 1 respectively, and four described summing circuit modules are designated as S respectively 0, S 2With
Figure GSA00000075646500102
Described S 0The signal output part of summing circuit module and described
Figure GSA00000075646500111
The feedback signal input end of summing circuit module is connected, and is described
Figure GSA00000075646500112
The signal output part of summing circuit module and described S 0The feedback signal input end of summing circuit module is connected, described S 2The signal output part of summing circuit module and described The feedback signal input end of summing circuit module is connected, and is described The signal output part of summing circuit module and described S 2The feedback signal input end of summing circuit module is connected, described S 0The signal output part of summing circuit module and described summation output circuit are used to export between the signal output part of summation output signal and are provided with NMOS pipe, the source electrode and the described S of described NMOS pipe 0The signal output part of summing circuit module is connected; The drain electrode of described NMOS pipe and described summation output circuit are used to export the signal output part that summation exports signal and are connected; The grid of described NMOS pipe inserts the corresponding sampled value of low level carry input signal of described complementation, and is described The signal output part of summing circuit module and described summation output circuit are used to export between the signal output part of complementary summation output signal and are provided with the 2nd NMOS pipe, the source electrode of described the 2nd NMOS pipe and described
Figure GSA00000075646500116
The signal output part of summing circuit module is connected; The drain electrode of described the 2nd NMOS pipe and described summation output circuit are used to export the signal output part that complementary summation exports signal and are connected; The grid of described the 2nd NMOS pipe inserts the corresponding sampled value of low level carry input signal of described complementation, described S 2The signal output part of summing circuit module and described summation output circuit are used to export between the signal output part of summation output signal and are provided with the 3rd NMOS pipe, the source electrode and the described S of described the 3rd NMOS pipe 2The signal output part of summing circuit module is connected; The drain electrode of described the 3rd NMOS pipe and described summation output circuit are used to export the signal output part that summation exports signal and are connected; The grid of described the 3rd NMOS pipe inserts the corresponding sampled value of described low level carry input signal, and is described
Figure GSA00000075646500117
The signal output part of summing circuit module and described summation output circuit are used to export between the signal output part of complementary summation output signal and are provided with the 4th NMOS pipe, the source electrode of described the 4th NMOS pipe and described
Figure GSA00000075646500118
The signal output part of summing circuit module is connected; The signal output part that the drain electrode of described the 4th NMOS pipe and described summation output circuit are used to export complementary summation output signal is connected, and the grid of described the 4th NMOS pipe inserts the sampled value of described low level carry input signal correspondence;
The signal input part of described carry output circuit is imported the corresponding sampled value of the summand input signal of the corresponding sampled value of the addend input signal of the corresponding sampled value of described addend input signal, the sampled value that described summand input signal is corresponding, the sampled value that described low level carry input signal is corresponding, described complementation, described complementation and the corresponding sampled value of low level carry input signal of described complementation; Described carry output circuit inserts the power clock signal of amplitude level counterlogic 2, the signal output part output carry output signal and the complementary carry output signals of described carry output circuit;
The signal input part that the signal output part that each described tri-valued, thermal-insulating and low-power adder unit is used for output carry output signal and the described tri-valued, thermal-insulating and low-power adder unit of next bit are used to import low level carry input signal is connected; The signal input part that the signal output part that each described tri-valued, thermal-insulating and low-power adder unit is used to export complementary carry output signals and the described tri-valued, thermal-insulating and low-power adder unit of next bit are used to import the low level carry input signal of complementation is connected; The described tri-valued, thermal-insulating and low-power adder unit of lowest order is used to import the signal input part input 0 of low level carry input signal, and the signal input part that the described tri-valued, thermal-insulating and low-power adder unit of lowest order is used to import complementary low level carry input signal inserts the clock clock signal of amplitude level counterlogic 2.
Each described tri-valued, thermal-insulating and low-power adder unit is used to import the signal input part of addend input signal, the signal input part that is used to import the summand input signal, the signal input part that is used to import the signal input part of complementary addend input signal and is used to import complementary summand input signal and is respectively arranged with several DTCTGAL impact dampers; And the number of the described DTCTGAL impact damper that each signal input part of any described tri-valued, thermal-insulating and low-power adder unit is provided with is identical, and the number of a described DTCTGAL impact damper of each signal input part setting of two adjacent described tri-valued, thermal-insulating and low-power adder units is inequality; The signal output part that each described tri-valued, thermal-insulating and low-power adder unit is used to export summation output signal is respectively arranged with several the 2nd DTCTGAL impact dampers with the signal output part that is used to export complementary summation output signal; And the number of described the 2nd DTCTGAL impact damper that each signal output part of any described tri-valued, thermal-insulating and low-power adder unit is provided with is identical, and the number of described the 2nd DTCTGAL impact damper of each signal output part setting of two adjacent described tri-valued, thermal-insulating and low-power adder units is inequality.
The time delay of the time delay of a described DTCTGAL impact damper, described the 2nd DTCTGAL impact damper is identical with the time delay of described tri-valued, thermal-insulating and low-power adder unit, is the clock period half.
A described DTCTGAL impact damper is input signal and the identical impact damper of output signal with described the 2nd DTCTGAL impact damper, and the output of a described DTCTGAL impact damper and described the 2nd DTCTGAL impact damper all postpones the clock period half than input.
Compared with prior art; The invention has the advantages that at first and each input signal is sampled with each NMOS pipe in the clock clock signal control input signals sample circuit; The NMOS pipe of the adder logic relation that realizes as requested of each sampled value of obtaining of sampling through the bootstrapping operation makes up corresponding four summing circuit modules and intersects the carry output circuit of storage type structure, power clock Φ then 1, Φ accomplishes assignment and energy recovery to output load through four summing circuit modules and carry output circuit, can realize correct logic functions; Compare with the three value full adders of being realized by gate circuit, the circuit delay and the area of adder unit of the present invention is littler, power consumption is lower; Compare with DPL three value totalizers, totalizer of the present invention can be saved energy consumption in 0.9 μ s time about about 90%, has tangible low-power consumption characteristic.In summation the 5th NMOS pipe, the 6th NMOS pipe, the 7th NMOS pipe and the 8th NMOS pipe are set in the output circuit, being arranged so that of this four NMOS pipe
Figure GSA00000075646500121
The summing circuit module with The summing circuit module is not used or S 2The summing circuit module with
Figure GSA00000075646500123
When the summing circuit module was not used, the disconnection power clock was connected with obsolete two summing circuit modules, with the power consumption of further reduction summation output circuit.
Description of drawings
Fig. 1 is the input signal sample circuit figure of tri-valued, thermal-insulating and low-power adder unit of the present invention;
Fig. 2 a is the carry output circuit figure of tri-valued, thermal-insulating and low-power adder unit of the present invention;
Fig. 2 b is the symbol of the carry output circuit shown in Fig. 2 a;
Fig. 2 c is the synoptic diagram that concerns of clock clock and power clock Φ;
Fig. 3 a is low level carry input signal C In=0
Figure GSA00000075646500132
The S of time output summation output signal 0The summing circuit module diagram;
Fig. 3 b is the symbol of the circuit module shown in Fig. 3 a;
Fig. 4 a is low level carry input signal C In=0
Figure GSA00000075646500133
The complementary summation output of time output signal
Figure GSA00000075646500134
The summing circuit module diagram;
Fig. 4 b is the symbol of the circuit module shown in Fig. 4 a;
Fig. 5 a is low level carry input signal C In=2
Figure GSA00000075646500135
The S of time output summation output signal 2The summing circuit module diagram;
Fig. 5 b is the symbol of the circuit module shown in Fig. 5 a;
Fig. 6 a is low level carry input signal C In=2
Figure GSA00000075646500136
The complementary summation output of time output signal
Figure GSA00000075646500137
The summing circuit module diagram;
Fig. 6 b is the symbol of the circuit module shown in Fig. 6 a;
Fig. 7 a is the summation output circuit of tri-valued, thermal-insulating and low-power adder unit of the present invention;
Fig. 7 b is the symbol of the summation output circuit shown in Fig. 7 a;
Fig. 7 c is the clock clock
Figure GSA00000075646500138
With power clock Φ 1, Φ concern synoptic diagram;
Fig. 8 a is the circuit diagram of tri-valued, thermal-insulating and low-power adder unit of the present invention;
Fig. 8 b is the symbol of the adder unit shown in Fig. 8 a;
Fig. 9 is the circuit diagram of four tri-valued, thermal-insulating and low-power totalizers of the present invention;
Figure 10 is for to carry out the analog waveform figure that computer simulation obtains to four tri-valued, thermal-insulating and low-power totalizers of the present invention;
Figure 11 is that the transient state energy consumption of four tri-valued, thermal-insulating and low-power totalizers of the present invention and DPL three value totalizers compares synoptic diagram.
Embodiment
Embodiment describes in further detail the present invention below in conjunction with accompanying drawing.
Embodiment one:
Table 1 has provided the truth table of three value adder units (being full adder) circuit, and wherein A and B represent addend input signal and summand input signal, C respectively InExpression is from the low level carry input signal of low level, S and C OutSignal and carry output signals are exported in the expression summation respectively.
The truth table of one three value of table 1 adder unit
Figure GSA00000075646500141
The present invention combines on the basis of analytical table 1 disclosed among the Chinese Journal of Semiconductors " Design of a DTCTGAL circuit and its application " (author: Wang Pengjun, Li Kunpeng, Mei Fengna) [semiconductor journal; " DTCTGAL circuit design and application thereof "; Wang Pengjun, Li Kunpeng, Mei Fengna], design a tri-valued, thermal-insulating and low-power adder unit: at first use the clock clock signal
Figure GSA00000075646500142
Control NMOS pipe is sampled to each input signal (comprising addend input signal, summand input signal, low level carry input signal, complementary addend input signal, complementary summand input signal and complementary low level carry input signal); The adder logic relation that realizes as requested of each sampled value of obtaining of sampling makes up corresponding four summing circuit modules, power clock signal Phi through the NMOS pipe of bootstrapping operation then 1, Φ is through four summing circuit modules, eight NMOS pipe (promptly NMOS pipe is to the 8th NMOS pipe) that is connected with four summing circuit modules and the carry output circuit completion that intersects storage type structure assignment and the energy recovery to output load, wherein power clock signal Phi 1, Φ phase place identical, but with the clock clock signal
Figure GSA00000075646500143
Differ 180 °, Φ 1Amplitude level counterlogic 1, Φ,
Figure GSA00000075646500144
The equal counterlogic 2 of amplitude level.
A kind of tri-valued, thermal-insulating and low-power adder unit that the present invention proposes; Shown in Fig. 1 to Fig. 8 b; Specifically comprise input signal sample circuit 1, summation output circuit 2 and carry output circuit 3, Fig. 8 a is the integrated circuit figure of adder unit, and Fig. 8 b is the symbol of the circuit diagram of Fig. 8 a.
In this specific embodiment; Input signal sample circuit 1 is specifically as shown in Figure 1; It comprises original input signal sample circuit module 11 and complementary input signal sample circuit module 12; Original input signal sample circuit module 11 mainly is made up of one group of NMOS pipe, and the source electrode of each NMOS pipe in the original input signal sample circuit module is imported addend input signal A, summand input signal B and low level carry input signal C respectively In, the drain electrode of each NMOS pipe in the original input signal sample circuit module 11 is respectively as one group of corresponding sampled value ax (ax of former sampling node output addend input signal A 0, ax 1..., ax 11, ax 12), one group of sampled value bx (bx that summand input signal B is corresponding 0, bx 1..., bx 11, bx 12) and low level carry input signal C InOne group of corresponding sampled value cx (cx 0, cx 1), the grid of each NMOS pipe in the original input signal sample circuit module 11 inserts the clock clock signal of amplitude level counterlogic 2 Complementary input signal sample circuit module 12 mainly is made up of another group NMOS pipe, and the source electrode of each NMOS pipe in the complementary input signal sample circuit module 12 is imported complementary addend input signal respectively
Figure GSA00000075646500152
Complementary summand input signal
Figure GSA00000075646500153
Low level carry input signal with complementation
Figure GSA00000075646500154
The drain electrode of each NMOS pipe in the complementary input signal sample circuit module 12 is respectively as the complementary addend input signal of complementary sampling node output
Figure GSA00000075646500155
One group of corresponding sampled value ay (ay 0, ay 1..., ay 11, ay 12), complementary summand input signal
Figure GSA00000075646500156
One group of corresponding sampled value by (by 0, by 1..., by 11, by 12) and complementary low level carry input signal
Figure GSA00000075646500157
One group of corresponding sampled value cy (cy 0, cy 1), the grid of each NMOS pipe in the complementary input signal sample circuit module 12 inserts the clock clock signal of amplitude level counterlogic 2
Figure GSA00000075646500158
In this clock clock signal by amplitude level counterlogic 2
Figure GSA00000075646500159
Each NMOS pipe in the control input signals sample circuit module 11 is to addend input signal A, summand input signal B and the low level carry input signal C of input InSample, obtain each self-corresponding one group of sampled value; Clock clock signal by amplitude level counterlogic 2
Figure GSA000000756465001510
Each NMOS pipe in the complementary sample circuit module 12 of control signal is to the addend input signal of complementation Complementary summand input signal
Figure GSA000000756465001512
Low level carry input signal with complementation
Figure GSA000000756465001513
Sample, obtain each self-corresponding one group of sampled value.
In this specific embodiment; Summation output circuit 2 is shown in Fig. 7 a and Fig. 7 b; It mainly is made up of four summing circuit modules 21,22,23,24, and the signal input part of four summing circuit modules 21,22,23,24 is all imported the corresponding sampled value ax of addend input signal A, the sampled value bx that summand input signal B is corresponding, complementary addend input signal Corresponding sampled value ay and complementary summand input signal
Figure GSA000000756465001515
Corresponding sampled value by, four summing circuit modules 21,22,23,24 all insert the power clock signal Phi of amplitude level counterlogic 2 and the power clock signal Phi of amplitude level counterlogic 1 respectively 1, the power clock signal Phi of amplitude level counterlogic 2 and the power clock signal Phi of amplitude level counterlogic 1 1And the clock clock signal of amplitude level counterlogic 2
Figure GSA000000756465001516
Relation shown in Fig. 7 c.Four summing circuit modules 21,22,23,24 are designated as S respectively 0,
Figure GSA000000756465001517
S 2With
Figure GSA000000756465001518
S 0The signal output part of summing circuit module 21 with
Figure GSA000000756465001519
The feedback signal input end of summing circuit module 22 is connected,
Figure GSA000000756465001520
The signal output part 22 and the S of summing circuit module 0The feedback signal input end of summing circuit module 21 is connected,
Figure GSA00000075646500161
The feedback signal input end of summing circuit module 22 is actually S 0The signal output part of summing circuit module 21, S 0The feedback signal input end of summing circuit module 21 is actually The signal output part of summing circuit module 22, here S 021 draws of summing circuit module
Figure GSA00000075646500163
Summing circuit module 22 constitutes cross-coupled structure, S 2The signal output part of summing circuit module 23 with
Figure GSA00000075646500164
The feedback signal input end of summing circuit module 24 is connected, The signal output part of summing circuit module 24 and S 2The feedback signal input end of summing circuit module 23 is connected, at this The feedback signal input end of summing circuit module 24 is actually S 2The signal output part of summing circuit module 23, S 2The feedback signal input end of summing circuit module 23 is actually
Figure GSA00000075646500167
The signal output part of summing circuit module 24, here S 223 draws of summing circuit module
Figure GSA00000075646500168
Summing circuit module 24 constitutes cross-coupled structure, S 0The signal output part of summing circuit module 21 and summation output circuit 2 are used to export between the signal output part of summation output signal and are provided with NMOS pipe N1, source electrode and the S of NMOS pipe N1 0The signal output part of summing circuit module 21 is connected, and the signal output part that the drain electrode of NMOS pipe N1 and summation output circuit 2 are used to export summation output signal is connected, and the grid of NMOS pipe N1 inserts the low level carry input signal of complementation Corresponding sampled value cy1, The signal output part of summing circuit module 22 and summation output circuit 2 are used to export between the signal output part of complementary summation output signal and are provided with the 2nd NMOS pipe N2, the source electrode of the 2nd NMOS pipe N2 with
Figure GSA000000756465001611
The signal output part of summing circuit module 22 is connected, and the signal output part that the drain electrode of the 2nd NMOS pipe N2 and summation output circuit 2 are used to export complementary summation output signal is connected, and the grid of the 2nd NMOS pipe N2 inserts the low level carry input signal of complementation Corresponding sampled value cy1, S 2The signal output part of summing circuit module 23 and summation output circuit 2 are used to export between the signal output part of summation output signal and are provided with the 3rd NMOS pipe N3, source electrode and the S of the 3rd NMOS pipe N3 2The signal output part of summing circuit module 23 is connected, and the signal output part that the drain electrode of the 3rd NMOS pipe N3 and summation output circuit 2 are used to export summation output signal is connected, and the grid of the 3rd NMOS pipe N3 inserts low level carry input signal correspondence C InCorresponding sampled value cx1, The signal output part of summing circuit module 24 and summation output circuit 2 are used to export between the signal output part of complementary summation output signal and are provided with the 4th NMOS pipe N4, the source electrode of the 4th NMOS pipe N4 with The signal output part of summing circuit module 24 is connected, and the signal output part that the drain electrode of the 4th NMOS pipe N4 and summation output circuit 2 are used to export complementary summation output signal is connected the grid access low level carry input signal C of the 4th NMOS pipe N4 InCorresponding sampled value cx1.As low level carry input signal C In=0
Figure GSA00000075646500171
Be cx among Fig. 7 a 1=0 (cy 1=2) time, S 0 Summing circuit module 21 with
Figure GSA00000075646500172
Summing circuit module 22 is managed N2 by cy through NMOS pipe N1 and the 2nd NMOS 1Gating outputs to the signal output part of summation output circuit 2, i.e. S=S 0,
Figure GSA00000075646500173
In like manner, work as C In=2
Figure GSA00000075646500174
The time, i.e. cx among Fig. 7 a 1=2 (cy 1=0) time, S 2 Summing circuit module 23 with
Figure GSA00000075646500175
Summing circuit module 24 is managed N4 by cx through the 3rd NMOS pipe N3 and the 4th NMOS 1Gating outputs to the signal output part of summation output circuit 2, i.e. S=S 2,
Figure GSA00000075646500176
At this, summation is provided with the 5th NMOS pipe N5, the 6th NMOS pipe N6, the 7th NMOS pipe N7 and the 8th NMOS pipe N8 in the output circuit 2, the source electrode of the 5th NMOS pipe N5 respectively with S 0 Summing circuit module 21 be used to insert amplitude level counterlogic 2 the power clock signal input end with
Figure GSA00000075646500177
The input end that summing circuit module 22 is used to insert the power clock signal of amplitude level counterlogic 2 is connected, the source electrode of the 6th NMOS pipe N6 respectively with S 2 Summing circuit module 23 be used to insert amplitude level counterlogic 2 the power clock signal input end with
Figure GSA00000075646500178
The input end that summing circuit module 24 is used to insert the power clock signal of amplitude level counterlogic 2 is connected; The drain electrode of the drain electrode of the 5th NMOS pipe N5 and the 6th NMOS pipe N6 all inserts the power clock signal Phi of amplitude level counterlogic 2, the source electrode of the 7th NMOS pipe N7 respectively with
Figure GSA00000075646500179
Summing circuit module 22 is used to insert the input end and the S of the power clock signal of amplitude level counterlogic 1 0The input end that summing circuit module 21 is used to insert the power clock signal of amplitude level counterlogic 1 is connected, the source electrode of the 8th NMOS pipe N8 respectively with
Figure GSA000000756465001710
Summing circuit module 24 is used to insert the input end and the S of the power clock signal of amplitude level counterlogic 1 2The input end that summing circuit module 23 is used to insert the power clock signal of amplitude level counterlogic 1 is connected, and the drain electrode of the drain electrode of the 7th NMOS pipe N7 and the 8th NMOS pipe N8 all inserts the power clock signal Phi of amplitude level counterlogic 1 1The grid of the grid of the 5th NMOS pipe N5 and the 7th NMOS pipe N7 interconnects with the grid of NMOS pipe N1 and the grid of the 2nd NMOS pipe N2 respectively; Promptly the grid of the grid of the grid of the grid of the 5th NMOS pipe N5, the 7th NMOS pipe N7, NMOS pipe N1 and the 2nd NMOS pipe N2 interconnects; The grid of the grid N6 of the 6th NMOS pipe and the 8th NMOS pipe N8 interconnects with the grid of the 3rd NMOS pipe N3 and the grid of the 4th NMOS pipe N4 respectively, and promptly the grid of the grid of the grid of the grid N6 of the 6th NMOS pipe, the 8th NMOS pipe N8, the 3rd NMOS pipe N3 and the 4th NMOS pipe N4 interconnects.
At this, through power clock signal Phi and S at amplitude level counterlogic 2 0 Summing circuit module 21 and S 2Add the 5th NMOS pipe N5 and the 6th NMOS pipe N6 between the summing circuit module 23, and through the power clock signal Phi at amplitude level counterlogic 1 1With
Figure GSA000000756465001711
22 draws of summing circuit module Add the 7th NMOS pipe N7 and the 8th NMOS pipe N8 between the summing circuit module 24, work as S like this 021 draws of summing circuit module Summing circuit module 22 is not during by gating, by the low level carry input signal C of complementation InSampled value cy 1Control the 5th NMOS pipe N5 and cut off S 0Getting in touch of the power clock signal Phi of summing circuit module 21 and amplitude level counterlogic 2, and control the 7th NMOS pipe N7 cuts off
Figure GSA00000075646500182
The power clock signal Phi of summing circuit module 22 and amplitude level counterlogic 1 1Contact, by low level carry input signal
Figure GSA00000075646500183
Sampled value cx 1Control the 6th NMOS pipe N6 and make S 2 Summing circuit module 23 interrelates with the power clock signal Phi of amplitude level counterlogic 2, and control the 8th NMOS pipe N8 makes
Figure GSA00000075646500184
The power clock signal Phi of summing circuit module 24 and amplitude level counterlogic 1 1Interrelate; Work as S 223 draws of summing circuit module
Figure GSA00000075646500185
Summing circuit module 24 is not during by gating, by low level carry input signal C InSampled value cx 1Control the 6th NMOS pipe N6 and cut off S 2Getting in touch of the power clock signal Phi of summing circuit module 23 and amplitude level counterlogic 2, and control the 8th NMOS pipe N8 cuts off
Figure GSA00000075646500186
The power clock signal Phi of summing circuit module 24 and amplitude level counterlogic 1 1Contact, by the low level carry input signal of complementation
Figure GSA00000075646500187
Sampled value cy 1Control the 5th NMOS pipe N5 and make S 0 Summing circuit module 21 interrelates with the power clock signal Phi of amplitude level counterlogic 2, and control the 7th NMOS pipe N7 makes
Figure GSA00000075646500188
The power clock signal Phi of summing circuit module 22 and amplitude level counterlogic 1 1Interrelate, can further reduce the power consumption of whole summation output circuit 2 in this way.
In this specific embodiment, S 0The summing circuit module is shown in Fig. 3 a; Its symbol is shown in Fig. 3 b; It comprises a NMOS pipe group M1, the 2nd NMOS pipe group M2, the 3rd NMOS pipe group M3, the 4th NMOS pipe group M4, the 5th NMOS pipe group M5, the 6th NMOS pipe group M6, the 9th NMOS pipe N9 and PMOS pipe P1; The one NMOS pipe group M1 mainly is made up of two NMOS pipes, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection, and the 2nd NMOS pipe group M2 mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes and drain electrode head and the tail serial connection; The 3rd NMOS pipe group M3 mainly is made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, and the 4th NMOS pipe group M4 mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; The 5th NMOS pipe group M5 mainly is made up of the four NMOS pipe, and the source electrode of four NMOS pipe and drain electrode head and the tail serial connection, and the 6th NMOS pipe group M6 mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection, the drain electrode of the drain electrode of the drain electrode of first NMOS pipe of a NMOS pipe group M1, first NMOS pipe of the 2nd NMOS pipe group M2 and first NMOS pipe of the 3rd NMOS pipe group M3 inserts the power clock signal Phi of amplitude level counterlogic 1 respectively 1, the source electrode of the source electrode of the source electrode of last NMOS pipe of a NMOS pipe group M1, last NMOS pipe of the 2nd NMOS pipe group M2 and last NMOS pipe of the 3rd NMOS pipe group M3 respectively with S 0The signal output part of summing circuit module 21 is connected; The grid of two NMOS pipes of the one NMOS pipe group M1 is imported corresponding sampled value of addend input signal and the corresponding sampled value of summand input signal respectively; The grid of three NMOS pipe of the 2nd NMOS pipe group M2 is imported corresponding sampled value of the corresponding sampled value of addend input signal, complementary addend input signal and the complementary corresponding sampled value of summand input signal respectively; The grid of three NMOS pipe of the 3rd NMOS pipe group M3 is imported corresponding sampled value of the corresponding sampled value of summand input signal, complementary summand input signal and the complementary corresponding sampled value of addend input signal respectively; The drain electrode of the drain electrode of the drain electrode of first NMOS pipe of the 4th NMOS pipe group M4, first NMOS pipe of the 5th NMOS pipe group M5 and first NMOS pipe of the 6th NMOS pipe group M6 inserts the power clock signal Phi of amplitude level counterlogic 2 respectively, the source electrode of the source electrode of the source electrode of last NMOS pipe of the 4th NMOS pipe group M4, last NMOS pipe of the 5th NMOS pipe group M5 and last NMOS pipe of the 6th NMOS pipe group M6 respectively with S 0The signal output part of summing circuit module 21 is connected; The grid of two NMOS pipes of the 4th NMOS pipe group M4 is imported the corresponding sampled value of the addend input signal sampled value corresponding with complementary summand input signal respectively; The grid of the four NMOS pipe of the 5th NMOS pipe group M5 is imported corresponding sampled value, the sampled value of summand input signal correspondence and the complementary corresponding sampled value of summand input signal of addend input signal of the corresponding sampled value of addend input signal, complementation respectively; The grid of two NMOS pipes of the 6th NMOS pipe group M6 is imported corresponding sampled value of complementary addend input signal and the corresponding sampled value of summand input signal respectively; The drain electrode of the one PMOS pipe P1 inserts the power clock signal Phi of amplitude level counterlogic 2, the drain electrode of the source electrode of PMOS pipe P1 and the 9th NMOS pipe N9 respectively with S 0The signal output part of summing circuit module 21 is connected, and the grid of PMOS pipe P1 is managed grid and the S of N9 respectively with the 9th NMOS 0The feedback signal input end of summing circuit module 21 promptly
Figure GSA00000075646500191
The output terminal of summing circuit module 22 is connected, and the source electrode of the 9th NMOS pipe N9 connects power supply ground.
In this specific embodiment,
Figure GSA00000075646500192
The summing circuit module is shown in Fig. 4 a; Its symbol is shown in Fig. 4 b; It comprises the 7th NMOS pipe group M7, the 8th NMOS pipe group M8, the 9th NMOS pipe group M9, the tenth NMOS pipe group M10, the 11 NMOS pipe group M11, the 12 NMOS pipe group M12, the tenth NMOS pipe N10 and the 2nd PMOS pipe P2; The 7th NMOS pipe group M7 mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes mainly is made up of three NMOS pipes with drain electrode head and the tail serial connection, the 8th NMOS pipe group M8, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection; The 9th NMOS pipe group M9 mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes mainly is made up of three NMOS pipes with drain electrode head and the tail serial connection, the tenth NMOS pipe group M10, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection; The 11 NMOS pipe group M11 mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes mainly is made up of two NMOS pipes with drain electrode head and the tail serial connection, the 12 NMOS pipe group M12, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; The drain electrode of the drain electrode of the drain electrode of first NMOS pipe of the 7th NMOS pipe group M7, first NMOS pipe of the 8th NMOS pipe group and first NMOS pipe of the 9th NMOS pipe group inserts the power clock signal Phi of amplitude level counterlogic 2 respectively, the source electrode of the source electrode of the source electrode of last NMOS pipe of the 7th NMOS pipe group M7, last NMOS pipe of the 8th NMOS pipe group M8 and last NMOS pipe of the 9th NMOS pipe group M9 respectively with The signal output part of summing circuit module 22 is connected; The grid of three NMOS pipes of the 7th NMOS pipe group M7 is imported the sampled value of the corresponding sampled value of summand input signal, addend input signal correspondence and the complementary corresponding sampled value of addend input signal respectively; The grid of three NMOS pipes of the 8th NMOS pipe group M8 is imported the sampled value of the corresponding sampled value of addend input signal, summand input signal correspondence and the complementary corresponding sampled value of summand input signal respectively; The grid of two NMOS pipes of the 9th NMOS pipe group M9 is imported the corresponding sampled value of the complementary addend input signal sampled value corresponding with complementary summand input signal respectively, and the drain electrode of the drain electrode of the drain electrode of first NMOS pipe of the tenth NMOS pipe group M10, first NMOS pipe of the 11 NMOS pipe group M11 and first NMOS pipe of the 12 NMOS pipe group M12 inserts the power clock signal Phi of amplitude level counterlogic 1 respectively 1, the source electrode of the source electrode of the source electrode of last NMOS pipe of the tenth NMOS pipe group M10, last NMOS pipe of the 11 NMOS pipe group M11 and last NMOS pipe of the 12 NMOS pipe group M12 respectively with
Figure GSA00000075646500202
The signal output part of summing circuit module 22 is connected; The grid of three NMOS pipe of the tenth NMOS pipe group M10 is imported corresponding sampled value of the corresponding sampled value of summand input signal, complementary summand input signal and the complementary corresponding sampled value of addend input signal respectively; The grid of three NMOS pipe of the 11 NMOS pipe group M11 is imported corresponding sampled value of the corresponding sampled value of addend input signal, complementary addend input signal and the complementary corresponding sampled value of summand input signal respectively; The grid of two NMOS pipes of the 12 NMOS pipe group M12 is imported corresponding sampled value of addend input signal and the corresponding sampled value of summand input signal respectively; The drain electrode of the 2nd PMOS pipe P2 inserts the power clock signal Phi of amplitude level counterlogic 2, the drain electrode of the source electrode of the 2nd PMOS pipe P2 and the tenth NMOS pipe N10 respectively with
Figure GSA00000075646500203
The signal output part of summing circuit module 22 is connected, the grid of the 2nd PMOS pipe P2 respectively with the grid of the tenth NMOS pipe N10 with
Figure GSA00000075646500204
The feedback signal input end of summing circuit module 22 is S 0The output terminal of summing circuit module 21 is connected, and the source electrode of the tenth NMOS pipe N10 connects power supply ground.
In this specific embodiment, S 2The summing circuit module is shown in Fig. 5 a; Its symbol is shown in Fig. 5 b; It comprises the 13 NMOS pipe group M13, the 14 NMOS pipe group M14, the 15 NMOS pipe group M15, the 16 NMOS pipe group M16, the 17 NMOS pipe group M17, the 18 NMOS pipe group M18, the 11 NMOS pipe N11 and the 3rd PMOS pipe P3; The 13 NMOS pipe group M13 mainly is made up of two NMOS pipes, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection, and the 14 NMOS pipe group M14 mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes and drain electrode head and the tail serial connection; The 15 NMOS pipe group M15 mainly is made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, and the 16 NMOS pipe group M16 mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; The 17 NMOS pipe group M17 mainly is made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, and the 18 NMOS pipe group M18 mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, the drain electrode of the drain electrode of the drain electrode of first NMOS pipe of the 13 NMOS pipe group M13, first NMOS pipe of the 14 NMOS pipe group M14 and first NMOS pipe of the 15 NMOS pipe group M15 inserts the power clock signal Phi of amplitude level counterlogic 1 respectively 1, the source electrode of the source electrode of the source electrode of last NMOS pipe of the 13 NMOS pipe group M13, last NMOS pipe of the 14 NMOS pipe group M14 and last NMOS pipe of the 15 NMOS pipe group M15 respectively with S 2The signal output part of summing circuit module 23 is connected; The grid of two NMOS pipes of the 13 NMOS pipe group M13 is imported the corresponding sampled value of the complementary addend input signal sampled value corresponding with complementary summand input signal respectively; The grid of three NMOS pipes of the 14 NMOS pipe group M14 is imported the sampled value of the corresponding sampled value of addend input signal, summand input signal correspondence and the complementary corresponding sampled value of summand input signal respectively; The grid of three NMOS pipes of the 15 NMOS pipe group M15 is imported the sampled value of the corresponding sampled value of summand input signal, addend input signal correspondence and the complementary corresponding sampled value of addend input signal respectively; The drain electrode of the drain electrode of the drain electrode of first NMOS pipe of the 16 NMOS pipe group M16, first NMOS pipe of the 17 NMOS pipe group M17 and first NMOS pipe of the 18 NMOS pipe group M18 inserts the power clock signal Phi of amplitude level counterlogic 2 respectively, the source electrode of the source electrode of the source electrode of last NMOS pipe of the 16 NMOS pipe group M16, last NMOS pipe of the 17 NMOS pipe group M17 and last NMOS pipe of the 18 NMOS pipe group M18 respectively with S 2The signal output part of summing circuit module 23 is connected; The grid of two NMOS pipes of the 16 NMOS pipe group M16 is imported corresponding sampled value of addend input signal and the corresponding sampled value of summand input signal respectively; The grid of three NMOS pipe of the 17 NMOS pipe group M17 is imported corresponding sampled value of the corresponding sampled value of addend input signal, complementary addend input signal and the complementary corresponding sampled value of summand input signal respectively; The grid of three NMOS pipe of the 18 NMOS pipe group M18 is imported corresponding sampled value of the corresponding sampled value of summand input signal, complementary summand input signal and the complementary corresponding sampled value of addend input signal respectively; The drain electrode of the 3rd PMOS pipe P3 inserts the power clock signal Phi of amplitude level counterlogic 2, the drain electrode of the source electrode of the 3rd PMOS pipe P3 and the 11 NMOS pipe N11 respectively with S 2The signal output part of summing circuit module 23 is connected, and the grid of the 3rd PMOS pipe P3 is managed grid and the S of N11 respectively with the 11 NMOS 2The feedback signal input end of summing circuit module 23 promptly
Figure GSA00000075646500211
The output terminal of summing circuit module 24 is connected, and the source electrode of the 11 NMOS pipe N11 connects power supply ground.
In this specific embodiment,
Figure GSA00000075646500212
The summing circuit module is shown in Fig. 6 a; Its symbol is shown in Fig. 6 b; It comprises the 19 NMOS pipe group M19, the 20 NMOS pipe group M20, the 21 NMOS pipe group M21, the 22 NMOS pipe group M22, the 23 NMOS pipe group M23, the 24 NMOS pipe group M24, the 12 NMOS pipe N12 and the 4th PMOS pipe P4; The 19 NMOS pipe group M19 mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; The 20 NMOS pipe group M20 mainly is made up of the four NMOS pipe; And the source electrode of four NMOS pipe mainly is made up of two NMOS pipes with drain electrode head and the tail serial connection, the 21 NMOS pipe group M21, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; The 22 NMOS pipe group M22 mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes mainly is made up of three NMOS pipes with drain electrode head and the tail serial connection, the 23 NMOS pipe group M23, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection; The 24 NMOS pipe group M24 mainly is made up of two NMOS pipes; And the source electrodes of two NMOS pipe and drain electrode head and the tail serial connection, the drain electrode of the drain electrode of the drain electrode of first NMOS pipe of the 19 NMOS pipe group M19, first NMOS pipe of the 20 NMOS pipe group M20 and first NMOS pipe of the 21 NMOS pipe group M21 inserts the power clock signal Phi of amplitude level counterlogic 2 respectively, the source electrode of the source electrode of the source electrode of last NMOS pipe of the 19 NMOS pipe group M19, last NMOS pipe of the 20 NMOS pipe group M20 and last NMOS pipe of the 21 NMOS pipe group M21 respectively with
Figure GSA00000075646500221
The signal output part of summing circuit module 24 is connected; The grid of two NMOS pipes of the 19 NMOS pipe group M19 is imported the corresponding sampled value of the summand input signal sampled value corresponding with complementary addend input signal respectively; The grid of the four NMOS pipe of the 20 NMOS pipe group M20 is imported corresponding sampled value, the sampled value of summand input signal correspondence and the complementary corresponding sampled value of summand input signal of addend input signal of the corresponding sampled value of addend input signal, complementation respectively; The grid of two NMOS pipes of the 21 NMOS pipe group M21 is imported the corresponding sampled value of the addend input signal sampled value corresponding with complementary summand input signal respectively, and the drain electrode of the drain electrode of the drain electrode of first NMOS pipe of the 22 NMOS pipe group M22, first NMOS pipe of the 23 NMOS pipe group M23 and first NMOS pipe of the 24 NMOS pipe group M24 inserts the power clock signal Phi of amplitude level counterlogic 1 respectively 1, the source electrode of the source electrode of the source electrode of last NMOS pipe of the 22 NMOS pipe group M22, last NMOS pipe of the 23 NMOS pipe group M23 and last NMOS pipe of the 24 NMOS pipe group M24 respectively with
Figure GSA00000075646500222
The signal output part of summing circuit module 24 is connected; The grid of three NMOS pipes of the 22 NMOS pipe group M22 is imported the sampled value of the corresponding sampled value of summand input signal, addend input signal correspondence and the complementary corresponding sampled value of addend input signal respectively; The grid of three NMOS pipes of the 23 NMOS pipe group M23 is imported the sampled value of the corresponding sampled value of addend input signal, summand input signal correspondence and the complementary corresponding sampled value of summand input signal respectively; The grid of two NMOS pipes of the 24 NMOS pipe group M24 is imported the corresponding sampled value of the complementary addend input signal sampled value corresponding with complementary summand input signal respectively; The drain electrode of the 4th PMOS pipe P4 inserts the power clock signal Phi of amplitude level counterlogic 2, the drain electrode of the source electrode of the 4th PMOS pipe P4 and the 12 NMOS pipe N12 respectively with
Figure GSA00000075646500223
The signal output part of summing circuit module 24 is connected, the grid of the 4th PMOS pipe P4 respectively with the grid of the 12 NMOS pipe N12 with
Figure GSA00000075646500224
The feedback signal input end of summing circuit module 24 is S 2The output terminal of summing circuit module 23 is connected, and the source electrode of the 12 NMOS pipe N12 connects power supply ground.
In this specific embodiment; Carry output circuit 3 is shown in Fig. 2 a; Its symbol is shown in Fig. 2 b; Sampled value that the sampled value that its signal input part input addend input signal is corresponding, the sampled value that the summand input signal is corresponding, sampled value that low level carry input signal is corresponding, sampled value that complementary addend input signal is corresponding, complementary summand input signal are corresponding and the complementary corresponding sampled value of low level carry input signal; Carry output circuit 3 inserts the power clock signal Phi of amplitude level counterlogic 2, the signal output part output carry output signal C of carry output circuit OutCarry output signals with complementation
Figure GSA00000075646500231
Fig. 2 c has provided the clock clock signal of amplitude level counterlogic 2
Figure GSA00000075646500232
The synoptic diagram that concerns with the power clock signal Phi of amplitude level counterlogic 2.
At this, carry output circuit 3 is shown in Fig. 2 a, and it comprises carry output module 31 and complementary carry output module 32, the signal output part output carry output signal C of carry output module 31 Out, the complementary carry output signals of signal output part output of complementary carry output module 32 Carry output module 31 constitutes an intersection storage type structure with complementary carry output module 32.Carry output module 31 mainly is made up of the 25 NMOS pipe group M25, the 26 NMOS pipe group M26, the 27 NMOS pipe group M27, the 15 NMOS pipe N15 and the 5th PMOS pipe P5; The 25 NMOS pipe group M25 mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; The 26 NMOS pipe group M26 mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; The 27 NMOS pipe group M27 mainly is made up of the 13 NMOS pipe N13, a NMOS route of pipe line 271, the 2nd NMOS route of pipe line 272 and the 3rd NMOS route of pipe line 273; The one NMOS route of pipe line 271 and the 2nd NMOS route of pipe line 272 are formed by a NMOS pipe; The 3rd NMOS route of pipe line 273 is made up of two NMOS pipes and the source electrode of two NMOS pipes and the head and the tail serial connection that drains; The source electrode of the 13 NMOS pipe N13 is connected with the drain electrode of first NMOS pipe of the drain electrode of the NMOS pipe of the drain electrode of the NMOS pipe of a NMOS route of pipe line 271, the 2nd NMOS route of pipe line 272 and the 3rd NMOS route of pipe line 273 respectively; The drain electrode of the drain electrode of the drain electrode of the drain electrode of first NMOS pipe of the 25 NMOS pipe group M25, first NMOS pipe of the 26 NMOS pipe group M26, the 13 NMOS pipe N13 and the 5th PMOS pipe P5 all inserts the power clock signal Phi of amplitude level counterlogic 2; The source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of last NMOS pipe of the 25 NMOS pipe group M25, last NMOS pipe of the 26 NMOS pipe group M26, the NMOS pipe of a NMOS route of pipe line 271, the NMOS pipe of the 2nd NMOS route of pipe line 272, last NMOS pipe of the 3rd NMOS route of pipe line 273, the 5th PMOS pipe P5 all is connected with the signal output part of carry output module 31 with the drain electrode of the 15 NMOS pipe N15; The grid of two NMOS pipes of the 25 NMOS pipe group M25 is imported corresponding sampled value of addend input signal and the corresponding sampled value of summand input signal respectively; The grid of two NMOS pipes of the 26 NMOS pipe group M26 is imported corresponding sampled value of addend input signal and the corresponding sampled value of summand input signal respectively; The corresponding sampled value of grid input low level carry input signal of the 13 NMOS pipe N13; The corresponding sampled value of grid input addend input signal of the NMOS pipe of the one NMOS route of pipe line 271; The corresponding sampled value of grid input summand input signal of the NMOS pipe of the 2nd NMOS route of pipe line 272; The grid of two NMOS pipes of the 3rd NMOS route of pipe line 273 is imported corresponding sampled value of addend input signal and the corresponding sampled value of summand input signal respectively; The grid of the 5th PMOS pipe P5 is connected with the grid of the 15 NMOS pipe N15 and the signal output part of complementary carry output module 32 respectively, and the source electrode of the 15 NMOS pipe N15 connects power supply ground.Complementary carry output module 32 mainly is made up of the 28 NMOS pipe group M28, the 29 NMOS pipe group M29, the 30 NMOS pipe group M30, the 16 NMOS pipe N16 and the 6th PMOS pipe P6; The 28 NMOS pipe group M28 mainly is made up of the 14 NMOS pipe N14, the 4th NMOS route of pipe line 281, the 5th NMOS route of pipe line 282 and the 6th NMOS route of pipe line 283; The 4th NMOS route of pipe line 281 is made up of two NMOS pipes and the source electrode of two NMOS pipes and the head and the tail serial connection that drains; The 5th NMOS route of pipe line 282 and the 6th NMOS route of pipe line 283 are formed by a NMOS pipe; The 29 NMOS pipe group M29 mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; The 30 NMOS pipe group M30 mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; The source electrode of the 14 NMOS pipe N14 is connected with the drain electrode of the NMOS pipe of the drain electrode of the NMOS pipe of the drain electrode of first NMOS pipe of the 4th NMOS route of pipe line 281, the 5th NMOS route of pipe line 282 and the 6th NMOS route of pipe line 283 respectively; The drain electrode of the drain electrode of the drain electrode of the drain electrode of the 14 NMOS pipe N14, first NMOS pipe of the 29 NMOS pipe group M29, first NMOS pipe of the 30 NMOS pipe group M30 and the 6th PMOS pipe P6 all inserts the power clock signal Phi of amplitude level counterlogic 2; The source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of last NMOS pipe of the 4th NMOS route of pipe line 281, the NMOS pipe of the 2nd NMOS route of pipe line 282, the NMOS pipe of the 3rd NMOS route of pipe line 283, last NMOS pipe of the 29 NMOS pipe group M29, last NMOS pipe of the 30 NMOS pipe group M30, the 6th PMOS pipe P6 all is connected with the signal output part of complementary carry output module 32 with the drain electrode of the 16 NMOS pipe N16; The grid of two NMOS pipes of the 4th NMOS route of pipe line 281 is imported the corresponding sampled value of the complementary addend input signal sampled value corresponding with complementary summand input signal respectively; The corresponding sampled value of summand input signal that the grid input of the NMOS pipe of the 5th NMOS route of pipe line 282 is complementary; The corresponding sampled value of addend input signal that the grid input of the NMOS pipe of the 6th NMOS route of pipe line 283 is complementary; The grid of two NMOS pipes of the 29 NMOS pipe group M29 is imported the corresponding sampled value of the complementary addend input signal sampled value corresponding with complementary summand input signal respectively; The grid of two NMOS pipes of the 30 NMOS pipe group M30 is imported the corresponding sampled value of the complementary addend input signal sampled value corresponding with complementary summand input signal respectively; The corresponding sampled value of low level carry input signal that the grid input of the 14 NMOS pipe N14 is complementary; The grid of the 6th PMOS pipe P6 is connected with the grid of the 16 NMOS pipe N16 and the signal output part of carry output module 31 respectively, and the source electrode of the 16 NMOS pipe N16 connects power supply ground.
In this specific embodiment, the power clock signal of amplitude level counterlogic 2 is identical with the phase place of the power clock signal of amplitude level counterlogic 1, and with 180 ° of the phasic differences mutually of the clock clock signal of amplitude level counterlogic 2.
Embodiment two:
The tri-valued, thermal-insulating and low-power totalizer that a kind of tri-valued, thermal-insulating and low-power adder unit that is provided by embodiment one constitutes; As shown in Figure 9; It comprises 4 tri-valued, thermal-insulating and low-power adder units, and the input end input 0 that first tri-valued, thermal-insulating and low-power adder unit TAFA0 is used to import low level carry input signal is C InThe input end that=0, first tri-valued, thermal-insulating and low-power adder unit TAFA0 is used to import complementary low level carry input signal inserts the clock clock signal of amplitude level counterlogic 2
Figure GSA00000075646500251
Promptly
Figure GSA00000075646500252
First tri-valued, thermal-insulating and low-power adder unit TAFA0 is used for the signal output part C of output carry output signal 0The signal input part that is used to import low level carry input signal with second tri-valued, thermal-insulating and low-power adder unit TAFA1 is connected, and first tri-valued, thermal-insulating and low-power adder unit TAFA0 is used to export the signal output part of complementary carry output signals
Figure GSA00000075646500253
The signal input part that is used to import complementary low level carry input signal with second tri-valued, thermal-insulating and low-power adder unit TAFA1 is connected, and second tri-valued, thermal-insulating and low-power adder unit TAFA1 is used for the signal output part C of output carry output signal 1The signal input part that is used to import low level carry input signal with the 3rd tri-valued, thermal-insulating and low-power adder unit TAFA2 is connected, and second tri-valued, thermal-insulating and low-power adder unit TAFA1 is used to export the signal output part of complementary carry output signals
Figure GSA00000075646500254
The signal input part that is used to import complementary low level carry input signal with the 3rd tri-valued, thermal-insulating and low-power adder unit TAFA2 is connected, and the 3rd tri-valued, thermal-insulating and low-power adder unit TAFA2 is used for the signal output part C of output carry output signal 2The signal input part that is used to import low level carry input signal with the 4th tri-valued, thermal-insulating and low-power adder unit TAFA3 is connected, and the 3rd tri-valued, thermal-insulating and low-power adder unit TAFA2 is used to export the signal output part of complementary carry output signals The signal input part that is used to import complementary low level carry input signal with the 4th tri-valued, thermal-insulating and low-power adder unit TAFA3 is connected.
In this specific embodiment; Because the time delay of " Design of a DTCTGAL circuit and its application " (author: WangPengjun, Li Kunpeng, Mei Fengna) disclosed DTCTGAL (the Double Power-clock TernaryClocked Transmission Gate Adiabatic Logic) impact damper/reverser among each tri-valued, thermal-insulating and low-power adder unit and the Chinese Journal ofSemiconductors is identical; Be the clock period half; Therefore be used to import the signal input part of addend input signal, the signal input part that is used to import the summand input signal, the signal input part that is used to import the signal input part of complementary addend input signal and is used to import complementary summand input signal at each tri-valued, thermal-insulating and low-power adder unit and be respectively arranged with several DTCTGAL impact dampers 91; And the number of the DTCTGAL impact damper 91 that each signal input part of any tri-valued, thermal-insulating and low-power adder unit is provided with is identical, and the number of a DTCTGAL impact damper 91 of each signal input part setting of two adjacent tri-valued, thermal-insulating and low-power adder units is inequality; The signal output part that each tri-valued, thermal-insulating and low-power adder unit is used to export summation output signal is respectively arranged with several the 2nd DTCTGAL impact dampers 92 with the signal output part that is used to export complementary summation output signal; And the number of the 2nd DTCTGAL impact damper 92 that each signal output part of any tri-valued, thermal-insulating and low-power adder unit is provided with is identical; And the number of the 2nd DTCTGAL impact damper 92 of each signal output part setting of two adjacent tri-valued, thermal-insulating and low-power adder units is inequality; Through adding a DTCTGAL impact damper 91 and the 2nd DTCTGAL impact damper 92; Can regulate the phase relation of four each input signals of tri-valued, thermal-insulating and low-power totalizer and each output signal well; Make the output signal all postpone two cycles, and the output signal of the signal output part of each tri-valued, thermal-insulating and low-power adder unit output can be read in the same moment than input signal.The signal input part of first tri-valued, thermal-insulating and low-power adder unit TAFA0 of four tri-valued, thermal-insulating and low-power totalizers shown in Figure 9 is not provided with a DTCTGAL impact damper; The signal output part of first tri-valued, thermal-insulating and low-power adder unit TAFA0 is provided with three the 2nd DTCTGAL impact dampers 92; Be 1.5 cycles the time delay of three the 2nd DTCTGAL impact dampers 92, and always be 2 cycles the time delay that adds a tri-valued, thermal-insulating and low-power adder unit TAFA0; The signal input part of second tri-valued, thermal-insulating and low-power adder unit TAFA1 is provided with one the one DTCTGAL impact damper 91; The input of its input signal is than the input delay half period of the input signal of first tri-valued, thermal-insulating and low-power adder unit TAFA0; The output of second tri-valued, thermal-insulating and low-power adder unit TAFA1 is than the output delay half period of first tri-valued, thermal-insulating and low-power adder unit TAFA0; But, make the output signal of second tri-valued, thermal-insulating and low-power adder unit TAFA1 output and the output signal of first tri-valued, thermal-insulating and low-power adder unit TAFA0 output to read simultaneously through two the 2nd DTCTGAL impact dampers 92 are set at its signal output part; The signal input part of the 3rd tri-valued, thermal-insulating and low-power adder unit TAFA2 is provided with two the one DTCTGAL impact dampers 91; The input of its input signal is than the input delay half period of the input signal of second tri-valued, thermal-insulating and low-power adder unit TAFA1; The output of the 3rd tri-valued, thermal-insulating and low-power adder unit TAFA2 is than the output delay half period of second tri-valued, thermal-insulating and low-power adder unit TAFA1; But, make the output signal of the 3rd tri-valued, thermal-insulating and low-power adder unit TAFA2 output and the output signal of second tri-valued, thermal-insulating and low-power adder unit TAFA1 output to read simultaneously through one the 2nd DTCTGAL impact damper 92 is set at its signal output part; The signal input part of the 4th tri-valued, thermal-insulating and low-power adder unit TAFA3 is provided with three the one DTCTGAL impact dampers 91; The input of its input signal is than the input delay half period of the input signal of the 3rd tri-valued, thermal-insulating and low-power adder unit TAFA2; The output of the 4th tri-valued, thermal-insulating and low-power adder unit TAFA3 is than the output delay half period of the 3rd tri-valued, thermal-insulating and low-power adder unit TAFA2; But at its signal output part the 2nd DTCTGAL impact damper is not set, makes the output signal of the 4th tri-valued, thermal-insulating and low-power adder unit TAFA3 output and the output signal of the 3rd tri-valued, thermal-insulating and low-power adder unit TAFA1 output to read simultaneously like this.
Four tri-valued, thermal-insulating and low-power totalizers shown in Figure 9 also inserted another amplitude level counterlogic 1 power clock signal
Figure GSA00000075646500261
this be because the clock clock signal
Figure GSA00000075646500262
of amplitude level counterlogic 2 is used as the clock clock signal in the corresponding levels; Then can be used as the power clock signal at next stage uses; The power clock signal Phi of amplitude level counterlogic 2 is used as the power clock signal in the corresponding levels; Then can be used as the clock clock signal at next stage uses; Therefore the clock clock signal of working as amplitude level counterlogic 2 is used as the power clock signal; And the power clock signal Phi of amplitude level counterlogic 2 is as the clock clock enabling signal time spent; For keeping the phase place unanimity of two power clock signals, introduced the power clock signal of another amplitude level counterlogic 1
An above-mentioned DTCTGAL impact damper 91 comes down to one with the 2nd DTCTGAL impact damper 92 can guarantee input signal and the identical delayer of output signal; The output of the one DTCTGAL impact damper 91 and the 2nd DTCTGAL impact damper 92 all postpones the clock period half than input, promptly differs 180 degree.Specifically look the figure place of tri-valued, thermal-insulating and low-power totalizer to be designed and determine in total number of the 2nd DTCTGAL impact damper of DTCTGAL impact damper of the signal input part setting of each tri-valued, thermal-insulating and low-power adder unit and signal output part setting; Four tri-valued, thermal-insulating and low-power totalizers shown in Figure 9 only need postpone two cycles; Therefore total only need be provided with three grades of impact dampers; If need design five tri-valued, thermal-insulating and low-power totalizers then the level Four impact damper need be set; If need design six tri-valued, thermal-insulating and low-power totalizers then the Pyatyi impact damper need be set, and the like.
For explaining that better tri-valued, thermal-insulating and low-power totalizer of the present invention has correct logic functions and tangible low-power consumption characteristic, carries out computer simulation experiment.
Adopt TSMC 0.25 μ m CMOS technology device parameters, four tri-valued, thermal-insulating and low-power totalizers of the present invention are carried out computer simulation, analog waveform is shown in figure 10.The power clock signal Phi of amplitude level counterlogic 1 wherein 1,
Figure GSA00000075646500272
With the clock signal Φ of amplitude level counterlogic 2, the clock signal of amplitude level counterlogic 2
Figure GSA00000075646500273
Amplitude voltage be respectively 1.25V and 2.5V, the breadth length ratio of NMOS pipe is all got 0.36 μ m/0.24 μ m, the breadth length ratio of PMOS pipe is all got 0.72 μ m/0.24 μ m, A 3A 2A 1A 0Be addend, B 3B 2B 1B 0Be summand, S 3S 2S 1S 0Be four bit parallels summation output, C OutBe carry output.As can be seen from Figure 10, summation output signal and carry output signals all postpone two cycles than input signal, meet the designing requirement of four tri-valued, thermal-insulating and low-power totalizers.Through analyzing, prove that totalizer of the present invention has correct logic functions.
Under the situation that adopts identical input; With " A general method in the synthesis of ternary doublepass-transistor the circuits " (author: [semiconductor journal Hang Guoqiang) among four tri-valued, thermal-insulating and low-power totalizers of the present invention and the ChineseJournal of Semiconductors; " universal synthesis of the two transfer tube circuit of three values ", Hang Guoqiang] disclosed DPL three value totalizers carry out the comparison of transient state energy consumption, and are shown in figure 11; The reflection of the rising part of transient state energy consumption curve is injected energy to circuit among Figure 11; Sloping portion shows by power supply and recovers energy, the energy consumption of the phenomenon reflection circuit that edges up of curve concave bottom, and along with the circuit working time increases; Energy consumption saving trend is obvious further; In 0.9 μ s time, it is about 90% that tri-valued, thermal-insulating and low-power totalizer of the present invention is saved energy consumption, suffices to show that totalizer of the present invention has tangible low-power consumption characteristic.
Totalizer of the present invention is compared with existing totalizer, in design process, has adopted the insulated design technology, uses the alternating-current pulse power supply to be circuit supply; Inject through accomplishing energy to the charging of output node electric capacity; And, make totalizer have extremely low power consumption, simultaneously through reclaiming electric charge to the power supply realization energy recovery on the node capacitor; This totalizer adopts three value input and output signals, has simplified the wiring of circuit and has improved integration density; In addition, the method for designing of totalizer of the present invention can promote the use of in the MULTI-VALUED LOGIC CIRCUIT of Gao Ji more, to reduce the power consumption of MULTI-VALUED LOGIC CIRCUIT system.

Claims (9)

1. tri-valued, thermal-insulating and low-power adder unit; The input signal of this adder unit comprises addend input signal, summand input signal, low level carry input signal, complementary addend input signal, complementary summand input signal and complementary low level carry input signal; It is characterized in that this adder unit comprises input signal sample circuit, summation output circuit and carry output circuit; The signal input part of described input signal sample circuit is imported the summand input signal of described addend input signal, described summand input signal, described low level carry input signal, the addend input signal of described complementation, described complementation and the low level carry input signal of described complementation; Described input signal sample circuit inserts the clock clock signal of amplitude level counterlogic 2; The clock clock signal of described amplitude level counterlogic 2 is controlled described input signal sample circuit the summand input signal of described addend input signal, described summand input signal, described low level carry input signal, the addend input signal of described complementation, described complementation and the low level carry input signal of described complementation is sampled, and the signal output part of described input signal sample circuit is exported the summand input signal of described addend input signal, described summand input signal, described low level carry input signal, the addend input signal of described complementation, described complementation and each self-corresponding one group of sampled value of low level carry input signal of described complementation;
Described summation output circuit mainly is made up of four summing circuit modules; The signal input part of four described summing circuit modules is all imported the corresponding sampled value of the addend input signal of the corresponding sampled value of described addend input signal, the sampled value that described summand input signal is corresponding, described complementation and the corresponding sampled value of summand input signal of described complementation; Four described summing circuit modules all insert the power clock signal of amplitude level counterlogic 2 and the power clock signal of amplitude level counterlogic 1 respectively, and four described summing circuit modules are designated as S respectively 0, S 2With
Figure FSB00000559918400012
Described S 0The signal output part of summing circuit module and described
Figure FSB00000559918400013
The feedback signal input end of summing circuit module is connected, and is described
Figure FSB00000559918400014
The signal output part of summing circuit module and described S 0The feedback signal input end of summing circuit module is connected, described S 2The signal output part of summing circuit module and described The feedback signal input end of summing circuit module is connected; Described
Figure FSB00000559918400016
The signal output part of summing circuit module and described S 2The feedback signal input end of summing circuit module is connected, described S 0The signal output part of summing circuit module and described summation output circuit are used to export between the signal output part of summation output signal and are provided with NMOS pipe, the source electrode and the described S of described NMOS pipe 0The signal output part of summing circuit module is connected; The drain electrode of described NMOS pipe and described summation output circuit are used to export the signal output part that summation exports signal and are connected; The grid of described NMOS pipe inserts the corresponding sampled value of low level carry input signal of described complementation, and is described
Figure FSB00000559918400017
The signal output part of summing circuit module and described summation output circuit are used to export between the signal output part of complementary summation output signal and are provided with the 2nd NMOS pipe, the source electrode of described the 2nd NMOS pipe and described
Figure FSB00000559918400021
The signal output part of summing circuit module is connected; The drain electrode of described the 2nd NMOS pipe and described summation output circuit are used to export the signal output part that complementary summation exports signal and are connected; The grid of described the 2nd NMOS pipe inserts the corresponding sampled value of low level carry input signal of described complementation, described S 2The signal output part of summing circuit module and described summation output circuit are used to export between the signal output part of summation output signal and are provided with the 3rd NMOS pipe, the source electrode and the described S of described the 3rd NMOS pipe 2The signal output part of summing circuit module is connected; The drain electrode of described the 3rd NMOS pipe and described summation output circuit are used to export the signal output part that summation exports signal and are connected; The grid of described the 3rd NMOS pipe inserts the corresponding sampled value of described low level carry input signal, and is described The signal output part of summing circuit module and described summation output circuit are used to export between the signal output part of complementary summation output signal and are provided with the 4th NMOS pipe, the source electrode of described the 4th NMOS pipe and described
Figure FSB00000559918400023
The signal output part of summing circuit module is connected; The signal output part that the drain electrode of described the 4th NMOS pipe and described summation output circuit are used to export complementary summation output signal is connected, and the grid of described the 4th NMOS pipe inserts the sampled value of described low level carry input signal correspondence;
The signal input part of described carry output circuit is imported the corresponding sampled value of the summand input signal of the corresponding sampled value of the addend input signal of the corresponding sampled value of described addend input signal, the sampled value that described summand input signal is corresponding, the sampled value that described low level carry input signal is corresponding, described complementation, described complementation and the corresponding sampled value of low level carry input signal of described complementation; Described carry output circuit inserts the power clock signal of amplitude level counterlogic 2, the signal output part output carry output signal and the complementary carry output signals of described carry output circuit;
The power clock signal of described amplitude level counterlogic 2 is identical with the phase place of the power clock signal of described amplitude level counterlogic 1, and with 180 ° of the phasic differences mutually of the clock clock signal of described amplitude level counterlogic 2.
2. a kind of tri-valued, thermal-insulating and low-power adder unit according to claim 1; It is characterized in that being provided with in the described summation output circuit the 5th NMOS pipe, the 6th NMOS pipe, the 7th NMOS pipe and the 8th NMOS pipe, the source electrode of described the 5th NMOS pipe respectively with described S 0Summing circuit module and described The input end that the summing circuit module is used to insert the power clock signal of described amplitude level counterlogic 2 is connected, the source electrode of described the 6th NMOS pipe respectively with described S 2Summing circuit module and described
Figure FSB00000559918400025
The input end that the summing circuit module is used to insert the power clock signal of described amplitude level counterlogic 2 is connected; The drain electrode of the drain electrode of described the 5th NMOS pipe and described the 6th NMOS pipe all inserts the power clock signal of described amplitude level counterlogic 2, and the source electrode of described the 7th NMOS pipe is respectively with described
Figure FSB00000559918400026
Summing circuit module and described S 0The input end that the summing circuit module is used to insert the power clock signal of described amplitude level counterlogic 1 is connected, and the source electrode of described the 8th NMOS pipe is respectively with described
Figure FSB00000559918400031
Summing circuit module and described S 2The input end that the summing circuit module is used to insert the power clock signal of described amplitude level counterlogic 1 is connected; The drain electrode of the drain electrode of described the 7th NMOS pipe and described the 8th NMOS pipe all inserts the power clock signal of described amplitude level counterlogic 1; The grid of the grid of described the 5th NMOS pipe and described the 7th NMOS pipe interconnects with the grid of described NMOS pipe and the grid of described the 2nd NMOS pipe respectively, and the grid of the grid of described the 6th NMOS pipe and described the 8th NMOS pipe interconnects with the grid of described the 3rd NMOS pipe and the grid of described the 4th NMOS pipe respectively.
3. a kind of tri-valued, thermal-insulating and low-power adder unit according to claim 1 and 2 is characterized in that described S 0The summing circuit module comprises a NMOS pipe group, the 2nd NMOS pipe group, the 3rd NMOS pipe group, the 4th NMOS pipe group, the 5th NMOS pipe group, the 6th NMOS pipe group, the 9th NMOS pipe and PMOS pipe; A described NMOS pipe group mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; Described the 2nd NMOS pipe group mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes and drain electrode head and the tail serial connection; Described the 3rd NMOS pipe group mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes mainly is made up of two NMOS pipes with drain electrode head and the tail serial connection, described the 4th NMOS pipe group, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; Described the 5th NMOS pipe group mainly is made up of the four NMOS pipe; And the source electrode of four NMOS pipe mainly is made up of two NMOS pipes with drain electrode head and the tail serial connection, described the 6th NMOS pipe group, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; The drain electrode of the drain electrode of the drain electrode of first NMOS pipe of a described NMOS pipe group, first NMOS pipe of described the 2nd NMOS pipe group and first NMOS pipe of described the 3rd NMOS pipe group inserts the power clock signal of described amplitude level counterlogic 1 respectively, the source electrode of the source electrode of the source electrode of last NMOS pipe of a described NMOS pipe group, last NMOS pipe of described the 2nd NMOS pipe group and last NMOS pipe of described the 3rd NMOS pipe group respectively with described S 0The signal output part of summing circuit module is connected; The grid of two NMOS pipes of a described NMOS pipe group is imported corresponding sampled value of described addend input signal and the corresponding sampled value of described summand input signal respectively; The grid of three NMOS pipe of described the 2nd NMOS pipe group is imported the corresponding sampled value of the addend input signal of the corresponding sampled value of described addend input signal, described complementation and the corresponding sampled value of summand input signal of described complementation respectively; The grid of three NMOS pipe of described the 3rd NMOS pipe group is imported the corresponding sampled value of the summand input signal of the corresponding sampled value of described summand input signal, described complementation and the corresponding sampled value of addend input signal of described complementation respectively; The drain electrode of the drain electrode of the drain electrode of first NMOS pipe of described the 4th NMOS pipe group, first NMOS pipe of described the 5th NMOS pipe group and first NMOS pipe of described the 6th NMOS pipe group inserts the power clock signal of described amplitude level counterlogic 2 respectively, the source electrode of the source electrode of the source electrode of last NMOS pipe of described the 4th NMOS pipe group, last NMOS pipe of described the 5th NMOS pipe group and last NMOS pipe of described the 6th NMOS pipe group respectively with described S 0The signal output part of summing circuit module is connected; The grid of two NMOS pipes of described the 4th NMOS pipe group is imported the corresponding sampled value of summand input signal of corresponding sampled value of described addend input signal and described complementation respectively; The grid of the four NMOS pipe of described the 5th NMOS pipe group is imported corresponding sampled value, the sampled value of described summand input signal correspondence and the corresponding sampled value of summand input signal of described complementation of addend input signal of the corresponding sampled value of described addend input signal, described complementation respectively; The grid of two NMOS pipes of described the 6th NMOS pipe group is imported the corresponding sampled value and the corresponding sampled value of described summand input signal of addend input signal of described complementation respectively; The drain electrode of described PMOS pipe inserts the power clock signal of described amplitude level counterlogic 2, the drain electrode of the source electrode of described PMOS pipe and described the 9th NMOS pipe respectively with described S 0The signal output part of summing circuit module is connected, the grid of described PMOS pipe respectively with the grid and the described S of described the 9th NMOS pipe 0The feedback signal input end of summing circuit module is connected, and the source electrode of described the 9th NMOS pipe connects power supply ground;
Described summing circuit module comprises the 7th NMOS pipe group, the 8th NMOS pipe group, the 9th NMOS pipe group, the tenth NMOS pipe group, the 11 NMOS pipe group, the 12 NMOS pipe group, the tenth NMOS pipe and the 2nd PMOS pipe; Described the 7th NMOS pipe group mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes and drain electrode head and the tail serial connection; Described the 8th NMOS pipe group mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes and drain electrode head and the tail serial connection; Described the 9th NMOS pipe group mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; Described the tenth NMOS pipe group mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes and drain electrode head and the tail serial connection; Described the 11 NMOS pipe group mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes mainly is made up of two NMOS pipes with drain electrode head and the tail serial connection, described the 12 NMOS pipe group, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; The drain electrode of the drain electrode of the drain electrode of first NMOS pipe of described the 7th NMOS pipe group, first NMOS pipe of described the 8th NMOS pipe group and first NMOS pipe of described the 9th NMOS pipe group inserts the power clock signal of described amplitude level counterlogic 2 respectively; The source electrode of the source electrode of the source electrode of last NMOS pipe of described the 7th NMOS pipe group, last NMOS pipe of described the 8th NMOS pipe group and last NMOS pipe of described the 9th NMOS pipe group is connected with the signal output part of described
Figure FSB00000559918400042
summing circuit module respectively, and the grid of three NMOS pipes of described the 7th NMOS pipe group is imported the corresponding sampled value of the corresponding sampled value of described summand input signal, described addend input signal and the corresponding sampled value of addend input signal of described complementation respectively, and the grid of three NMOS pipes of described the 8th NMOS pipe group is imported the corresponding sampled value of the corresponding sampled value of described addend input signal, described summand input signal and the corresponding sampled value of summand input signal of described complementation respectively; The grid of two NMOS pipe of described the 9th NMOS pipe group is imported the corresponding sampled value of the addend input signal of described complementation and the corresponding sampled value of summand input signal of described complementation respectively; The drain electrode of the drain electrode of the drain electrode of first NMOS pipe of described the tenth NMOS pipe group, first NMOS pipe of described the 11 NMOS pipe group and first NMOS pipe of described the 12 NMOS pipe group inserts the power clock signal of described amplitude level counterlogic 1 respectively, and the source electrode of the source electrode of the source electrode of last NMOS pipe of described the tenth NMOS pipe group, last NMOS pipe of described the 11 NMOS pipe group and last NMOS pipe of described the 12 NMOS pipe group is connected with the signal output part of described
Figure FSB00000559918400051
summing circuit module respectively, and the grid of three NMOS pipes of described the tenth NMOS pipe group is imported the corresponding sampled value of the summand input signal of the corresponding sampled value of described summand input signal, described complementation and the corresponding sampled value of addend input signal of described complementation respectively; The grid of three NMOS pipe of described the 11 NMOS pipe group is imported the corresponding sampled value of the addend input signal of the corresponding sampled value of described addend input signal, described complementation and the corresponding sampled value of summand input signal of described complementation respectively; The grid of two NMOS pipes of described the 12 NMOS pipe group is imported corresponding sampled value of described addend input signal and the corresponding sampled value of described summand input signal respectively, and the drain electrode of described the 2nd PMOS pipe inserts the power clock signal of described amplitude level counterlogic 2, and the source electrode of described the 2nd PMOS pipe is connected with the signal output part of described
Figure FSB00000559918400052
summing circuit module respectively with the drain electrode of described the tenth NMOS pipe; The grid of described the 2nd PMOS pipe is connected with the grid of described the tenth NMOS pipe and the feedback signal input end of described
Figure FSB00000559918400053
summing circuit module respectively, and the source electrode of described the tenth NMOS pipe connects power supply ground;
Described S 2The summing circuit module comprises the 13 NMOS pipe group, the 14 NMOS pipe group, the 15 NMOS pipe group, the 16 NMOS pipe group, the 17 NMOS pipe group, the 18 NMOS pipe group, the 11 NMOS pipe and the 3rd PMOS pipe; Described the 13 NMOS pipe group mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; Described the 14 NMOS pipe group mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes and drain electrode head and the tail serial connection; Described the 15 NMOS pipe group mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes mainly is made up of two NMOS pipes with drain electrode head and the tail serial connection, described the 16 NMOS pipe group, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; Described the 17 NMOS pipe group mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes mainly is made up of three NMOS pipes with drain electrode head and the tail serial connection, described the 18 NMOS pipe group, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection; The drain electrode of the drain electrode of the drain electrode of first NMOS pipe of described the 13 NMOS pipe group, first NMOS pipe of described the 14 NMOS pipe group and first NMOS pipe of described the 15 NMOS pipe group inserts the power clock signal of described amplitude level counterlogic 1 respectively, the source electrode of the source electrode of the source electrode of last NMOS pipe of described the 13 NMOS pipe group, last NMOS pipe of described the 14 NMOS pipe group and last NMOS pipe of described the 15 NMOS pipe group respectively with described S 2The signal output part of summing circuit module is connected; The grid of two NMOS pipe of described the 13 NMOS pipe group is imported the corresponding sampled value of the addend input signal of described complementation and the corresponding sampled value of summand input signal of described complementation respectively; The grid of three NMOS pipes of described the 14 NMOS pipe group is imported the sampled value of the corresponding sampled value of described addend input signal, described summand input signal correspondence and the corresponding sampled value of summand input signal of described complementation respectively; The grid of three NMOS pipes of described the 15 NMOS pipe group is imported the sampled value of the corresponding sampled value of described summand input signal, described addend input signal correspondence and the corresponding sampled value of addend input signal of described complementation respectively; The drain electrode of the drain electrode of the drain electrode of first NMOS pipe of described the 16 NMOS pipe group, first NMOS pipe of described the 17 NMOS pipe group and first NMOS pipe of described the 18 NMOS pipe group inserts the power clock signal of described amplitude level counterlogic 2 respectively, the source electrode of the source electrode of the source electrode of last NMOS pipe of described the 16 NMOS pipe group, last NMOS pipe of described the 17 NMOS pipe group and last NMOS pipe of described the 18 NMOS pipe group respectively with described S 2The signal output part of summing circuit module is connected; The grid of two NMOS pipes of described the 16 NMOS pipe group is imported corresponding sampled value of described addend input signal and the corresponding sampled value of described summand input signal respectively; The grid of three NMOS pipe of described the 17 NMOS pipe group is imported the corresponding sampled value of the addend input signal of the corresponding sampled value of described addend input signal, described complementation and the corresponding sampled value of summand input signal of described complementation respectively; The grid of three NMOS pipe of described the 18 NMOS pipe group is imported the corresponding sampled value of the summand input signal of the corresponding sampled value of described summand input signal, described complementation and the corresponding sampled value of addend input signal of described complementation respectively; The drain electrode of described the 3rd PMOS pipe inserts the power clock signal of described amplitude level counterlogic 2, the drain electrode of the source electrode of described the 3rd PMOS pipe and described the 11 NMOS pipe respectively with described S 2The signal output part of summing circuit module is connected, the grid of described the 3rd PMOS pipe respectively with the grid and the described S of described the 11 NMOS pipe 2The feedback signal input end of summing circuit module is connected, and the source electrode of described the 11 NMOS pipe connects power supply ground;
Described summing circuit module comprises the 19 NMOS pipe group, the 20 NMOS pipe group, the 21 NMOS pipe group, the 22 NMOS pipe group, the 23 NMOS pipe group, the 24 NMOS pipe group, the 12 NMOS pipe and the 4th PMOS pipe; Described the 19 NMOS pipe group mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; Described the 20 NMOS pipe group mainly is made up of the four NMOS pipe; And the source electrode of four NMOS pipe and drain electrode head and the tail serial connection; Described the 21 NMOS pipe group mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; Described the 22 NMOS pipe group mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes and drain electrode head and the tail serial connection; Described the 23 NMOS pipe group mainly is made up of three NMOS pipes; And the source electrode of three NMOS pipes mainly is made up of two NMOS pipes with drain electrode head and the tail serial connection, described the 24 NMOS pipe group, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; The drain electrode of the drain electrode of the drain electrode of first NMOS pipe of described the 19 NMOS pipe group, first NMOS pipe of described the 20 NMOS pipe group and first NMOS pipe of described the 21 NMOS pipe group inserts the power clock signal of described amplitude level counterlogic 2 respectively; The source electrode of the source electrode of the source electrode of last NMOS pipe of described the 19 NMOS pipe group, last NMOS pipe of described the 20 NMOS pipe group and last NMOS pipe of described the 21 NMOS pipe group is connected with the signal output part of described
Figure FSB00000559918400071
summing circuit module respectively, and the grid that two NMOS of described the 19 NMOS pipe group manage is imported the corresponding sampled value of addend input signal of corresponding sampled value of described summand input signal and described complementation respectively, and the grid of the four NMOS pipe of described the 20 NMOS pipe group is imported corresponding sampled value, the sampled value of described summand input signal correspondence and the corresponding sampled value of summand input signal of described complementation of addend input signal of the corresponding sampled value of described addend input signal, described complementation respectively; The grid of two NMOS pipes of described the 21 NMOS pipe group is imported the corresponding sampled value of summand input signal of corresponding sampled value of described addend input signal and described complementation respectively; The drain electrode of the drain electrode of the drain electrode of first NMOS pipe of described the 22 NMOS pipe group, first NMOS pipe of described the 23 NMOS pipe group and first NMOS pipe of described the 24 NMOS pipe group inserts the power clock signal of described amplitude level counterlogic 1 respectively, and the source electrode of the source electrode of last NMOS pipe of the source electrode that last NMOS of described the 22 NMOS pipe group manages, described the 23 NMOS pipe group and last NMOS pipe of described the 24 NMOS pipe group is connected with the signal output part of described summing circuit module respectively, and the grid of three NMOS pipes of described the 22 NMOS pipe group is imported the sampled value of the corresponding sampled value of described summand input signal, described addend input signal correspondence and the corresponding sampled value of addend input signal of described complementation respectively; The grid of three NMOS pipes of described the 23 NMOS pipe group is imported the sampled value of the corresponding sampled value of described addend input signal, described summand input signal correspondence and the corresponding sampled value of summand input signal of described complementation respectively; The grid of two NMOS pipe of described the 24 NMOS pipe group is imported the corresponding sampled value of the addend input signal of described complementation and the corresponding sampled value of summand input signal of described complementation respectively, and the drain electrode of described the 4th PMOS pipe inserts the power clock signal of described amplitude level counterlogic 2, and the source electrode of described the 4th PMOS pipe is connected with the signal output part of described
Figure FSB00000559918400073
summing circuit module respectively with the drain electrode of described the 12 NMOS pipe; The grid of described the 4th PMOS pipe is connected with the grid of described the 12 NMOS pipe and the feedback signal input end of described
Figure FSB00000559918400074
summing circuit module respectively, and the source electrode of described the 12 NMOS pipe connects power supply ground.
4. a kind of tri-valued, thermal-insulating and low-power adder unit according to claim 3; It is characterized in that described carry output circuit comprises carry output module and complementary carry output module; The signal output part of described carry output module is exported described carry output signals; The signal output part of described complementary carry output module is exported the carry output signals of described complementation; Described carry output module mainly is made up of the 25 NMOS pipe group, the 26 NMOS pipe group, the 27 NMOS pipe group, the 15 NMOS pipe and the 5th PMOS pipe; Described the 25 NMOS pipe group mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; Described the 26 NMOS pipe group mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; Described the 27 NMOS pipe group mainly is made up of the 13 NMOS pipe, a NMOS route of pipe line, the 2nd NMOS route of pipe line and the 3rd NMOS route of pipe line; A described NMOS route of pipe line and described the 2nd NMOS route of pipe line are formed by a NMOS pipe; Described the 3rd NMOS route of pipe line is made up of two NMOS pipes and the source electrode of two NMOS pipes and the head and the tail serial connection that drains; The source electrode of described the 13 NMOS pipe is connected with the drain electrode of first NMOS pipe of the drain electrode of the NMOS pipe of the drain electrode of the NMOS pipe of a described NMOS route of pipe line, described the 2nd NMOS route of pipe line and described the 3rd NMOS route of pipe line respectively; The drain electrode of the drain electrode of the drain electrode of first NMOS pipe of described the 25 NMOS pipe group, first NMOS pipe of described the 26 NMOS pipe group, the drain electrode of described the 13 NMOS pipe and described the 5th PMOS pipe all inserts the power clock signal of described amplitude level counterlogic 2; The drain electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of last NMOS pipe of described the 25 NMOS pipe group, last NMOS pipe of described the 26 NMOS pipe group, the NMOS pipe of a described NMOS route of pipe line, the NMOS pipe of described the 2nd NMOS route of pipe line, last NMOS pipe of described the 3rd NMOS route of pipe line, the source electrode of described the 5th PMOS pipe and described the 15 NMOS pipe all is connected with the signal output part of described carry output module, and the grid of two NMOS pipes of described the 25 NMOS pipe group is imported corresponding sampled value of described addend input signal and the corresponding sampled value of described summand input signal respectively, and the grid of two NMOS pipes of described the 26 NMOS pipe group is imported corresponding sampled value of described addend input signal and the corresponding sampled value of described summand input signal respectively; The grid of described the 13 NMOS pipe is imported the corresponding sampled value of described low level carry input signal; The grid of the NMOS pipe of a described NMOS route of pipe line is imported the corresponding sampled value of described addend input signal, and the grid of the NMOS pipe of described the 2nd NMOS route of pipe line is imported the corresponding sampled value of described summand input signal, and the grid of two NMOS pipes of described the 3rd NMOS route of pipe line is imported corresponding sampled value of described addend input signal and the corresponding sampled value of described summand input signal respectively; The grid of described the 5th PMOS pipe is connected with the grid of described the 15 NMOS pipe and the signal output part of described complementary carry output module respectively, and the source electrode of described the 15 NMOS pipe connects power supply ground;
Described complementary carry output module mainly is made up of the 28 NMOS pipe group, the 29 NMOS pipe group, the 30 NMOS pipe group, the 16 NMOS pipe and the 6th PMOS pipe; Described the 28 NMOS pipe group mainly is made up of the 14 NMOS pipe, the 4th NMOS route of pipe line, the 5th NMOS route of pipe line and the 6th NMOS route of pipe line; Described the 4th NMOS route of pipe line is made up of two NMOS pipes and the source electrode of two NMOS pipes and the head and the tail serial connection that drains; Described the 5th NMOS route of pipe line and described the 6th NMOS route of pipe line are formed by a NMOS pipe; Described the 29 NMOS pipe group mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; Described the 30 NMOS pipe group mainly is made up of two NMOS pipes; And the source electrode of two NMOS pipes and drain electrode head and the tail serial connection; The source electrode of described the 14 NMOS pipe is connected with the drain electrode of the NMOS pipe of the drain electrode of the NMOS pipe of the drain electrode of first NMOS pipe of described the 4th NMOS route of pipe line, described the 5th NMOS route of pipe line and described the 6th NMOS route of pipe line respectively; The drain electrode of the drain electrode of first NMOS pipe of the drain electrode of described the 14 NMOS pipe, described the 29 NMOS pipe group, first NMOS pipe of described the 30 NMOS pipe group and the drain electrode of described the 6th PMOS pipe all insert the power clock signal of described amplitude level counterlogic 2; The drain electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of last NMOS pipe of described the 4th NMOS route of pipe line, the NMOS pipe of described the 5th NMOS route of pipe line, the NMOS pipe of described the 6th NMOS route of pipe line, last NMOS pipe of described the 29 NMOS pipe group, last NMOS pipe of described the 30 NMOS pipe group, the source electrode of described the 6th PMOS pipe and described the 16 NMOS pipe all is connected with the signal output part of described complementary carry output module; The grid of two NMOS pipe of described the 4th NMOS route of pipe line is imported the corresponding sampled value of the addend input signal of described complementation and the corresponding sampled value of summand input signal of described complementation respectively; The grid of the NMOS pipe of described the 5th NMOS route of pipe line is imported the corresponding sampled value of summand input signal of described complementation; The grid of the NMOS pipe of described the 6th NMOS route of pipe line is imported the corresponding sampled value of addend input signal of described complementation; The grid of two NMOS pipe of described the 29 NMOS pipe group is imported the corresponding sampled value of the addend input signal of described complementation and the corresponding sampled value of summand input signal of described complementation respectively; The grid of two NMOS pipe of described the 30 NMOS pipe group is imported the corresponding sampled value of the addend input signal of described complementation and the corresponding sampled value of summand input signal of described complementation respectively; The grid of described the 14 NMOS pipe is imported the corresponding sampled value of low level carry input signal of described complementation; The grid of described the 6th PMOS pipe is connected with the grid of described the 16 NMOS pipe and the signal output part of described carry output module respectively, and the source electrode of described the 16 NMOS pipe connects power supply ground.
5. a kind of tri-valued, thermal-insulating and low-power adder unit according to claim 4; It is characterized in that described input signal sample circuit comprises original input signal sample circuit module and complementary input signal sample circuit module; Described original input signal sample circuit module mainly is made up of one group of NMOS pipe; The source electrode of each NMOS pipe in the described original input signal sample circuit module is imported described addend input signal, described summand input signal and described low level carry input signal respectively; The drain electrode of each NMOS pipe in the described original input signal sample circuit module is respectively as former sampling node; Export one group of sampled value and one group of corresponding sampled value of described low level carry input signal of one group of corresponding sampled value of described addend input signal, described summand input signal correspondence, the grid of each NMOS pipe in the described original input signal sample circuit module inserts the clock clock signal of described amplitude level counterlogic 2; Described complementary input signal sample circuit module mainly is made up of another group NMOS pipe; The source electrode of each NMOS pipe in the described complementary input signal sample circuit module is imported the summand input signal of the addend input signal of described complementation, described complementation and the low level carry input signal of described complementation respectively; The drain electrode of each NMOS pipe in the described complementary input signal sample circuit module is respectively as complementary sampling node; Export one group of corresponding sampled value of the summand input signal of one group of corresponding sampled value of the addend input signal of described complementation, described complementation and one group of corresponding sampled value of low level carry input signal of described complementation, the grid of each NMOS pipe in the described complementary input signal sample circuit module inserts the clock clock signal of described amplitude level counterlogic 2.
6. tri-valued, thermal-insulating and low-power totalizer that constitutes by the described tri-valued, thermal-insulating and low-power adder unit of claim 1; It is characterized in that comprising a plurality of tri-valued, thermal-insulating and low-power adder units; Described tri-valued, thermal-insulating and low-power adder unit comprises input signal sample circuit, summation output circuit and carry output circuit; The signal input part of described input signal sample circuit is imported the summand input signal of described addend input signal, described summand input signal, described low level carry input signal, the addend input signal of described complementation, described complementation and the low level carry input signal of described complementation; Described input signal sample circuit inserts the clock clock signal of amplitude level counterlogic 2; The clock clock signal of described amplitude level counterlogic 2 is controlled described input signal sample circuit the summand input signal of described addend input signal, described summand input signal, described low level carry input signal, the addend input signal of described complementation, described complementation and the low level carry input signal of described complementation is sampled, and the signal output part of described input signal sample circuit is exported the summand input signal of described addend input signal, described summand input signal, described low level carry input signal, the addend input signal of described complementation, described complementation and each self-corresponding one group of sampled value of low level carry input signal of described complementation;
Described summation output circuit mainly is made up of four summing circuit modules; The signal input part of four described summing circuit modules is all imported the corresponding sampled value of the addend input signal of the corresponding sampled value of described addend input signal, the sampled value that described summand input signal is corresponding, described complementation and the corresponding sampled value of summand input signal of described complementation; Four described summing circuit modules all insert the power clock signal of amplitude level counterlogic 2 and the power clock signal of amplitude level counterlogic 1 respectively, and four described summing circuit modules are designated as S respectively 0,
Figure FSB00000559918400101
S 2With
Figure FSB00000559918400102
Described S 0The signal output part of summing circuit module and described
Figure FSB00000559918400103
The feedback signal input end of summing circuit module is connected, and is described
Figure FSB00000559918400104
The signal output part of summing circuit module and described S 0The feedback signal input end of summing circuit module is connected, described S 2The signal output part of summing circuit module and described The feedback signal input end of summing circuit module is connected, and is described The signal output part of summing circuit module and described S 2The feedback signal input end of summing circuit module is connected, described S 0The signal output part of summing circuit module and described summation output circuit are used to export between the signal output part of summation output signal and are provided with NMOS pipe, the source electrode and the described S of described NMOS pipe 0The signal output part of summing circuit module is connected; The drain electrode of described NMOS pipe and described summation output circuit are used to export the signal output part that summation exports signal and are connected; The grid of described NMOS pipe inserts the corresponding sampled value of low level carry input signal of described complementation, and is described The signal output part of summing circuit module and described summation output circuit are used to export between the signal output part of complementary summation output signal and are provided with the 2nd NMOS pipe, the source electrode of described the 2nd NMOS pipe and described
Figure FSB00000559918400111
The signal output part of summing circuit module is connected; The drain electrode of described the 2nd NMOS pipe and described summation output circuit are used to export the signal output part that complementary summation exports signal and are connected; The grid of described the 2nd NMOS pipe inserts the corresponding sampled value of low level carry input signal of described complementation, described S 2The signal output part of summing circuit module and described summation output circuit are used to export between the signal output part of summation output signal and are provided with the 3rd NMOS pipe, the source electrode and the described S of described the 3rd NMOS pipe 2The signal output part of summing circuit module is connected; The drain electrode of described the 3rd NMOS pipe and described summation output circuit are used to export the signal output part that summation exports signal and are connected; The grid of described the 3rd NMOS pipe inserts the corresponding sampled value of described low level carry input signal, and is described The signal output part of summing circuit module and described summation output circuit are used to export between the signal output part of complementary summation output signal and are provided with the 4th NMOS pipe, the source electrode of described the 4th NMOS pipe and described
Figure FSB00000559918400113
The signal output part of summing circuit module is connected; The signal output part that the drain electrode of described the 4th NMOS pipe and described summation output circuit are used to export complementary summation output signal is connected, and the grid of described the 4th NMOS pipe inserts the sampled value of described low level carry input signal correspondence;
The signal input part of described carry output circuit is imported the corresponding sampled value of the summand input signal of the corresponding sampled value of the addend input signal of the corresponding sampled value of described addend input signal, the sampled value that described summand input signal is corresponding, the sampled value that described low level carry input signal is corresponding, described complementation, described complementation and the corresponding sampled value of low level carry input signal of described complementation; Described carry output circuit inserts the power clock signal of amplitude level counterlogic 2, the signal output part output carry output signal and the complementary carry output signals of described carry output circuit;
The signal input part that the signal output part that each described tri-valued, thermal-insulating and low-power adder unit is used for output carry output signal and the described tri-valued, thermal-insulating and low-power adder unit of next bit are used to import low level carry input signal is connected; The signal input part that the signal output part that each described tri-valued, thermal-insulating and low-power adder unit is used to export complementary carry output signals and the described tri-valued, thermal-insulating and low-power adder unit of next bit are used to import the low level carry input signal of complementation is connected; The described tri-valued, thermal-insulating and low-power adder unit of lowest order is used to import the signal input part input 0 of low level carry input signal, and the signal input part that the described tri-valued, thermal-insulating and low-power adder unit of lowest order is used to import complementary low level carry input signal inserts the clock clock signal of amplitude level counterlogic 2;
The power clock signal of described amplitude level counterlogic 2 is identical with the phase place of the power clock signal of described amplitude level counterlogic 1, and with 180 ° of the phasic differences mutually of the clock clock signal of described amplitude level counterlogic 2.
7. a kind of tri-valued, thermal-insulating and low-power totalizer according to claim 6; It is characterized in that each described tri-valued, thermal-insulating and low-power adder unit is used to import the signal input part of addend input signal, is used to import the signal input part of summand input signal, the signal input part that is used to import the signal input part of complementary addend input signal and is used to import complementary summand input signal is respectively arranged with several DTCTGAL impact dampers; And the number of the described DTCTGAL impact damper that each signal input part of any described tri-valued, thermal-insulating and low-power adder unit is provided with is identical, and the number of a described DTCTGAL impact damper of each signal input part setting of two adjacent described tri-valued, thermal-insulating and low-power adder units is inequality; The signal output part that each described tri-valued, thermal-insulating and low-power adder unit is used to export summation output signal is respectively arranged with several the 2nd DTCTGAL impact dampers with the signal output part that is used to export complementary summation output signal; And the number of described the 2nd DTCTGAL impact damper that each signal output part of any described tri-valued, thermal-insulating and low-power adder unit is provided with is identical, and the number of described the 2nd DTCTGAL impact damper of each signal output part setting of two adjacent described tri-valued, thermal-insulating and low-power adder units is inequality.
8. a kind of tri-valued, thermal-insulating and low-power totalizer according to claim 7; The time delay that it is characterized in that the time delay of a described DTCTGAL impact damper, described the 2nd DTCTGAL impact damper is identical with the time delay of described tri-valued, thermal-insulating and low-power adder unit, is the clock period half.
9. according to claim 7 or 8 described a kind of tri-valued, thermal-insulating and low-power totalizers; It is characterized in that a described DTCTGAL impact damper and described the 2nd DTCTGAL impact damper are input signal and the identical impact damper of output signal, the output of a described DTCTGAL impact damper and described the 2nd DTCTGAL impact damper all postpones the clock period half than input.
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