CN101431332B - High-speed phase discriminator - Google Patents

Abstract

The invention relates to a high-speed phase detector, in particular to a high-speed phase detector based on the single-phase-clock dynamic CMOS technology, belonging to the technical field of signal processing and the circuit thereof. Based on the traditional phase detector, a time delay module is added to a feedback loop, so that no dead zone exists when the phase detector is in operation; and a high speed D trigger is used for replacing the traditional low speed D trigger, thereby causing the working speed of the phase detector to reach 900 MHz. The phase detector has the advantages of high working speed, easy manufacture, and no dead zone during the operation, and is especially suitable for precisely differentiating the phase difference of two input signals in a delay-locked loop.

Description

high speed phase detector

technical field

The invention relates to a high-speed phase detector, to be precise, relates to a high-speed phase detector based on single-phase clock dynamic CMOS technology, and belongs to the technical field of signal processing and its circuit.

Background technique

With the rapid development of integrated circuit technology, the operating frequency of the microprocessor is increasing year by year. At present, Intel has launched a microprocessor chip with a main frequency exceeding 3GHz. The main frequency of general-purpose microprocessor chips is generally above 100 MHz. Due to the limitations of PCB technology, it is difficult for the motherboard to provide a clock signal above 200MHz for the chip. Therefore, a stable high-frequency clock generation circuit is required inside the chip. With the improvement of people's requirements for low power consumption, short lock time and high speed, the traditional high frequency clock generation circuit can no longer meet the requirements, so it is necessary to design a high frequency clock signal generation circuit with short lock time. Therefore, it is more and more important to design a high-performance delay-locked loop (Delay Locked Loop-DLL). The phase detector (Phase Detector-PD) is a key module in the delay-locked loop. It compares the phase of the input signal, outputs a pulse signal with a pulse width corresponding to the phase difference, and drives the subsequent circuit to make the delay-locked loop The tracking of the phase is completed to generate a high-frequency clock signal.

The design of the phase detector is mainly concerned with the operating speed, jitter, gain and dead zone issues. A traditional phase detector is shown in Figure 1. This kind of phase detector has a large capture range, fast locking speed, and relatively simple circuit, but it also has many shortcomings, such as the dead zone problem, which refers to the minimum phase difference that the phase detector can identify; the working speed is not fast enough , only about 100MHz, which cannot meet the requirements of current products.

Contents of the invention

The technical problem to be solved by the invention is to introduce a high-speed phase detector. The phase detector has fast working speed and no dead zone, which makes up for the shortcomings of the traditional phase detector.

In order to solve the above-mentioned technical problems, the present invention adopts the following technical solutions. On the basis of the traditional phase detector, a delay module is added in the feedback loop, so that there is no dead zone when the phase detector works, and the traditional low-speed D flip-flop is replaced by a high-speed D flip-flop, so that the detector The phase device works fast, reaching 900MHz.

The technical solution of the present invention will now be described in detail in conjunction with the accompanying drawings.

A high-speed phase detector, including a first D flip-flop 1, a second D flip-flop 2, a third NOR gate NOR3, the circuit structure of the first D flip-flop 1 and the second D flip-flop 2 are exactly the same, and the third The NOR gate NOR3 is a two-input NOR gate, the first D flip-flop 1 has D port, Q port and RST port, the second D flip-flop 2 has D port, Q port and RST port, the third NOR gate NOR3 There are the fifth input terminal IN5, the sixth input terminal IN6 and the third output terminal OUT3, which is characterized in that it also contains the first NOR gate NOR1, the second NOR gate NOR2, the delay unit Delay, the first NOR gate Both NOR1 and the second NOR gate NOR2 are two-input NOR gates. The first NOR gate NOR1 has a first input terminal IN1, a second input terminal IN2 and a first output terminal OUT1, and the second NOR gate NOR2 has a first input terminal IN1. Three input terminals IN3, a fourth input terminal IN4 and a second output terminal OUT2, the delay unit Delay has a seventh input terminal IN7 and a fourth output terminal OUT4, the phase detector has two input terminals and two output terminals, two The two input terminals are A input terminal A and B input terminal B, and the two output terminals are Q _A output terminal Q _A and Q _B output terminal Q _B , A input terminal A is connected to the D port of the first D flip-flop 1, B The input terminal B is connected to the D port of the second D flip-flop 2, the second input terminal IN2, the RST port of the first D flip-flop 1, the fourth output terminal OUT4, the RST port of the second D flip-flop 2 and the fourth input The terminals IN4 are connected together, the Q port of the first D flip-flop 1 is connected with the first input terminal IN1, the Q port of the second D flip-flop 2 is connected with the third input terminal IN3, the fifth input terminal IN5 and the sixth input terminal IN6 is respectively connected to the Q port of the first D flip-flop 1 and the Q port of the second D flip-flop 2, the third output terminal OUT3 is connected to the seventh input terminal IN7, and the first output terminal OUT1 is connected to the Q _A output terminal Q _A , the second output terminal OUT2 is connected to the Q _B output terminal Q _B .

The further feature of the technical solution of the present invention is that the circuit structures of the first D flip-flop 1 and the second D flip-flop 2 are completely the same, and the first D flip-flop 1 includes a first MOS transistor M1, a second MOS transistor M2, a third The MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5 and the sixth MOS transistor M6, the first MOS transistor M1, the second MOS transistor M2 and the fourth MOS transistor M4 are PMOS transistors, the third MOS transistor M3, the sixth MOS transistor M6 The fifth MOS transistor M5 and the sixth MOS transistor M6 are NMOS transistors, the first MOS transistor M1, the third MOS transistor M3 and the fifth MOS transistor M5 are connected in series and then bridged between the positive power supply terminal VDD and the negative power supply terminal GND: the first The source of a MOS transistor M1 is connected to the positive power supply terminal VDD, the drain of the first MOS transistor M1 is connected to the drain of the third MOS transistor M3, the source of the third MOS transistor M3 is connected to the drain of the fifth MOS transistor M5 connection, the source of the fifth MOS transistor M5 is connected to the negative terminal of the power supply GND, the second MOS transistor M2, the fourth MOS transistor M4 and the sixth MOS transistor M6 are connected in series and connected across the positive terminal VDD of the power supply and the negative terminal GND of the power supply Between: the source of the second MOS transistor M2 is connected to the positive power supply terminal VDD, the drain of the second MOS transistor M2 is connected to the source of the fourth MOS transistor M4, the drain of the fourth MOS transistor M4 is connected to the sixth MOS transistor M6 The drain of the sixth MOS transistor M6 is connected to the negative power supply GND, the source of the third MOS transistor M3, the drain of the fifth MOS transistor M5, the gate of the second MOS transistor M2 and the sixth MOS transistor M2 The gates of the transistor M6 are connected together, the gate of the third MOS transistor M3 is connected to the gate of the fourth MOS transistor M4 as the D port of the first D flip-flop 1, the gate of the first MOS transistor M1 is connected to the gate of the fifth The gate of the MOS transistor M5 is connected to serve as the RST port of the first D flip-flop 1 , and the drain of the second MOS transistor M2 is connected to the source of the fourth MOS transistor M4 to serve as the Q port of the first D flip-flop 1 .

Compared with background technology, the present invention has following advantage:

1. The traditional D flip-flop uses more MOS tubes, which greatly affects the working speed of the D flip-flop, which in turn affects the working speed of the phase detector, and also increases the difficulty of making the D flip-flop. The D flip-flop in the present invention uses less MOS tubes, the D flip-flop has a high working speed, the phase detector has a high working speed, and the D flip-flop is easy to manufacture.

2. The feedback loop of the traditional phase detector is too simple, which will also cause a dead zone in the phase detector, which greatly affects the phase detection accuracy of the phase detector. In the present invention, a new loop structure is adopted, and a delay unit is added, which completely solves the dead zone problem of the circuit and greatly improves the phase detection accuracy of the phase detector.

Description of drawings

Figure 1 is a circuit block diagram of a traditional phase detector.

Fig. 2 is a circuit block diagram of the high-speed phase detector of the present invention.

FIG. 3 is a circuit diagram of a D flip-flop used in the high-speed phase detector of the present invention.

FIG. 4 is a circuit diagram of the high-speed phase detector of the present invention.

Detailed ways

The technical scheme and working principle of the present invention will now be described in detail in conjunction with the drawings and embodiments. The high-speed phase detector of the embodiment has exactly the same circuit structure as the high-speed phase detector described in the summary of the invention, and only key technical data are listed below.

Example

The width-to-length ratios of the first MOS transistor M1, the second MOS transistor M2, and the fourth MOS transistor M4 are all 2 μm/0.18 μm, and the width-to-length ratios of the third MOS transistor M3, the fifth MOS transistor M5, and the sixth MOS transistor M6 are all 2 μm/0.18 μm. is 1μm/0.18μm;

The delay unit Delay is formed by cascading two stages of NOT gates. The width-to-length ratio of the PMOS tube in the NOT gate is 10 μm/0.6 μm, and the width-to-length ratio of the NMOS tube is 5 μm/0.6 μm.

The supply voltage is 1.8V;

The working speed is 900MHz.

The working principle of the high-speed phase detector of this embodiment will be described in detail below with reference to FIG. 4 . In FIG. 4, the MOS transistors used by the second D flip-flop 2 use the first 'MOS transistor M1', the second 'MOS transistor M2', the third 'MOS transistor M3', and the corresponding first D flip-flop 1. The fourth 'MOS transistor M4', the fifth 'MOS transistor M5' and the sixth 'MOS transistor M6' indicate that the gate of the sixth MOS transistor M6 and the gate of the sixth 'MOS transistor M6' are respectively defined as the first node X and the second node X', the fourth output terminal OUT4 is defined as the third node RESET, the output terminal Q of the first D flip-flop 1 is defined as the fourth node Q1, and the output terminal Q of the second D flip-flop 2 is defined as the first Five-node Q2.

In the initial state, the third node RESET is at low level, the first MOS transistor M1 and the first 'MOS transistor M1' are turned on, and the fifth MOS transistor M5 and the fifth 'MOS transistor M5' are turned off. When the signal A leads the signal B , that is, the rising edge of the input signal A appears first, and the input signal B is still at a low level. At this time, the third MOS transistor M3 is turned on, and the fourth MOS transistor M4 is turned off, so the first node X is at a high level, so that the second The MOS transistor M2 is turned off, and the fourth node Q1 maintains the original state, that is, the low level. Because the input signal B is still at low level at this time, the third 'MOS transistor M3' is cut off, and the fifth 'MOS transistor M5' is also cut off, so the second node X' is in a hold state, that is, low level, so that the second 'MOS transistor M3' is cut off. The MOS transistor M2 ′ is turned on, and the sixth MOS transistor M6 ′ is turned off, and the fifth node Q2 is at a high level at this time. Because the fourth node Q1 is at low level, and the fifth node Q2 is at high level, after passing through the third NOR gate NOR3, the third node RESET remains at low level, passing through the first NOR gate NOR1 and the second After the NOR gate NOR2, the output signal Q _A is high level, and Q _B is low level, indicating that the input signal A leads the input signal B.

When the input signal B leads the input signal A, the circuit action is similar to the circuit action when the input signal A leads the input signal B, and the final result is that the output signal Q _A is low level, and the output signal Q _B is high level.

When the input signal A and the input signal B are in the same phase, the fourth node Q1 and the fifth node Q2 are both at low level, and when passing through the third NOR gate NOR3, the third node RESET is converted from low level to high level. When the fifth MOS transistor M5 and the fifth 'MOS transistor M5' are turned on, the first node X and the second node X' are converted from high level to low level, and the second MOS transistor M2 and the second 'MOS transistor M2' turn on, so that the fourth node Q1 and the fifth node Q2 are at a high level, and the above process is also a process of feedback setting a high level. The Q _A output terminal Q _A and the Q _B output terminal Q _B each output a pulse, which is at a high level at the same time, and then switches from a high level to a low level at the same time, so it is judged that the input signal A and the input signal B are in the same phase . In short, when the input signal A leads the input signal B, the Q _A output terminal Q _A is high level, and the Q _B output terminal Q _B is low level; when the input signal A lags the input signal B, the Q _B output terminal Q _B is high level, Q _A output terminal Q _A is low level; when the input signal A and B are in phase, both Q _A output terminal Q _A and Q _B output terminal Q _B are high level; when Q _A output When both Q _A and Q _B output Q _B are at low level, it means that the phase detector is in the process of judging.

To sum up, this embodiment compares the phases of two input signals through a simple circuit, which can accurately and quickly determine whether the signals are leading, lagging or in-phase, and provides accurate and fast judgments for the delay locked loop, thereby ensuring delay locking The ring can provide a high-speed stable clock signal. The phase detector is especially suitable for accurately discriminating the phase difference of two input signals in a delay locked loop.

Claims (4)

1. high-speed phase discriminator, contain first d type flip flop (1), second d type flip flop (2), the 3rd NOR gate (NOR3), the circuit structure of first d type flip flop (1) and second d type flip flop (2) is identical, the 3rd NOR gate (NOR3) is two input NOR gate, first d type flip flop (1) has the D port, Q port and RST port, second d type flip flop (2) has the D port, Q port and RST port, the 3rd NOR gate (NOR3) has the 5th input (IN5), the 6th input (IN6) and the 3rd output (OUT3), it is characterized in that, it also contains first NOR gate (NOR1), second NOR gate (NOR2), delay unit (Delay), first NOR gate (NOR1) and second NOR gate (NOR2) all are two input NOR gate, first NOR gate (NOR1) has first input end (IN1), second input (IN2) and first output (OUT1), second NOR gate (NOR2) has the 3rd input (IN3), four-input terminal (IN4) and second output (OUT2), delay unit (Delay) has the 7th input (IN7) and the 4th output (OUT4), this phase discriminator has two inputs and two outputs, two inputs are A input (A) and B input (B), and two outputs are Q _AOutput (Q _A) and Q _BOutput (Q _B), A input (A) is connected with the D port of first d type flip flop (1), B input (B) is connected with the D port of second d type flip flop (2), second input (IN2), the RST port of first d type flip flop (1), the 4th output (OUT4), the RST port and the four-input terminal (IN4) of second d type flip flop (2) link together, the Q port of first d type flip flop (1) is connected with first input end (IN1), the Q port of second d type flip flop (2) is connected with the 3rd input (IN3), the 5th input (IN5) is connected with the Q port of first d type flip flop (1) and the Q port of second d type flip flop (2) respectively with the 6th input (IN6), the 3rd output (OUT3) is connected with the 7th input (IN7), first output (OUT1) and Q _AOutput (Q _A) connect second output (OUT2) and Q _BOutput (Q _B) connect.

2. high-speed phase discriminator according to claim 1, it is characterized in that, first d type flip flop (1) contains first metal-oxide-semiconductor (M1), second metal-oxide-semiconductor (M2), the 3rd metal-oxide-semiconductor (M3), the 4th metal-oxide-semiconductor (M4), the 5th metal-oxide-semiconductor (M5) and the 6th metal-oxide-semiconductor (M6), first metal-oxide-semiconductor (M1), second metal-oxide-semiconductor (M2) and the 4th metal-oxide-semiconductor (M4) are the PMOS pipes, the 3rd metal-oxide-semiconductor (M3), the 5th metal-oxide-semiconductor (M5) and the 6th metal-oxide-semiconductor (M6) are the NMOS pipes, first metal-oxide-semiconductor (M1), be connected across between power positive end (VDD) and the power supply negative terminal (GND) after the 3rd metal-oxide-semiconductor (M3) and the 5th metal-oxide-semiconductor (M5) serial connection: the source electrode of first metal-oxide-semiconductor (M1) is connected with power positive end (VDD), the drain electrode of first metal-oxide-semiconductor (M1) is connected with the drain electrode of the 3rd metal-oxide-semiconductor (M3), the source electrode of the 3rd metal-oxide-semiconductor (M3) is connected with the drain electrode of the 5th metal-oxide-semiconductor (M5), the source electrode of the 5th metal-oxide-semiconductor (M5) is connected with power supply negative terminal (GND), second metal-oxide-semiconductor (M2), be connected across between power positive end (VDD) and the power supply negative terminal (GND) after the 4th metal-oxide-semiconductor (M4) and the 6th metal-oxide-semiconductor (M6) serial connection: the source electrode of second metal-oxide-semiconductor (M2) is connected with power positive end (VDD), the drain electrode of second metal-oxide-semiconductor (M2) is connected with the source electrode of the 4th metal-oxide-semiconductor (M4), the drain electrode of the 4th metal-oxide-semiconductor (M4) is connected with the drain electrode of the 6th metal-oxide-semiconductor (M6), the source electrode of the 6th metal-oxide-semiconductor (M6) is connected with power supply negative terminal (GND), the source electrode of the 3rd metal-oxide-semiconductor (M3), the drain electrode of the 5th metal-oxide-semiconductor (M5), the grid of the grid of second metal-oxide-semiconductor (M2) and the 6th metal-oxide-semiconductor (M6) links together, the grid of the 3rd metal-oxide-semiconductor (M3) is connected the D port of back as first d type flip flop (1) with the grid of the 4th metal-oxide-semiconductor (M4), the grid of first metal-oxide-semiconductor (M1) is connected the RST port of back as first d type flip flop (1) with the grid of the 5th metal-oxide-semiconductor (M5), the drain electrode of second metal-oxide-semiconductor (M2) is connected the Q port of back as first d type flip flop (1) with the source electrode of the 4th metal-oxide-semiconductor (M4).

3. high-speed phase discriminator according to claim 1 is characterized in that, delay unit (Delay) is formed by the cascade of two-stage not gate.

4. high-speed phase discriminator according to claim 1, it is characterized in that, first d type flip flop (1) contains first metal-oxide-semiconductor (M1), second metal-oxide-semiconductor (M2), the 3rd metal-oxide-semiconductor (M3), the 4th metal-oxide-semiconductor (M4), the 5th metal-oxide-semiconductor (M5) and the 6th metal-oxide-semiconductor (M6), first metal-oxide-semiconductor (M1), second metal-oxide-semiconductor (M2) and the 4th metal-oxide-semiconductor (M4) are the PMOS pipes, the 3rd metal-oxide-semiconductor (M3), the 5th metal-oxide-semiconductor (M5) and the 6th metal-oxide-semiconductor (M6) are the NMOS pipes, first metal-oxide-semiconductor (M1), be connected across between power positive end (VDD) and the power supply negative terminal (GND) after the 3rd metal-oxide-semiconductor (M3) and the 5th metal-oxide-semiconductor (M5) serial connection: the source electrode of first metal-oxide-semiconductor (M1) is connected with power positive end (VDD), the drain electrode of first metal-oxide-semiconductor (M1) is connected with the drain electrode of the 3rd metal-oxide-semiconductor (M3), the source electrode of the 3rd metal-oxide-semiconductor (M3) is connected with the drain electrode of the 5th metal-oxide-semiconductor (M5), the source electrode of the 5th metal-oxide-semiconductor (M5) is connected with power supply negative terminal (GND), second metal-oxide-semiconductor (M2), be connected across between power positive end (VDD) and the power supply negative terminal (GND) after the 4th metal-oxide-semiconductor (M4) and the 6th metal-oxide-semiconductor (M6) serial connection: the source electrode of second metal-oxide-semiconductor (M2) is connected with power positive end (VDD), the drain electrode of second metal-oxide-semiconductor (M2) is connected with the source electrode of the 4th metal-oxide-semiconductor (M4), the drain electrode of the 4th metal-oxide-semiconductor (M4) is connected with the drain electrode of the 6th metal-oxide-semiconductor (M6), the source electrode of the 6th metal-oxide-semiconductor (M6) is connected with power supply negative terminal (GND), the source electrode of the 3rd metal-oxide-semiconductor (M3), the drain electrode of the 5th metal-oxide-semiconductor (M5), the grid of the grid of second metal-oxide-semiconductor (M2) and the 6th metal-oxide-semiconductor (M6) links together, the grid of the 3rd metal-oxide-semiconductor (M3) is connected the D port of back as first d type flip flop (1) with the grid of the 4th metal-oxide-semiconductor (M4), the grid of first metal-oxide-semiconductor (M1) is connected the RST port of back as first d type flip flop (1) with the grid of the 5th metal-oxide-semiconductor (M5), the drain electrode of second metal-oxide-semiconductor (M2) is connected the Q port of back as first d type flip flop (1) with the source electrode of the 4th metal-oxide-semiconductor (M4), delay unit (Delay) is formed by the cascade of two-stage not gate.

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