CN101408864B - Data protection method for power failure and controller using the method - Google Patents

Abstract

The present invention proposes a data protection method, which is applicable to multiple physical blocks mapped by logical blocks in a non-volatile memory. The data protection method includes: recording data update information in each physical block, the data update information is used to identify the update relationship of data in the physical block; and re-obtaining the update relationship of the physical block based on the data update information, wherein the data update information is composed of multiple characters with a cyclic relationship, and the number of the characters is greater than the number of the physical blocks, wherein the data update information is recorded in each physical block in sequence based on the update relationship and the cyclic relationship.

Description

Data protection method for power failure and controller using the method

technical field

The invention relates to a data protection method, and in particular to a data protection method used for power failure and a controller using the method.

Background technique

The rapid growth of digital cameras, cell phone cameras, and MP3 players over the past few years has led to a rapid increase in consumers' demand for storage media. Because flash memory (Flash Memory) has data non-volatility, power saving, small size and no Features such as mechanical structure are suitable for portable applications, and are most suitable for use in such portable battery-powered products. In addition to the built-in storage needs of portable products, for external products such as small memory cards and flash drives, each person may have multiple flash drives and small memory cards at the same time, so the market size is larger than those devices. Therefore, the flash memory industry has become a very popular type in the electronics industry in recent years.

Flash memory is generally managed in units of blocks. If a single logical block maps multiple physical blocks and an abnormal power failure occurs when data is being written, it may cause data loss. incorrect or unstable phenomena. That is to say, the system cannot distinguish between the original data physical block and the new data physical block after the power is restored.

To solve the above problems, traditionally, relevant information is marked in one byte of the redundant area of each page of the physical block. For example, taking 3 physical blocks corresponding to 1 logical block as an example, using the feature that each bit of the flash memory can change from 1 to 0, the selected byte is written in multiple times to add different For example, FF means recorded in the first stage, FF is changed to 0F to represent recorded in the second stage, and 0F is changed to 00 to represent recorded in the third stage. That is, if the flag is FF, it means the newest data, while 0F means the second oldest data and 00 means the oldest data.

However, the known technology has the following problems. When the memory used is multi-level memory unit (Multi Level Cell, MLC) and non-(NAND) flash memory, since this type of flash memory can only be written once, it is impossible to use the above method of writing multiple times to mark. That is, in the case of MLC and non-flash memory, once the mark is written, it cannot be changed.

Based on this, it is necessary to develop a data protection method to effectively re-distinguish the update relationship of blocks after a power failure.

Contents of the invention

The invention provides a data protection method for a non-volatile memory, which can effectively re-distinguish old and new data after power off.

The present invention provides a controller that can execute a data protection method for a nonvolatile memory, which can effectively re-distinguish old and new data after power off.

The present invention proposes a data protection method, which is applicable to a plurality of physical blocks corresponding to logical blocks in a non-volatile memory. The data protection method includes: recording data update information in each physical block, data The update information is used to identify the update relationship of the data in the physical block; and re-establish the update relationship of the physical block according to the data update information, wherein the data update information is composed of a plurality of characters with a cyclic relationship, and each of the characters The number is greater than the number of the physical blocks, wherein the data update information recorded in each physical block is recorded sequentially according to the update relationship and the cycle relationship.

In an embodiment of the present invention, the above-mentioned characters are a plurality of numbers or a plurality of characters.

In an embodiment of the present invention, the above-mentioned reconstruction and update relationship includes identifying the physical block containing the data update information of the next character as the physical block with the oldest data according to the next character of the character used since the cyclic relationship, And sequentially identify the update relationship of other physical blocks according to the cycle relationship.

In an embodiment of the present invention, the above-mentioned reconstruction and update relationship includes identifying the physical block containing the data update information of the next character as the physical block with the latest data by using the next character of the unused character according to the cyclic relationship, And sequentially identify the update relationship of other physical blocks according to the cycle relationship.

In an embodiment of the present invention, the aforementioned recording of data update information in each physical block is recording the data update information in a redundant area of each physical block.

In an embodiment of the present invention, the above-mentioned non-volatile memory is a flash memory whose page can only be programmed once.

In an embodiment of the present invention, the above-mentioned flash memory is SLC (Single Level Cell) or MLC (Multi Level Cell) NAND flash memory.

The present invention provides a data protection device, which is suitable for a plurality of physical blocks corresponding to a logical block in a non-volatile memory. The data protection device includes: A module, which is located in each of the physical areas A data update information is recorded in the block, and the data update information is used to identify the update relationship of the data in the physical block; the B module judges whether there is a physical block that cannot identify the old and new relationship among the physical blocks; And the C module, which obtains the update relationship of the physical block whose new-old relationship cannot be identified according to the data update information when the B module judges that there is a physical block whose old-new relationship cannot be identified, wherein the data update information consists of a cycle relationship, and the number of the characters is greater than the number of the physical blocks, wherein the A module that records the data update information in each of the physical blocks is based on the update relationship and the Circular relationship to record sequentially.

The present invention proposes a data protection method, which can effectively record the data update information of one-to-many blocks and obtain the update relationship of the blocks from the data update information after an abnormal power failure, thereby avoiding Lost after power on.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, preferred embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1A illustrates a host using a non-volatile memory storage device according to an embodiment of the present invention.

FIG. 1B shows a detailed block diagram of the non-volatile memory storage device shown in FIG. 1A.

FIG. 1C is a block diagram illustrating a controller according to another embodiment of the present invention.

2A and 2B are detailed block diagrams illustrating a non-volatile memory and its operation according to an embodiment of the present invention.

FIG. 3 is a detailed block diagram illustrating the redundant region R of the page in FIG. 1B according to an embodiment of the present invention.

4A is a schematic diagram illustrating data update information when one logical block corresponds to three physical blocks according to an embodiment of the present invention.

FIG. 4B is a schematic diagram illustrating another data update information according to FIG. 4A .

FIG. 5 is a flowchart illustrating a data protection method according to a first embodiment of the present invention.

FIG. 6 is a flowchart illustrating a data protection method according to a second embodiment of the present invention.

FIG. 7 is a schematic diagram illustrating a device to which the wear leveling method of the embodiment of the present invention is applicable.

Description of reference symbols

100: Host

102: Microprocessor

104: random access memory

106: Input/Output Device

108: System bus

110: data transmission interface

120: Non-volatile memory storage device

122, 122': Controller

122a: Memory management module

122b: Non-volatile memory interface

122c: host transmission interface

122d: buffer memory

122e: Program memory

122f: Error correction module

122g: power management module

122h: Microprocessing unit

124: Non-volatile memory

124-0, 124-1, 124-2, 124-N: blocks

202: System area

204: data area

206: Spare area

208: Replacement area

210: Momentary Zone

M, C, T: blocks

302: Addressing tag

304: Update relationship marker

306: block status flag

308: Other tags

310: bytes for storing system information

320: Byte to store error correcting code

401: logical block

402, 403, 404: physical blocks

S501, S503, S505, S507, S509: steps

S601, S603, S605, S607, S609: steps

702: USB flash drive

704: Digital camera

704a: SD card

704b: MMC card

704c: CF card

704d: memory stick

706: SSD

Detailed ways

A non-volatile memory storage system generally includes a non-volatile memory and a controller (control chip). Typically, a non-volatile memory storage system is used with a host system so that the host system can write data to or read data from the non-volatile memory storage system. In addition, there is also a non-volatile memory storage system that includes an embedded non-volatile memory and software executable on a host system that essentially acts as a controller for the embedded flash memory.

FIG. 1A illustrates a host using a non-volatile memory storage device according to an embodiment of the present invention.

1A, the host 100 generally includes a microprocessor 102, a random access memory (random access memory, RAM) 104, an input/output (input/output, I/O) device 106, a system bus 108 and a data transmission interface 110. It must be understood that the host 100 may further include other components, such as a display device or a network device.

The host 100 may be a system such as a computer, a digital camera, a camcorder, a communication device, an audio player or a video player. In general, host 100 can be virtually any system that can store data.

In the embodiment of the present invention, the non-volatile memory storage device 120 is electrically connected with other components of the host 100 through the data transmission interface 110 . Through the processing of the microprocessor 102 , the random access memory 104 and the input/output device 106 , data can be written into the non-volatile memory storage device 120 or read from the non-volatile memory storage device 120 . The non-volatile memory storage device 120 includes a pen drive, a memory card or a solid state drive (Solid State Drive, SSD).

FIG. 1B shows a detailed block diagram of the non-volatile memory storage device shown in FIG. 1A.

Please refer to FIG. 1B , the nonvolatile memory storage device 120 generally includes a controller 122 and a nonvolatile memory 124 .

The controller 122 is used to control the overall operation of the non-volatile memory storage device 120 , such as data storage, reading and erasing. The controller 122 includes a memory management module 122a, a non-volatile memory interface 122b, a buffer memory 122d and a micro-processing unit 122h.

The memory management module 122a is used for managing the non-volatile memory 124, such as implementing wear leveling (wear leveling) method, bad block management, maintaining mapping table (mapping table) and so on.

The non-volatile memory interface 122b is used to access the non-volatile memory 124, that is, the data to be written by the host 100 will be converted into a format acceptable to the non-volatile memory 124 through the non-volatile memory interface 122b .

The buffer memory 122d is used for temporarily storing system data (such as a mapping table) or data read or written by the host. In this embodiment, the buffer memory 122d is a static random access memory (static random access memory, SRAM). However, it must be understood that the present invention is not limited thereto, and dynamic random access memory (DRAM), magnetoresistive memory (MRAM), phase change memory (PRAM) or other suitable memories can also be applied to the present invention.

The micro-processing unit 122h is used to control the overall operation of the controller 122 .

In another embodiment of the present invention, please refer to FIG. 1C , the controller 122' further includes a host transmission interface 122c, a programming memory 122e, an error correction module 122f and a power management module 122g.

Host transmission interface 122c is in order to communicate with host computer 100, and host transmission interface 122c can be USB interface, IEEE 1394 interface, SATA interface, PCI Express interface, MS interface, MMC interface, SD card interface, CF card interface or IDE interface.

The programming memory 122e is used for storing the programming code executed by the controller to control the non-volatile memory storage device 120 .

The error correction module 122f is used to calculate an error correcting code (error correcting code) to check and correct the data read or written by the host.

The power management module 122g is used for managing the power of the non-volatile memory storage device 120 .

The non-volatile memory 124 is used for storing data. In this implementation, the nonvolatile memory 124 is a flash memory, more specifically, the nonvolatile memory 124 is a multi-level memory cell (Multi LevelCell, MLC) and non-volatile (NAND) flash memory. But it must be understood that the present invention is not limited thereto, for example, the non-volatile memory 124 may also be a single-level cell (Single Level Cell, SLC) and a non-flash memory.

The non-volatile memory 124 is generally divided into a plurality of physical blocks (physical blocks) 124-0 to 124-N, and the physical blocks are referred to as blocks for convenience below. Generally speaking, a block is the smallest unit of erasing in a flash memory. That is, each block contains a minimum number of memory cells that are erased together. Each block is usually divided into multiple pages. A page is usually the smallest unit of programming, but it should be noted that for some different flash memory designs, the smallest programming unit can also be the size of a sector, that is, there are multiple sectors in a page And a sector is the smallest unit of programming. In other words, a page is the smallest unit from which data is written and data is read. Each page generally includes a user data area D and a redundant area R. The user data area is used to store user data, and the redundant area is used to store system data (for example, the above-mentioned ECC code).

To correspond to the sector size of a disk drive, generally speaking, the user data area D is usually 512 bytes, and the redundancy area R is usually 16 bytes. That is, one page is one sector. However, a plurality of sectors may form one page, for example, one page includes four sectors.

Generally speaking, a block can be composed of any number of pages, such as 64 pages, 128 pages, 256 pages, and so on. The blocks 124 - 0 to 124 -N can also be generally grouped into multiple zones. The zones are used to manage the memory and operate independently of each other to increase the parallelism of operation execution and simplify the management complexity.

The operation of the non-volatile memory will be described in detail below according to the present invention and with reference to the accompanying drawings. It must be understood that the use of words like "extract", "move", "swap" in the following descriptions to manipulate flash memory blocks is a logical concept. That is to say, the actual location of the flash memory block is not changed, but the flash memory block is logically operated.

2A and 2B are detailed block diagrams illustrating the non-volatile memory 124 and its operation according to an embodiment of the present invention.

Please refer to FIG. 2A. In an embodiment of the present invention, in order to efficiently program (ie, write and erase) the nonvolatile memory 124, blocks 124-1 to 124-N of the nonvolatile memory 124 will be It is logically divided into a system area 202, a data area 204 and a spare area 206. Generally speaking, the blocks belonging to the data area 204 in the non-volatile memory 124 account for more than 90%, and the rest are the system area 202 and the spare area 206 .

The blocks in the system area 202 are used to record system data, such as the number of areas of the non-volatile memory 124, the number of blocks in each area, the number of pages in each block, logical-physical mapping tables, etc. .

The blocks in the data area 204 are used to store user data, generally speaking, they are blocks corresponding to logical block addresses operated by the host 100 .

The blocks in the spare area 206 are used to replace the blocks in the data area 204, so the blocks in the spare area 206 are empty or usable blocks, that is, no recorded data or invalid data marked as useless . Specifically, when data is to be written again to an already written data position, an erase operation must be performed first. However, as mentioned above, the writing unit of the flash memory is a page, and the erasing unit is a block. An erasing unit is greater than a writing unit, which means that to perform a block erase operation, the valid pages in the block to be erased must first be copied to other blocks before proceeding. Therefore, when new data is to be written in the block M where the data position has been written in the data area 204, a block C is generally extracted in the spare area 206, and then the valid data in the block M is copied to the spare area 206. After block C and new data is written into block C, block M is erased and moved to the spare area 206 while block C is moved to the data area 204 . It must be understood that moving the block M to the spare area 206 after erasing and moving the block C to the data area 204 is logically associating the block M with the spare area 206 and the block C with the data area 204 . Those skilled in the art can understand that the logical relationship of the blocks in the data area 204 can be maintained by a logical-physical mapping table.

In the embodiment of the present invention, in order to use the nonvolatile memory 124 more efficiently, the blocks 124 - 1 to 124 -N are logically divided into a replacement area 208 and a transient area 210 .

Please refer to FIG. 2B , the replacement area 208 is a block for temporarily storing the block to be replaced in the data area 204 . In more detail, when the block C of the spare area 206 is extracted to replace the block M of the data area 204, new data will be written into the block C in the embodiment of the present invention, but the block C will not be written immediately. Valid data in block M is moved to block C and block M is erased. This is because the valid data in the block M may become invalid in the next operation, so moving the valid data in the block M to the physical block C immediately will cause unnecessary transfer. In the embodiment of the present invention, the block C in which new data is written will be temporarily associated as a replacement area, and multiple physical block addresses corresponding to one In the case of the logical block address, that is, the content of the block M and the block C is integrated to be the content of the corresponding logical block, thereby improving the efficiency of the use of the block. The relationship between these parent and sub-blocks (block M and block C) can be determined according to the size of the buffer memory 122d in the controller 122. In the embodiment of the present invention, five groups are implemented.

The function of the transient area 210 is similar to that of the replacement area 208 . As mentioned above, MLC NAND flash memory is used in the embodiment of the present invention. This MLC NAND flash memory is a multi-layer storage unit, and one page can include 4 sectors, that is, there are 4 sectors of 512 bytes in one page, a total of 2048 bytes. As mentioned above, flash memory is written in page units, so in the case of using MLC NAND flash memory, 4 sectors must be programmed each time, so when writing a small amount of data that is less than one page, it will cause waste of resources. In the embodiment of the present invention, the transient area 210 is used to temporarily store such a small amount of data. Specifically, as mentioned above, when the data of the block C to be written into the replacement area 208 is a small amount of data less than one page, a block T will be extracted from the spare area 206, and then the small amount of data will be written into to block T and associate block T as the transient region 210 . Afterwards, when the amount of data subsequently written is enough to write one page, the data is written into the block C, and then the block T is erased and moved from the transient area 210 to the spare area 206 .

As mentioned above, in order to avoid frequently erasing blocks, block C and block T are used to update the data of block M. However, when the system is storing the blocks M, C, and T during the operation of the nonvolatile memory storage device 120, if an abnormal power failure occurs, the update relationship between the blocks M, C, and T will be changed. will be lost. Specifically, during the operation of the non-volatile memory storage device 120, the instantaneous relationship of the blocks M, C and T will be stored in the buffer memory 122d of the controller 122. When the non-volatile memory storage device 120 is abnormally shut down When the power is turned off, the data in the buffer memory 122d will be lost. Therefore, after the power of the non-volatile memory storage device 120 is restored, although the controller 122 can obtain the information that the blocks M, C, and T map to the same logical block from the re-established logical-physical mapping table, the However, it is impossible to distinguish the update relationship of blocks M, C, and T.

In order to solve the above problems, the present invention marks the information about the update relationship of the block in the redundant area of the page of the block. FIG. 3 is a detailed block diagram illustrating the redundant region R of the page in FIG. 1B according to an embodiment of the present invention.

As mentioned above, the redundant area R is generally 16 bytes, which is divided into 6 bytes 310 for storing system information and 10 bytes 320 for storing error correcting codes. The byte 310 storing system information includes an addressing flag 302 , an update relation flag 304 , a block status flag 306 and other flags 308 .

The address tag 302 includes 3 bytes, wherein 2 bytes are used to mark the area (zone) to which this block belongs, and 1 byte is used to mark the logical block corresponding to this block.

The update relationship flag 304 includes 1 byte, which is used to mark the data update information of the block data in the state where the instantaneous relationship between the blocks M, C and T exists, and the data update information can represent the update of the block Relationships (i.e. new and old relationships).

According to the present invention, when the instantaneous relationship between the blocks M, C and T exists in the system, the memory management module 122a will record data update information in the update relationship flag 304 . The data update information is composed of a plurality of characters having a cyclic relationship, and the number of characters is greater than the number of blocks forming the instant relationship, that is, if there are n blocks forming the instant relationship When there are at least n+1 characters representing data update information. In addition, the data update information recorded in each physical block is recorded sequentially according to the update relationship of the block and the cyclic relationship of characters.

FIG. 4A is a schematic diagram illustrating data update information when one logical block corresponds to three physical blocks according to an embodiment of the present invention.

Please refer to FIG. 4A , the logical block 401 maps to the physical blocks 402 , 403 and 404 . The physical block 402 stores the oldest data, the physical block 403 stores the second-oldest data, and the physical block 404 stores the newest data.

In FIG. 4A, cyclic numbers 0-3 are used as characters representing data update information. Assuming that the update relation of the physical block 402 is marked as 0, when a newer physical block is generated, the update relation of the physical block 403 will be marked as 1 and when an updated physical block 404 is generated, the physical block The update relation of block 404 will be marked as 2. After the non-volatile memory storage device 120 is abnormally powered off, the controller 122 can identify the unused character as 3 according to the data update information, and the next character of character 3 in the cycle of 0-3 is 0, so it has the oldest The block of data is the physical block 402 , and according to this cycle, it is identified that the physical block 403 stores the second oldest data, and the physical block 404 stores the latest data.

FIG. 4B is a schematic diagram illustrating another data update information according to FIG. 4A .

Please refer to FIG. 4B , which also uses cyclic numbers 0-3 as characters representing data update information. Assuming that the update relation of the physical block 402 is marked as 2, when a newer physical block is generated, the update relation of the physical block 403 will be marked as 3 and when an updated physical block 404 is generated, the physical block The update relation of block 404 will be marked as 0. After the non-volatile memory storage device 120 is abnormally powered off, the controller 122 can identify the unused character as 1 according to the data update information, and the next character of character 1 in the cycle of 0-3 is 2, so it has the oldest The block of data is the physical block 402, and according to this, it is cyclically identified that the physical block 403 has the second oldest data, and the physical block 404 is identified that the latest data is stored.

In this embodiment, numbers are used as data to update information. However, the present invention is not limited thereto, and other symbols can also be applied to the present invention, such as using letters with a circular relationship (such as A, B, C, D . . . ).

In this embodiment, the next character of the unused character in the data update information is used as the block with the oldest data. However, in another embodiment of the present invention, the next character of the unused character in the data update information is character as a block with the latest data.

Please refer to FIG. 3 , the block status flag 306 includes 1 byte, which is used to mark whether the block is a normal block or a damaged block.

Other Flags 308 includes 1 byte, which is used to flag other system information.

This embodiment explains the present invention by using a 16-byte redundant area and its byte configuration. However, it must be understood that the present invention is not limited thereto, and redundant regions with other numbers of bytes or other byte configurations are also applicable to the present invention.

FIG. 5 is a flow chart illustrating a data protection method according to the first embodiment of the present invention, which is executed by the memory management module 122a of the controller 122 to re-acquire the above-mentioned instantaneous blocks M, C, and The relationship between T.

Please refer to Figure 5. The data protection method is divided into two parts. In Figure 5 (a), step S501 will generate one-to-many (that is, one logical block corresponds to multiple physical blocks) in each physical area A data update information is recorded in the block. The composition and manner of the data update information have been described in detail above, and will not be repeated here.

In (b) of FIG. 5 , when an abnormal power failure occurs, it is judged whether there are multiple physical blocks whose relationship between old and new cannot be identified in the logical-physical mapping table (step S503 ). If it is determined in step S503 that there is an unidentifiable physical block, then in step S505 the update relation flag is read from the redundant area of the page of the physical block. Afterwards, in step S507, the block with the oldest (or newest) data is determined according to the character of the data update information read from the update relation tag. The manner of determining the block with the oldest (or newest) data is described above in conjunction with FIG. 4A and FIG. 4B , and will not be repeated here. Afterwards, in step S509 , the update relationship of other unidentifiable physical blocks is identified according to the cycle relationship of the data update information.

FIG. 6 is a flowchart illustrating a data protection method according to a second embodiment of the present invention. The hardware structure of the controller implementing the data protection method of the second embodiment is the same as that of the first embodiment, and will not be repeated here.

Please refer to Figure 6. The data protection method is also divided into two parts. In Figure 6 (a), step S601 will write data in the physical block and generate one-to-many at the same time (that is, one logical block corresponds to multiple A piece of data update information is recorded in each physical block. The composition and manner of the data update information have been described in detail above, and will not be repeated here.

In another embodiment of the present invention, the data update information in the physical block can only be written once. That is to say, in the case of a flash memory that can only be programmed once, the data can only be written once, and when it must be reprogrammed, it must be erased before reprogramming.

In (b) of FIG. 6 , when an abnormal power failure occurs, it is determined whether there are multiple physical blocks whose relationship between the old and the new cannot be identified in the logical-physical mapping table (step S603 ). If it is determined in step S603 that there is an unidentifiable physical block, then in step S605 the update relation flag is read from the redundant area of the page of the physical block. Afterwards, in step S607, the block with the oldest (or newest) data is determined according to the number of cyclic characters of the data update information read from the update relation tag, for example, the number of cyclic characters is between 3-5. The manner of determining the block with the oldest (or newest) data has been described above with reference to FIG. 4A and FIG. 4B , and will not be repeated here. Afterwards, in step S609, the update relationship of other unidentifiable physical blocks is identified according to the cycle character of the data update information.

The data protection method proposed by the present invention is suitable for non-volatile memory, so the data protection method proposed by the present invention can be applied to various devices using non-volatile memory as storage media. For example, the SD card 704a, the MMC card 704b, the CF card 704c, the memory stick (memory stick) 704d and the solid state hard drive 706 etc. used by the USB flash disk 702 shown in Figure 7, digital camera (video camera) 704.

To sum up, the data protection method for non-volatile memory proposed by the present invention can effectively obtain the update relationship of one-to-many blocks after abnormal power failure. Thus, data loss after an abnormal power failure is avoided.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the invention should be based on the claims of the present invention.

Claims (14)

1. A data protection method, which is applicable to a plurality of physical blocks mapped to a logical block in a nonvolatile memory, the data protection method comprising: Recording a piece of data update information in each of the physical blocks, the data update information is used to identify the update relationship of data in the physical block; judging whether there is a physical block whose old-new relationship cannot be identified among the physical blocks; and When it is judged that there is a physical block whose old-new relationship cannot be identified, the update relationship of the physical block whose old-new relationship cannot be identified is obtained according to the data update information, Wherein the data update information is composed of a plurality of characters having a cyclic relationship, and the number of the characters is greater than the number of the physical blocks, The data update information recorded in each of the physical blocks is recorded sequentially according to the update relationship and the cycle relationship. 2. The data protection method according to claim 1, wherein the characters are a plurality of numbers or a plurality of characters. 3. The data protection method according to claim 1, wherein obtaining the update relationship comprises identifying the physical block containing the data update information of the next character with the next character of the unused character according to the cyclic relationship is the physical block with the oldest data, and sequentially identify the update relationship of the other physical blocks according to the cycle relationship. 4. The data protection method according to claim 1, wherein obtaining the update relationship comprises identifying the physical block containing the data update information of the next character with the next character of the unused character according to the cyclic relationship It is the physical block with the latest data, and the updating relationship of the other physical blocks is sequentially identified according to the cyclic relationship. 5. The data protection method according to claim 1, wherein recording the data update information in each of the physical blocks is recording the data update information in a redundant area of each of the physical blocks. 6. The data protection method as claimed in claim 1, wherein the non-volatile memory is a flash memory whose page can only be programmed once. 7. The data protection method as claimed in claim 6, wherein the flash memory is an SLC and non-flash memory or an MLC and non-flash memory. 8. A data protection device, which is applicable to a plurality of physical blocks corresponding to a logical block in a non-volatile memory, the data protection device comprising: A module, which records a data update information in each of the physical blocks, and the data update information is used to identify the update relationship of the data in the physical blocks; B module, which judges whether there is a physical block that cannot identify the old and new relationship among the physical blocks; and C module, which obtains the update relationship of the physical block whose new-old relationship cannot be identified according to the data update information when the B module judges that there is a physical block whose new-old relationship cannot be identified, Wherein the data update information is composed of a plurality of characters having a cyclic relationship, and the number of the characters is greater than the number of the physical blocks, The A modules recording the data update information in each of the physical blocks are recorded sequentially according to the update relationship and the cycle relationship. 9. The data protection device according to claim 8, wherein the characters are a plurality of numbers or a plurality of letters. 10. The data protection device as claimed in claim 8, wherein the C module for obtaining the update relationship identifies the physical address of the data update information containing the next character with the next character of the unused character according to the cyclic relationship. The block is the physical block with the oldest data, and the updating relationship of other said physical blocks is sequentially identified according to the circular relationship. 11. The data protection device as claimed in claim 8, wherein the C module for obtaining the update relation identifies the physical character of the data update information comprising the next character with the next character of the unused character according to the cyclic relation. A block is a physical block with the latest data, and the updating relationship of other said physical blocks is sequentially identified according to the cyclic relationship. 12. The data protection device as claimed in claim 8, wherein the A module that records the data update information in each of the physical blocks records the data update information in a redundant area of each of the physical blocks . 13. The data protection device as claimed in claim 8, wherein the non-volatile memory is a flash memory whose page can only be programmed once. 14. The data protection device of claim 13, wherein the flash memory is an SLC and non-flash memory or an MLC and non-flash memory.

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