CN101026335B - Control circuit for power supply device, power supply device, and control method thereof - Google Patents

Abstract

The present invention provides a control circuit for a power supply device, a power supply device and a control method thereof, in which output voltages to be supplied to various devices are determined and set to optimum levels at high speed and efficiently. A control circuit (10A) in the power supply unit supplies a desired voltage level ranging from V1 to V3 to a device (60) which provides an initial voltage and then requires to receive the desired voltage level. The control circuit (10A) includes a communication unit (21) for receiving a desired level such as V1, and a communication unit including REG1 to REG3 for storing in advance an initial set level for determining an initial voltage and a communication unit ( 21) Storage unit (22) of the received request level. The initial or desired voltage ranging from V1 to V3 may be controlled in response to an initial set level or desired level.

Description

Power supply device control circuit, power supply device and control method thereof

technical field

The present invention relates to a control circuit for a power supply device, a power supply, and a method for controlling the power supply.

Background technique

Since integrated circuits such as LSIs or ICs generally vary in manufacturing process, their transistors may not have uniform threshold voltage levels or resistance levels. Also, the threshold voltage level or resistance level of transistors of such an integrated circuit may vary depending on usage conditions (including ambient temperature). In the event that the threshold voltage levels or resistance levels of the transistors are inconsistent, the delay time of the integrated circuit will therefore be different, and thus the operating speed will also be different. In order to eliminate any significant variation in operating speed, power supply means are provided for applying an optimum voltage to the integrated circuit in relation to the threshold voltage level or resistance level.

An electronic device and an integrated circuit controlled by a power supply unit are disclosed in Japanese Unexamined Patent Publication Nos. 2000-228833 and 2001-332695, respectively. The electronic device disclosed in Publication No. 2000-228833 is configured to charge its associated battery by an external power source and discharge it for operating system components. Specifically, the output of its power supply device (power supply) is controlled so that the sum of the operating power of the system components and the charging of the battery is kept substantially constant. The electronics allow a controller of the power supply unit to monitor the output (current) of the power supply unit and control power supplied to system components and charging of associated batteries to minimize power consumption.

The integrated circuit disclosed in No. 2001-332695 includes a first logic gate and a second logic gate, the first logic gate is powered by a first group of potentials with a smaller potential difference, and the second logic gate is powered by a group of potentials with a larger potential difference The second set of potentials supplies power, while the reference potential at the MIS transistor is shared by the first logic gate and the second logic gate. The integrated circuit causes the voltage output magnitude of the MIS transistor in the second logic gate to become greater than the voltage output magnitude of the MIS transistor in the first logic gate, thereby operating the second logic gate at a higher speed than the first logic gate . Moreover, since the power consumption of each logic gate in the integrated circuit is proportional to the square of the voltage output amplitude of the MIS transistor, the voltage output amplitude of the MIS transistor in the first logic gate is set to be smaller than that in the second logic gate The voltage output amplitude of the MIS transistor, so that the first logic gate can be operated with lower power consumption than the second logic gate.

Contents of the invention

The power supply unit is connected to various devices including the above-mentioned integrated circuits. Therefore, it is necessary to modify the output voltage of the power supply unit to its optimum level to match the connected equipment, while preventing the operating speed of the integrated circuit from being significantly different due to any difference in transistor threshold voltage level or resistance level.

However, the voltage output of the power supply unit has to be adjusted to an optimal level every time the power supply unit is started up. As the voltage output is modified from its fixed initial set value to an optimal level that differs for each device, the time required for its modification will be significantly extended. In other words, it is difficult to modify the voltage output to its optimal level at high speed.

Also, the power supply device allows its voltage output to be modified from a fixed initial setting value to an optimal level according to each type of connected equipment, so its setting action will be very inefficient.

The present invention is designed in consideration of the above disadvantages, and an object thereof is to provide a control circuit for a power supply device, a power supply device and a control method thereof, in which voltage output devices to be supplied to various devices can be quickly and efficiently set to the optimum level.

The control circuit for the power supply device of the first technical solution of the present invention, and the power supply device for supplying the required voltage to the equipment that provides the initial voltage and then requires to receive the required voltage different from the initial voltage according to the second technical solution of the present invention include : a communication unit for receiving a required level of a required voltage; and a storage unit for pre-storing an initial set level for determining an initial voltage and storing the required level received by the communication unit, wherein in response to the initial setting Set level or required level to control initial voltage or desired voltage.

The control circuit for a power supply device according to the first technical aspect of the present invention, and the power supply device according to the second technical aspect of the present invention include a communication unit for receiving a required level of a required voltage, and a device for pre-storing The initially set level and the storage unit storing the required level received by the communication unit, wherein the initial voltage or the required voltage is controlled in response to the initially set level or the required level. As a result, compared with the case where the voltage is adjusted to the optimum level for the equipment each time the power supply unit is started, the voltage is directly set to the level required by the connected equipment in response to the required level stored in the storage unit. The time required for the optimum level can be made shorter. In other words, the voltage to be supplied to the device can be set to an optimum level efficiently and at high speed.

The power supply device control method of the third technical aspect of the present invention is for supplying a required voltage to a device that supplies an initial voltage and then requires receiving a required voltage different from the initial voltage, the method comprising the steps of: receiving a required level of the required voltage; storing in advance an initial set level for determining the initial voltage, and storing the received requested level; and controlling the initial voltage or the requested voltage in response to the initially set level or the requested level.

The power supply device control method of the third technical aspect of the present invention includes the steps of: receiving a required level of a required voltage; storing in advance an initial set level for determining an initial voltage, and storing the received required level; and responding The initial voltage or the required voltage is controlled at the initial set level or the required level. As a result, the voltage is directly set to the optimum level required by the connected equipment in response to the stored demand level, compared to the case where the voltage is adjusted to the optimum level for the equipment each time the power supply unit is started. The time required for leveling can be shortened. In other words, the voltage to be supplied to the device can be set to an optimum level efficiently and at high speed.

Description of drawings

The above and other objects and novel features of the present invention will appear more fully from the following detailed description when read in conjunction with the accompanying drawings. However, it should be clearly understood that the drawings are for illustrative purposes only, and are not intended to define limitations of the present invention.

FIG. 1 is a block diagram showing a connection between a power supply unit and electronic equipment according to a first embodiment of the present invention;

2 is a circuit diagram of a power supply unit connected to an electronic device;

Fig. 3 is a schematic diagram of electronic equipment connected to a power supply unit.

Detailed ways

(Example)

An embodiment of the present invention will be described below with reference to FIGS. 1 to 3 . As shown in FIG. 1, the power supply device 10 of this embodiment is connected to an electronic device 60 (external device) through an IIC bus IIC (communication device). The IIC bus IIC is used to exchange various data between the power supply device 10 and the electronic device 60 . As shown, the power supply unit 10 has three (CH-1 to CH-3) channel outputs. Electronic device 60 includes one or more integrated circuits.

As shown in FIG. 2 , the power supply device 10 includes a communication controller 20 , and first to third DC-DC converters 30 to 50 . The communication controller 20 includes an interface controller 21, a flash memory 22, a data processor 23 (such as an MPU), and three registers REG1 to REG3. 10A in the figure shows the control circuit of the power supply device 10 .

The interface controller 21 is connected to the IIC bus IIC. As can be seen from FIGS. 2 and 3 , the IIC bus IIC is connected to the interface controller 61 of the electronic device 60 . As shown in FIG. 3 , the electronic device 60 includes a ring oscillator RINGOSC and an oscillator OSC4 . The ring oscillator RINGOSC and the oscillator OSC4 are connected to a phase-locked loop circuit PLL. A phase-locked loop circuit PLL is connected to the frequency/voltage converter 63 . The frequency/voltage converter 63 is then connected to the interface controller 61 .

As shown in FIG. 2 , the registers REG1 , REG2 and REG3 and the data processor 23 are connected in parallel with the interface controller 21 . The flash memory 22 is connected to a data processor 23, which in turn is connected in parallel to registers REG1, REG2 and REG3.

The register REG1 is connected to the D/A converter DAC1 of the first DC-DC converter 30 as shown. The register REG2 is connected to the D/A converter DAC2 of the second DC-DC converter 40 . The register REG3 is connected to the D/A converter DAC3 of the third DC-DC converter 50 .

As shown in the figure, the first DC-DC converter 30 includes a main switching transistor FET1, a synchronous side switching transistor FET2, a choke coil L1 and a capacitor C1. The drain of the main switching transistor FET1 is connected to the input terminal (IN1) for receiving the DC input voltage VIN. As shown in FIG. 3 , the DC input voltage VIN is applied to both the main switching transistor FET1 and the communication controller 20 via the input terminal ( IN4 ). The source of the main switching transistor FET1 is connected to the drain of the sync side switching transistor FET2. The source of the sync-side switching transistor FET2 is connected to ground. Also, the source of the main switching transistor FET1 and the drain of the synchronous side switching transistor FET2 are connected to the choke coil L1. The choke coil L1 is connected to the output terminal (OUT1). The capacitor C1 is connected between the output terminal (OUT1) and ground. The output terminal ( OUT1 ) is connected to the electronic device 60 .

The first DC-DC converter 30 also includes an error amplifier ERA1, a D/A converter DAC1, a triangle wave oscillator OSC1, and a PWM comparator PWM1. The inverting input terminal of the error amplifier ERA1 is connected to the output terminal (OUT1). The non-inverting input terminal of the error amplifier ERA1 is connected to the D/A converter DAC1.

The triangular wave oscillator OSC1 outputs a triangular wave signal. The triangular wave signal oscillates within a range of voltage amplitudes (eg, between 1.0V and 2.0V). The triangle wave oscillator OSC1 may include an OP amplifier, resistors, capacitors, and the like.

The PWM comparator PWM1 has a positive input terminal (+) and a negative input terminal (−). The positive input (+) is connected to the output (N1) of the error amplifier ERA1, and the negative input (-) is connected to the triangle wave oscillator OSC1. The output terminal (Q1) of the PWM comparator PWM1 is connected to the gate of the main switching transistor FET1, and the inverting output terminal (*Q1) of the PWM comparator PWM1 is connected to the gate of the synchronous side switching transistor FET2.

The second DC-DC converter 40 is basically the same as the first DC-DC converter 30 in structure. More specifically, the error amplifier ERA2, D/A converter DAC2, triangle wave oscillator OSC2, PWM comparator PWM2, main switching transistor FET3, synchronous side switching transistor FET4, choke coil L2, and capacitor C2 can be used to replace the error Amplifier ERA1, D/A converter DAC1, triangular wave oscillator OSC1, PWM comparator PWM1, main switching transistor FET1, synchronous side switching transistor FET2, choke coil L1 and capacitor C1, thereby constructing the second DC- DC converter 40 . The triangular wave oscillator OSC2, like the triangular wave oscillator OSC1, outputs a triangular wave signal oscillating within a voltage amplitude range (eg, between 1.0V and 2.0V).

N2 , IN2 and OUT2 represent the output terminal of the error amplifier ERA2 , the input terminal of the second DC-DC converter 40 and the output terminal of the second DC-DC converter 40 , respectively. The output terminal and the inverting output terminal of the PWM comparator PWM2 are represented by Q2 and *Q2 respectively. The output terminal OUT2 is connected to the electronic device 60 .

The third DC-DC converter 50 includes an NMOS transistor FET5, an NMOS transistor FET6, a choke coil L3, and a capacitor C3. As shown in the figure, the drain of the NMOS transistor FET5 is connected to the input terminal IN3 for receiving the DC input voltage VIN. The source of the NMOS transistor FET5 is connected to a choke coil L3 which in turn is connected to ground.

The source of the NMOS transistor FET5 is connected to the drain of the NMOS transistor FET6. Also, the source of the NMOS transistor FET6 is connected to the output terminal OUT3. Capacitor C3 is connected between output terminal OUT3 and ground. The output terminal OUT3 is connected to the electronic device 60 .

The third DC-DC converter 50 includes an error amplifier ERA3, a D/A converter DAC3, a triangle wave oscillator OSC3 and a PWM comparator PWM3. The inverting input terminal of the error amplifier ERA3 is connected to the output terminal OUT3. The non-inverting input terminal of the error amplifier ERA3 is connected to the D/A converter DAC3. The triangular wave oscillator OSC3 outputs a triangular wave signal similarly to the triangular wave oscillators OSC1 and OSC2 .

The positive input terminal (+) of the PWM comparator PWM3 is connected to the output terminal N3 of the error amplifier ERA3, and the negative input terminal (-) thereof is connected to the triangular wave oscillator OSC3. The output terminal Q3 of the PWM comparator PWM3 is connected to the gate of the NMOS transistor FET5. The inverting output terminal *Q3 of the PWM comparator PWM3 is connected to the gate of the NMOS transistor FET6.

A control method of the power supply device 10 is now described. When the power supply device 10 shown in FIG. 2 is powered on, its interface controller 21 outputs a reset signal S1 to the data processor 23 . When receiving the reset signal S1, the data processor 23 accesses the flash memory 22 to read initial data. This initial data is used to set the voltage V1 to be supplied to the electronic circuit connected to the output terminal OUT1 of the first DC-DC converter 30 to the initial level pre-stored in the non-volatile mode in the flash memory 22. device60. More specifically, the initial voltage is set to a rated level (for example, 5V) of the electronic device 60 corresponding to the initial setting level of the present invention. The data processor 23 outputs the voltage command signal S2 corresponding to the initial data to the register REG1. Since the flash memory 22 stores initial data (initial setting level) in a nonvolatile mode, it corresponds to a nonvolatile storage device (memory) of the present invention. The initial setting level is not limited to the rated level (5V) of the electronic device 60, but can be selected from the allowable range of the rated voltage (for example, from 4.5V to 5.5V).

The register REG1 stores the voltage command signal S2 and then outputs the signal S2 to the D/A converter DAC1 of the first DC-DC converter 30 . When the power supply device 10 is powered on, the register REG1 stores the initial data (initial setting level) of the voltage command signal S2 in a volatile mode, and corresponds to the register unit (volatile storage unit) of the present invention.

The D/A converter DAC1 generates an analog voltage signal (reference voltage) from the voltage command signal S2, which is then received by the non-inverting input terminal of the error amplifier ERA1. As shown, voltage V1 is fed back to the inverting input of error amplifier ERA1. The error amplifier ERA1 compares the feedback voltage V1 with the reference voltage to output an error output voltage to the positive input terminal (+) of the PWM comparator PWM1.

The negative input terminal (-) of the PWM comparator PWM1 receives the triangular wave signal from the triangular wave oscillator OSC1. The PWM comparator PWM1 compares the voltage of the triangular wave signal with the error output voltage from the error amplifier ERA1.

When the error output voltage is greater than the voltage of the triangular wave signal, the PWM comparator PWM1 outputs a high-level PWM signal from the output terminal Q1. At the same time, the PWM comparator PWM1 outputs a low-level PWM signal from the output terminal *Q1. When the error output voltage is less than the voltage of the triangular wave signal, the PWM comparator PWM1 outputs a low-level PWM signal from the output terminal Q1. At the same time, the PWM comparator PWM1 outputs a high-level PWM signal from the output terminal *Q1.

A PWM signal is input to the gate of the main switching transistor FET1. The main switching transistor FET1 is turned on when the PWM signal is at a high level, and is turned off at a low level. An inverted PWM signal is input to the gate of the sync-side switching transistor FET2. The switching transistor FET2 on the synchronous side is cut off when the inverting PWM signal is at a low level, and is turned on at a high level. By repeating the change of the PWM signal between high level and low level and the change of the inverse PWM signal between low level and high level, the voltage V1 is adjusted to the initial level (5V in this embodiment), It is then supplied to the electronic device 60 via the output terminal OUT1. Since the first DC-DC converter 30 compares the feedback voltage V1 with an analog signal (reference voltage) converted from the voltage command signal S2 and adjusts the voltage V1 to an initial setting by turning on and off the two switching transistors FET1 and FET2 fixed value, so it corresponds to the voltage controller of the present invention.

Integrated circuits in electronic device 60 may vary in threshold voltage or resistance level of transistors. Therefore, the optimal level of integrated circuit voltage may be inconsistent depending on threshold voltage or resistance level, etc. In order to obtain the optimum level of the voltage V1 (for example, 4.8V corresponding to the required level of the required voltage of the present invention), the electronic device 60 outputs the voltage adjustment signal S14 (see FIG. 3 ) to the interface controller 21, which will be described below.

As shown in FIG. 3 , the phase locked loop circuit PLL receives the frequency signal S11 from the ring oscillator RINGOSC and the reference frequency signal S12 from the oscillator OSC4 . For example, the ring oscillator RINGOSC includes a loop in which a set of inverters can be connected in an odd number of stages. The period of the frequency signal S11 is determined by the product of the odd number of stages of the inverter and the delay time of the inverter. This delay time differs depending on the threshold voltage, resistance level, or the like. Therefore, the cycle of the frequency signal S11 differs depending on the threshold voltage, resistance level, or the like. The phase locked loop circuit PLL compares the frequency signal S11 with the reference frequency signal S12 to output an output signal S13. The output signal S13 represents the difference between the frequency signal S11 and the reference frequency signal S12. The output signal S13 is then input to the frequency/voltage converter 63 . The frequency/voltage converter 63 outputs the voltage adjustment signal S14 converted from the output signal S13. If necessary, the voltage adjustment signal S14 is transmitted from the interface controller 61 to the interface controller 21 in the power supply device 10 via the IIC bus IIC. The voltage adjustment signal S14 adjusts the voltage V1 to eliminate the difference between the frequency signal S11 and the reference frequency signal S12. This makes it possible for the first DC-DC converter 30 to supply the electronic device 60 with the optimum level (4.8V) of the voltage V1. Since the interface controller 21 receives the voltage adjustment signal S14 for adjusting the voltage V1 to an optimum level, it corresponds to the communication unit of the present invention.

As shown in FIG. 2 , the interface controller 21 outputs the voltage adjustment signal S14 to the register REG1 and the data processor 23 . The register REG1 stores the voltage adjustment signal S14 instead of the voltage command signal S2 , and then outputs the voltage adjustment signal S14 to the converter DAC1 of the first DC-DC converter 30 . Since the register REG1 stores the voltage adjustment signal S14 received by the interface controller 21 in a volatile mode when the voltage V1 is supplied from the power supply device 10 to the electronic device 60 , it corresponds to the register unit of the present invention. The data processor 23 writes the voltage adjustment data (received voltage level) corresponding to the voltage adjustment signal S14 in the flash memory 22, which replaces the initial data (initial setting level). Since the flash memory 22 stores the voltage adjustment data (received voltage level) of the voltage adjustment signal S14 received at the interface controller 21 and written by the data processor 23, it corresponds to the storage unit of the present invention.

The D/A converter DAC1 outputs an analog voltage signal (reference voltage) corresponding to the voltage adjustment signal S14 to the non-inverting input terminal of the error amplifier ERA1. It can be seen from FIG. 2 that the error amplifier ERA1 compares the feedback voltage V1 with the reference voltage to output the error output voltage to the positive input terminal (+) of the PWM comparator PWM1.

Similar to the above control method, the PWM comparator PWM1 outputs the PWM signal and the inverted PWM signal to the gate of the main switching transistor FET1 and the gate of the synchronous side switching transistor FET2 respectively. Similar to the above-mentioned control method, the PWM signal repeatedly changes between high level and low level, and at the same time, the inverted PWM signal repeatedly changes between low level and high level, so that the voltage supplied to the electronic device 60 via the output terminal OUT1 can be The voltage V1 is controlled at the optimum level (4.8V). Since the first DC-DC converter 30 compares the feedback voltage V1 with an analog signal (reference voltage) corresponding to the voltage adjustment signal S14, and adjusts the voltage V1 to an optimum level by turning on and off the two transistors FET1 and FET2 , so it corresponds to the voltage controller of the present invention.

Upon receiving the reset signal S1, the data processor 23 accesses the flash memory 22 to read the initial data of the voltage V2. Then, the data processor 23 outputs the voltage command signal S3 to the register REG2. The voltage command signal S3 is used to adjust the voltage V2 supplied to the electronic device 60 connected to the output terminal OUT2 of the second DC-DC converter 40 to an initially set level. In this embodiment, the initial setting level is equal to the rated voltage of the electronic device 60 (for example, 2.5V).

The register REG2 stores the voltage command signal S3 and outputs the signal S3 to the D/A converter DAC2 of the second DC-DC converter 40 . Since the register REG2 stores the voltage command signal S3 corresponding to initial data (initial setting level) in a volatile mode, it corresponds to the register unit (volatile memory means) of the present invention.

The D/A converter DAC2 outputs an analog voltage signal (reference voltage) corresponding to the voltage command signal S3 to the non-inverting input terminal of the error amplifier ERA2. As shown, voltage V2 is fed back to the inverting input of error amplifier ERA2. The error amplifier ERA2 compares the feedback voltage V2 with the reference voltage to output an error output voltage to the positive input terminal (+) of the PWM comparator PWM2.

The triangular wave signal is input to the negative input terminal (-) of the PWM comparator PWM2 by the triangular wave oscillator OSC2. Similar to the aforementioned PWM comparator PWM1, the PWM comparator PWM2 outputs the PWM signal and the inverted PWM signal to the gate of the main switching transistor FET3 and the gate of the synchronous side switching transistor FET4, respectively. The voltage V2 is adjusted to the initial level ( 2.5 V in this embodiment), which is then supplied to the electronic device 60 via the output terminal OUT2. Since the second DC-DC converter 40 compares the feedback voltage V2 with an analog signal (reference voltage) corresponding to the voltage command signal S3 and adjusts the voltage V2 to an initial setting by turning on and off the two switching transistors FET3 and FET4 value, so it represents the voltage controller unit of the present invention.

However, the voltage V2 to be supplied to the electronic device 60 by the second DC-DC converter 40 may differ depending on a threshold voltage or a resistance level, etc., and is not at an optimum level (for example, 2.7V). In this unfavorable situation, similar to the method shown in FIG. 3 , the electronic device 60 outputs the voltage adjustment signal S15 (see FIG. 2 ) to the interface controller 21 along the IIC bus IIC. The voltage adjustment signal S15 is used to instruct the second DC-DC converter 40 to supply the electronic device 60 with an optimal level of the voltage V2 (2.7V in this embodiment).

Then, the interface controller 21 outputs the voltage adjustment signal S15 to the register REG2 and the data processor 23 . The register REG2 stores the voltage adjustment signal S15 instead of the voltage command signal S3 , and outputs the signal S15 to the D/A converter DAC2 of the second DC-DC converter 40 . Since the register REG2 stores the voltage adjustment signal S15 received by the interface controller 21 in a volatile mode when the power supply device 10 supplies the voltage V2 to the electronic device 60 , it corresponds to the register unit of the present invention. On the other hand, the data processor 23 writes the data (received voltage level) of the voltage adjustment signal S15 in the flash memory 22 instead of the initial data (initial setting level).

The D/A converter DAC2 outputs an analog voltage signal (reference voltage) corresponding to the voltage adjustment signal S15 to the non-inverting input terminal of the error amplifier ERA2. The error amplifier ERA2 compares the feedback voltage V2 with the reference voltage to output an error output voltage to the positive input terminal (+) of the PWM comparator PWM2.

The triangular wave signal is input to the negative input terminal (-) of the PWM comparator PWM2 by the triangular wave oscillator OSC2. The PWM comparator PWM2 outputs the PWM signal and the inverted PWM signal to the gate of the main switching transistor FET3 and the gate of the synchronous side switching transistor FET4, respectively. Similar to the above-mentioned control method, the PWM signal repeatedly changes between high level and low level, and at the same time, the inverted PWM signal repeatedly changes between low level and high level, so that the voltage supplied to the electronic device 60 via the output terminal OUT2 can be The voltage V2 is controlled at the optimum level (2.7V). Since the second DC-DC converter 40 compares the feedback voltage V2 with an analog signal (reference voltage) corresponding to the voltage adjustment signal S15, and adjusts the voltage V2 to an optimum level by turning on and off the two transistors FET3 and FET4 , which therefore corresponds to the voltage controller unit of the present invention.

Upon receiving the reset signal S1, the data processor 23 accesses the flash memory 22 to read the initial data of the negative voltage V3. Then, the data processor 23 outputs the voltage command signal S4 to the register REG3. The voltage command signal S4 is used to adjust the negative voltage V3 supplied to the electronic device 60 connected to the output terminal OUT3 of the third DC-DC converter 50 to an initially set level. In this embodiment, the initial setting level is equal to the rated voltage of the electronic device 60 (eg -2.5V).

The register REG3 stores the voltage command signal S4 and outputs the signal S4 to the D/A converter DAC3 of the third DC-DC converter 50 . Since the register REG3 stores the voltage command signal S4 corresponding to initial data (initial setting level) in a volatile mode, it corresponds to the register unit (volatile memory unit) of the present invention.

The D/A converter DAC3 outputs an analog voltage signal (reference voltage) corresponding to the voltage command signal S4 to the non-inverting input terminal of the error amplifier ERA3. As shown, voltage V3 is fed back to the inverting input of error amplifier ERA3. The error amplifier ERA3 compares the feedback voltage V3 with the reference voltage to output an error output voltage to the positive input terminal (+) of the PWM comparator PWM3.

The triangular wave signal is input to the negative input terminal (-) of the PWM comparator PWM3 by the triangular wave oscillator OSC3. Similar to the aforementioned PWM comparator PWM1 or PWM2, the PWM comparator PWM3 outputs the PWM signal and the inverted PWM signal to the gate of the NMOS transistor FET5 and the gate of the NMOS transistor FET6, respectively. By repeating the change of the PWM signal between high level and low level and the change of the inverse PWM signal between low level and high level, the voltage V3 is adjusted to the initial level (-2.5V in this embodiment ), and supply it to the electronic device 60 via the output terminal OUT3. Since the third DC-DC converter 50 compares the feedback voltage V3 with an analog signal (reference voltage) corresponding to the voltage command signal S4 and adjusts the voltage V3 to an initial setting by turning on and off the two switching transistors FET5 and FET6 value, so it represents the voltage controller unit of the present invention.

When the voltage V3 supplied from the third DC-DC converter 50 to the electronic device 60 is not at the optimal level (eg -2.9V) but at another level (-2.5V), the method shown in FIG. 3 Similarly, the electronic device 60 outputs the voltage adjustment signal S16 (see FIG. 2 ) to the interface controller 21 along the IIC bus IIC. The voltage regulation signal S16 is used to instruct the third DC-DC converter 50 to supply the electronic device 60 with an optimum level of the voltage V3 (-2.9V).

The interface controller 21 outputs the voltage adjustment signal S16 to the register REG3 and the data processor 23 . The register REG3 stores the voltage adjustment signal S16 instead of the voltage command signal S4 and outputs the signal S16 to the D/A converter DAC3 of the third DC-DC converter 50 . Since the register REG3 stores the voltage adjustment signal S16 received by the interface controller 21 in a volatile mode when the power supply device 10 supplies the voltage V3 to the electronic device 60 , it corresponds to the register unit of the present invention. On the other hand, the data processor 23 writes the data (received voltage level) of the voltage adjustment signal S16 in the flash memory 22 instead of the initial data (initial setting level).

The D/A converter DAC3 outputs an analog voltage signal (reference voltage) corresponding to the voltage adjustment signal S16 to the non-inverting input terminal of the error amplifier ERA3. The error amplifier ERA3 compares the feedback voltage V3 with the reference voltage to output an error output voltage to the positive input terminal (+) of the PWM comparator PWM3.

The PWM comparator PWM3 outputs the PWM signal and the inverted PWM signal to the gate of the NMOS transistor FET5 and the gate of the NMOS transistor FET6, respectively. Similar to the above-mentioned control method, the PWM signal repeatedly changes between high level and low level, and at the same time, the inverted PWM signal repeatedly changes between low level and high level, so that the voltage supplied to the electronic device 60 via the output terminal OUT3 can be The voltage V3 is controlled at the optimum level (-2.9V). Since the third DC-DC converter 50 compares the feedback voltage V3 with an analog signal (reference voltage) corresponding to the voltage adjustment signal S16, and adjusts the voltage V3 to the optimum voltage by turning on and off the two NMOS transistors FET5 and FET6 level, so it corresponds to the voltage controller unit of the present invention.

The power supply device 10 of the present embodiment allows data (received voltage levels) of the voltage adjustment signals S14 to S16 to remain stored in the flash memory 22 (nonvolatile memory unit) even if the power supply is interrupted. When the power supply device 10 is turned on while data (received voltage levels) of the voltage adjustment signals S14 to S16 remain stored in the flash memory 22, its first to third DC-DC converters 30, 40, and 50 are activated , the voltages V1 , V2 and V3 are determined in response to comparing the voltages V1 , V2 and V3 with their respective corresponding signals S14 , S15 and S16 (received voltage levels). When any of the voltages V1, V2, and V3 is not at the optimum level set for the electronic device 60, the power supply device 10 responds to a voltage adjustment signal (received voltage level) received from the electronic device 60 by reducing the voltage to V1, V2 or V3 is controlled to its optimum level.

(Effect of the embodiment)

The control circuit 10A for a power supply device and the power supply device 10 in the embodiment enable the interface controller 21 to receive the voltage adjustment signals S14 to S16, and enable the flash memory 22 to store in advance the initial levels for determining the initial levels of the voltages V1 to V3 The data (initially set level) and the optimum level of the voltage of the electronic device 60 corresponding to the voltage adjustment signals S14 to S16, so that the voltages V1 to V3 respond to the data (initially set level) and the optimum level It is supplied to the electronic device 60 after being modified to optimize the level. Therefore, when the power supply device 10 is turned on, its voltages V1 to V3 are set to initial levels determined by the initial set levels stored in the flash memory 22, and the optimum level for the electronic device 60 can be used stored in flash memory 22. When the power supply unit 10 is turned on again after the interruption, its voltages V1 to V3 can be easily set to its electronic equipment 60 in response to the optimum set level (initial set level) stored in the flash memory 22. optimal level required. As a result, compared to the case where the voltages V1 to V3 are adjusted every time the power supply device 10 is activated to supply power to the electronic device 60, the power supply device 10 adjusts the voltage V1 to V3 in response to the optimum set level stored in the flash memory 22. The time required for V3 to be set to the optimum set level for the electronic device 60 can become shorter, allowing the voltages V1 to V3 to be set to the optimum level at high speed and efficiently.

Similarly, the control method of the power supply device 10 of this embodiment makes it possible to store in advance initial data (initial setting levels) for determining the initial levels of the voltages V1 to V3 when the voltage adjustment signals S14 to S16 have been received , and can store the optimum level of the voltage for the electronic device 60 determined by the voltage adjustment signals S14 to S16, so that the voltages V1 to V3 are adjusted in response to the data (initially set level) and the optimum level After being modified, it is supplied to the electronic device 60 . Therefore, when the power supply device 10 is turned on, its voltages V1 to V3 are set to initial levels determined by the initial setting levels, and optimum levels for the electronic device 60 can be stored. In the control method of the power supply device 10, when the power supply device 10 is turned on again after being interrupted, its voltages V1 to V3 can be easily set in response to the optimal setting levels (initial setting levels) stored in advance. Set to the optimal level required by its electronic equipment 60. As a result, compared to the case where the voltages V1 to V3 are adjusted each time the power supply apparatus 10 is activated to supply power to the electronic equipment 60, the power supply apparatus 10 sets the voltages V1 to V3 to the desired level in response to the optimal setting level. The time required for the optimum setting level of the electronic device 60 can become shorter, allowing high-speed and efficient setting of the voltages V1 to V3 to the optimum level.

Moreover, the control circuit 10A for the power supply unit and the power supply unit 10 in the embodiment enable the flash memory 22 and the registers REG1 to REG3 to operate as follows: When the power supply unit 10 is turned on, the registers REG1 to REG3 save the data processor 23 from the flash memory. 22, and when the power supply device 10 supplies a voltage such as V1 to the electronic device 60, save the maximum voltage for the electronic device 60 determined by the voltage adjustment signals S14 to S16. optimal voltage level. Therefore, when the power supply device 10 is turned on, a voltage such as V1 of the power supply device 10 is set to its initial setting level with reference to the initial data (initial setting level) held in the registers REG1 to REG3. When the power supply unit 10 supplies a voltage such as V1 to the electronic device 60, the voltage such as V1 of the power supply unit 10 is set to its optimum level with reference to the optimum levels held in the registers REG1 to REG3.

Similarly, the power supply device control method in the embodiment is such that when the power supply device 10 is turned on, the initial data (initial setting level) stored in the nonvolatile mode can be read out and stored in the volatile mode, and when When the power supply device 10 supplies a voltage such as V1 to the electronic device 60 , the optimum voltage level for the electronic device 60 determined by the voltage adjustment signals S14 to S16 can be stored in a volatile mode. Therefore, when the power supply device 10 is turned on, a voltage such as V1 of the power supply device 10 is set to its initial setting level with reference to the initial data (initial setting level) saved in the volatile mode. When the power supply unit 10 supplies a voltage such as V1 to the electronic device 60, the voltage such as V1 of the power supply unit 10 is set to its optimum level with reference to the optimum level stored in the volatile mode.

Also, the control circuit 10A for a power supply device and the power supply device 10 in the embodiment make it possible for the first to third DC-DC converters 30 to 50 to supply the electronic equipment 60 in response to the initial data stored in the registers REG1 to REG3 (initial setting level) or the optimal level and modified voltage V1 to V3. Therefore, it is not necessary to individually adjust the voltages V1 to V3 to their initial set values each time the power supply device 10 is turned on. Referring to the initially set level, the voltages V1 to V3 may be efficiently supplied from the first to third DC-DC converters 30 to 50 to the electronic device 60 . In addition, in the control circuit 10A for the power supply device and the power supply device 10 , it is not necessary to individually adjust the voltages V1 to V3 to their initial set values when the power supply device 10 supplies the voltages V1 to V3 to the electronic equipment 60 . On the contrary, the voltages V1 to V3 can be set to their optimum levels efficiently and at high speed by the first to third DC-DC converters 30 to 50 with reference to the optimum levels stored in registers including REG1 .

Similarly, the power supply device control method in the embodiment allows supply of the voltages V1 to V3 modified in response to initial data (initial setting level) or optimum levels stored in a volatile mode to the electronic device 60 . Therefore, it is not necessary to individually adjust the voltages V1 to V3 to their initial set values each time the power supply device 10 is turned on. The voltages V1 to V3 determined by the initially set levels can be effectively supplied to the electronic device 60 . In addition, the control method of the power supply device 10 does not need to individually adjust the voltages V1 to V3 to their initial set values when the power supply device 10 supplies the voltages V1 to V3 to the electronic device 60 . In contrast, the voltages V1 to V3 can be set to their optimal levels efficiently and at high speed with reference to the optimal levels for the electronic device 60 stored in the volatile mode.

The control circuit 10A for the power supply unit and the power supply unit 10 in the embodiment enable the registers REG1 to REG3 to replace the initial voltage levels for the electronic equipment 60 when the power supply unit 10 supplies voltages V1 to V3 to the electronic equipment 60. data (initial setting level) and stored. Therefore, when the power supply device 10 supplies the voltages V1 to V3 to the electronic equipment 60, the voltages V1 to V3 can be set efficiently and at high speed in response to the optimum levels for the electronic equipment 60 stored in the registers REG1 to REG3. to its optimum level.

Similarly, the power supply device control method in the embodiment makes it possible to replace the initial data (initial setting level) with the optimum level for the electronic device 60 when the power supply device 10 supplies the voltages V1 to V3 to the electronic device 60. stored in non-volatile mode. Therefore, the voltages V1 to V3 can be set to their optimal levels efficiently and at high speed in response to the optimal levels stored in the nonvolatile mode.

The control circuit 10A for the power supply unit and the power supply unit 10 in the embodiment enable the data processor 23 to write and store the data (received voltage levels) of the voltage adjustment signals S14 to S16 in the flash memory 22 instead of the initial data (initial setting level). Therefore, data (received voltage levels) for determining optimum levels of the voltages V1 to V3 can be stored in the flash memory 22 (nonvolatile memory unit) without losing any data.

Similarly, the power supply device control method in the embodiment allows storing data of a voltage adjustment signal (received voltage level) instead of initial data (initial setting level) previously stored in nonvolatile mode. Therefore, data (received voltage levels) for determining optimum levels of the voltages V1 to V3 can be stored in a nonvolatile mode without losing any data.

The control circuit 10A for a power supply device and the power supply device 10 in the embodiment enable the flash memory 22 (nonvolatile memory unit) to hold voltage adjustment data (received voltage level). Therefore, the voltage regulation data (received voltage level) can be safely stored in non-volatile mode without any data loss even when the power supply is interrupted.

Similarly, the power supply device control method in the embodiment allows storing the voltage adjustment data (received voltage level) of the voltage adjustment signal in a non-volatile mode. Therefore, voltage adjustment data (received voltage level) can be safely stored without any data loss.

The control circuit 10A for a power supply device and the power supply device 10 in the embodiment enable the interface controller 21 to output the voltage adjustment signals S14 to S16 to the registers REG1 to REG3 and the data processor 23, so that the voltage adjustment signals S14 to S16 ( voltage adjustment data) are stored in registers REG1 to REG3 (volatile storage units), and their voltage adjustment data (received voltage levels) corresponding to signals S14 to S16 are stored in flash memory 22 (nonvolatile storage unit). When the voltage adjustment data is stored in the registers REG1 to REG3, the data of the received voltage level is stored in the flash memory 22 in parallel. Therefore, the efficiency of the power supply device 10 can be improved compared to the case where the voltage adjustment data and the data of the received voltage level are sequentially stored in the registers REG1 to REG3 and the flash memory 22 .

Similarly, the control method of the power supply device 10 in the embodiment allows storing voltage adjustment data in a volatile mode, and storing data of a received voltage level in a nonvolatile mode. When the voltage adjustment data is stored in volatile mode, the data of the received voltage level is stored in parallel in non-volatile mode. Therefore, the efficiency of the power supply device 10 can be improved compared to the case where the voltage adjustment data and the data of the received voltage level are stored sequentially in the volatile mode and the nonvolatile mode.

The present invention is not limited to the above embodiments, but can be implemented with partial structural modifications without departing from the scope of the present invention. The control circuit 10A for the power supply device and the power supply device 10 in the embodiment allow the voltage adjustment signals S14 to S16 (voltage adjustment data) to be stored in the registers REG1 to REG3 (volatile memory units), and are compared with the voltage adjustment signal Data of the received voltage levels corresponding to S14 to S16 are stored in the flash memory 22 (nonvolatile memory unit). Alternatively, the voltage adjustment signals S14 to S16 (voltage adjustment data) may be stored in the registers REG1 to REG3 (volatile storage unit). Therefore, when the voltages V1 to V3 to be supplied to the electronic device 60 have been set to optimal levels efficiently and at high speed in response to the voltage adjustment data stored in the registers REG1 to REG3, the received voltage level Data is stored in the flash memory 22 without any data loss. In other words, it is possible to preferentially set the voltages V1 to V3 to be supplied to the electronic device 60 to optimal levels before storing data of the received voltage levels in the flash memory 22 without data loss.

The control method of the power supply device 10 may be modified in which the voltage adjustment signals S14 to S16 (voltage adjustment data) are stored in a volatile mode before storing data of the received voltage level in a nonvolatile mode. Therefore, when the voltages V1 to V3 to be supplied to the electronic device 60 have been set to optimum levels efficiently and at high speed in response to the voltage adjustment data stored in the volatile mode, the data of the received voltage level is stored without No data is lost. In other words, it is possible to preferentially set the voltages V1 to V3 to be supplied to the electronic device 60 to optimal levels before storing data of the received voltage levels.

Although the power supply device 10 in the embodiment has output units for three channels (CH1 to CH3) as shown in FIG. 1, it may also have output units for four or more corresponding channels. Furthermore, the flash memory 22 may hold a control program for the power supply device 10 in addition to storing initial data (initial setting level). The control circuit 10A in the power supply device 10 of the embodiment may include one or more semiconductor chips. The power supply device 10 may also include one or more semiconductor chips. The power supply device 10 and its control circuit 10A may be provided in a module. Also, the electronic equipment may include a power supply device having a control circuit and a DC-DC converter.

The control circuit for a power supply device, the power supply device and the control method thereof of the present invention are configured to receive and store a request from an electronic device to be powered when an initial setting level for determining an initial voltage level has been stored in advance. voltage level. This makes it possible to control the voltage to be supplied in response to the initially set level and the requested level. As a result, compared with the case where the voltage is adjusted every time the power supply device is activated to supply power to the electronic equipment, the voltage is set to the optimum set level required by the electronic equipment in response to the stored set level. The time required can be shortened, allowing high-speed and efficient voltage setting to an optimal level.

This application is based on and claims priority from prior Japanese Patent Application No. 2006-047819 filed on February 24, 2006, the entire contents of which are hereby incorporated by reference.

Claims (14)

1. A control circuit for a power supply device for supplying a required voltage to a device which provides an initial voltage and then requires to receive said required voltage different from said initial voltage, said The control circuit includes: a communication unit for receiving a required level of said required voltage; and a storage unit for pre-storing an initial set level for determining the initial voltage, and storing the required level received by the communication unit, wherein controlling the initial voltage or the required voltage in response to the initially set level or the required level, Wherein said storage unit comprises: a non-volatile storage unit in which at least the initial set level is pre-stored; and a register unit for storing the initially set level and the required level, and wherein the register unit stores an initial set level read from the nonvolatile storage unit when the power supply unit is activated, and stores a request received by the communication unit when the power supply unit is operated level. 2. The control circuit for a power supply device as claimed in claim 1, further comprising: A voltage controller unit for controlling the initial voltage or the required voltage in response to the initially set level or the required level stored in the register unit. 3. The control circuit for a power supply device as claimed in claim 1, wherein The register unit stores the required level instead of the initial setting level when the power supply device is operated. 4. The control circuit for a power supply device as claimed in claim 1, wherein The nonvolatile storage unit stores the required level instead of the previously stored initial setting level. 5. The control circuit for a power supply device as claimed in claim 1, wherein The required level is received by the communication unit and then stored in the register unit and the non-volatile storage unit simultaneously. 6. The control circuit for a power supply device as claimed in claim 1, wherein The required level is stored in the register unit and then stored in the nonvolatile storage unit after being received by the communication unit. 7. A power supply unit for supplying a required voltage to a device that provides an initial voltage and then requires to receive said required voltage different from said initial voltage, said power supply unit comprising: a communication unit for receiving a required level of said required voltage; and a storage unit for pre-storing an initial set level for determining the initial voltage, and storing the required level received by the communication unit, wherein controlling the initial voltage or the required voltage in response to the initially set level or the required level, Wherein said storage unit comprises: a non-volatile storage unit in which at least the initial set level is pre-stored; and a register unit for storing the initially set level and the required level, and wherein the register unit stores an initial set level read from the nonvolatile storage unit when the power supply unit is activated, and stores a request received by the communication unit when the power supply unit is operated level. 8. The power supply unit according to claim 7, comprising: A voltage controller unit for controlling the initial voltage or the required voltage in response to the initially set level or the required level stored in the register unit. 9. The power supply device as claimed in claim 7, wherein The register unit stores the required level instead of the initial setting level when the power supply device is operated. 10. The power supply device as claimed in claim 7, wherein The nonvolatile storage unit stores the required level instead of the previously stored initial setting level. 11. The power supply device as claimed in claim 7, wherein The required level is received by the communication unit and then stored in the register unit and the non-volatile storage unit simultaneously. 12. The power supply unit as claimed in claim 7, wherein The required level is stored in the register unit and then stored in the nonvolatile storage unit after being received by the communication unit. 13. A method of controlling a power supply device for supplying a required voltage to a device that provides an initial voltage and then requests to receive the required voltage different from the initial voltage, the method comprising the following step: receiving a desired level of said desired voltage; storing in advance an initial set level for determining the initial voltage, and storing the received requested level; and controlling the initial voltage or the required voltage in response to the initially set level or the required level, Wherein said storing step comprises: storing at least the initial set level in advance in a non-volatile mode; storing said initially set level and said requested level in volatile mode; and When the power supply unit is activated, read out the initial setting level stored in the non-volatile mode, and store the initial setting level in the volatile mode; and when the power supply unit is operated, in the The volatile mode stores the received request level. 14. The power supply device control method as claimed in claim 13, wherein The requested level is stored in nonvolatile mode instead of the initial setting level previously stored in nonvolatile mode.

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