CN100440305C - A Realization Circuit of Liquid Crystal Gray Scale - Google Patents

Abstract

The invention discloses a liquid crystal grayscale realization circuit, which includes a pulse generation unit, a grayscale modulation unit, a grayscale data reading control unit, a data memory, and a frame synchronization generation unit; the pulse generation unit is used to generate periodic The pulse waveform generates a horizontal synchronous signal, including a sub-frame counter, each of which outputs a counter reset control signal, controls a plurality of counters in parallel, and controls their reset; the clock signal of the counter corresponds to the input of the corresponding pulse width generator A comparator, the output of the comparator is used as a selection signal of a selector to generate a corresponding pulse waveform after selecting the high/low level; the data memory is used to store grayscale data; the frame synchronously generates The unit is used to generate a frame synchronization signal; the gray modulation unit is used to combine pulses and output them. The circuit of the invention realizes the function of converting the gray scale data into pulses with few logic gates, saves the area and is simple to realize the circuit.

Description

A Realization Circuit of Liquid Crystal Gray Scale

technical field

The invention relates to a grayscale modulation unit of a liquid crystal display control drive chip, in particular to an improvement of a liquid crystal grayscale pulse generation unit.

Background technique

The existing light-emitting mechanism of liquid crystal displays realizes different brightness by applying different electric fields to a certain pixel point. Current driver chips generally adopt a dynamic driving method and are divided into row electrodes and column electrodes. Generally, the row electrodes are scanned row by row at a frame rate above 30 Hz, and a bright or non-bright signal is applied synchronously to the column electrodes.

The voltage on the column electrodes is gated or not gated by generating pulse signals with different widths through digital logic and sending them to the analog driving circuit. When the sent pulse width is 0, it will not be strobed, and when the sent pulse width is not 0, it will be gated for the corresponding time length, which corresponds to different light and dark levels, called gray scale. Therefore, from the perspective of digital circuit design, the only concern is how long the pulse width sent to the analog drive circuit lasts. The longest continuous level of the pulse width is the highest gray level that can be achieved.

Any color is obtained by mixing the three primary colors of RGB (red, green and blue) according to different proportions. If R, G, and B have X, Y, and Z possible values respectively, a total of X*Y*Z colors can be achieved. For example, R, G, and B each have 64 grayscale options, and a total of 64*64*64 = 262144 possible combinations. Since the implementation circuits of R, G, and B are exactly the same, it is necessary to design a circuit that can output 64 gray values in a certain waveform to the analog driving circuit.

Currently, there are generally two grayscale modulation methods, PWM and FRC.

PWM, that is, Pulse Width Modulation (Pulse Width Modulation), is divided into several time slices in one scan time, such as 64-level grayscale, it is divided into 64 time slices; if 5/64 grayscale is displayed, then the point is It is said that there is driving voltage only in 5/64 of the time, and the final equivalent voltage is only 5/64 of all black.

FRC, that is, Frame Rate Control, is that each time slice becomes a subframe and displays 64 levels of grayscale, so 64 subframes are used. First of all, we need to distinguish the concept of subframe. The frame rate refers to the number of full-screen data scanned within one second. In order to realize FRC, a frame is divided into several subframes. Due to the visual effect of the human eye, the perceived brightness is the accumulation of all subframes, see the effect shown in Figure 1, the gray level of each point is the cumulative effect of the subframes at this point.

For gray levels with relatively high order, the combination of PWM+FRC is generally used. Because the higher the grayscale, the higher the frequency required for PWM, and the greater the power consumption. The bit width of the grayscale data determines the grayscale level. Generally speaking, the grayscale that can be achieved by jPWM+kFRC (j, k=0, 1, 2...) is 2 ^(j+K) , and j+k is The bit width of the grayscale data. If you want to achieve 64 levels of grayscale, (j+k) should be 6. 5PWM+1FRC means that it is divided into two subframes, and each subframe has 32 time slices, as shown in Figure 2. 4PWM+2FRC means that it is divided into four subframes, and each subframe has 16 time slices, as shown in Figure 3.

An existing circuit structure is shown in Figure 4. For the grayscale data of each pixel, there is a counter to compare with it. If the value of the counter is less than the grayscale value, the output is high level. If If the value of the counter is greater than the gray value, the output is a low level.

Although this kind of circuit is simple to implement, since each pixel on the LCD screen needs three such circuits, one circuit includes a 6-bit counter and a 6-bit comparator, so the area is very large, and it is difficult to use in terms of cost and actual use. The above considerations cannot be adopted.

Contents of the invention

The purpose of the present invention is to provide a liquid crystal grayscale realization circuit, through the hardware design scheme of pulse gating, after superimposing each pulse width, using the grayscale data information, different pulse widths are selected at different times to realize 64 levels The gray scale is to overcome the disadvantage of large drive circuit area in the prior art.

Technical scheme of the present invention comprises:

A liquid crystal grayscale realization circuit, which includes a pulse generation unit, a grayscale modulation unit, a grayscale data reading control unit, a data memory, and a frame synchronization generation unit;

The pulse generation unit is used to generate periodic pulse waveforms, which are used as the input of the gray scale modulation unit, and simultaneously generate a line synchronization signal; the pulse generation unit also includes a sub-frame counter, and each bit outputs a counter reset control signal , control a plurality of counters in parallel, and control their reset; the clock signal of the counter and the corresponding pulse width generator input a corresponding comparator, the output of the comparator is used as a selector selection signal for high or The corresponding pulse waveform is generated after the low level is selected;

The grayscale data reading control unit is used to select an address according to the row synchronous signal, and read grayscale data from the data memory as the input of the grayscale modulation unit;

The data memory is used to store grayscale data, and output the grayscale data according to the address input by the grayscale data reading control unit and the read application signal;

The frame synchronization generating unit is used to receive the line synchronization signal, and generate a frame synchronization signal according to the size of the LCD panel;

The gray-scale modulation unit is used to input pulses and gray-scale data, and realize output after combining pulses of each segment of gray-scale data.

In the above circuit, the pulse width generator in the pulse generating unit is formed by combining a predetermined width value and a pre-allocated remainder pulse width.

In the above-mentioned circuit, the gray scale modulating unit outputs high or low level waveforms, which represent different gray scales according to the duration of the high and low levels.

The circuit described above, wherein the gray scale modulation unit further includes: a plurality of selectors cascaded, each selector uses a pulse as a data selection signal, and its input signal is gray scale data and the selector at the previous level Output.

Compared with the prior art, the liquid crystal grayscale realization circuit provided by the present invention realizes the function of converting grayscale data into pulses with few logic gates, saves the area, and has a simple realization circuit.

Description of drawings

FIG. 1 is a schematic diagram of the effect of grayscale modulation in the prior art on the human eye;

FIG. 2 is a schematic diagram of a 5PWM+1FRC mode in the prior art;

FIG. 3 is a schematic diagram of a 4PWM+2FRC mode in the prior art;

Fig. 4 is the circuit principle diagram that the counter mode of prior art realizes liquid crystal gray scale;

Fig. 5 is that the pulse gating mode of the present invention realizes the liquid crystal gray scale circuit diagram;

Fig. 6 is a circuit diagram of the grayscale modulation unit of the present invention;

Fig. 7 is the circuit diagram of the pulse generation unit of the present invention;

Fig. 8 is the excitation pulse that 5PWM+1FRC of the present invention needs to input, and the effect diagram of the grayscale data output under the grayscale modulation unit;

Fig. 9 is an excitation pulse that needs to be input by 4PWM+2FRC of the present invention, and an effect diagram of grayscale data output under the grayscale modulation unit.

Detailed ways

Below in conjunction with accompanying drawing, the implementation of technical solution will be described in further detail:

The realization circuit of liquid crystal grayscale in the present invention has a structure as shown in FIG. 5 , including a pulse generation unit, a grayscale modulation unit, a grayscale data reading control unit, a data memory, and a frame synchronization generation unit.

The pulse generation unit is used to generate a periodic pulse waveform as the input of the gray scale modulation unit, and simultaneously generate a horizontal synchronous signal. The grayscale data reading control unit is used for selecting an address according to the row synchronous signal, and reading grayscale data from the data memory as an input of the grayscale modulation unit. The data memory is used to store grayscale data, and output the grayscale data according to the address input by the grayscale data reading control unit and the read application signal. The frame synchronization generating unit is used for receiving the line synchronization signal and generating the frame synchronization signal according to the size of the LCD panel. The gray-scale modulation unit is used to input pulses and gray-scale data, and realize the combined output of the pulses of each segment of gray-scale data. The output waveform has only two levels, high and low, and different gray levels are represented according to the duration of the high and low levels. Spend.

Since the grayscale data of any color cannot be changed, the design of the excitation pulse generation unit and the grayscale modulation unit directly affects the output waveform of the circuit of the present invention.

The present invention adopts the way of pulse gating, and can pre-generate a group of pulse widths A, B, C, D... with different lengths, and use A, B, C, D... as the unit of gating. The 5PWM+1FRC algorithm has 2 subframes, and each subframe uses 5 combinations of pulse widths to represent the pulse width from 0 to 31; the 4PWM+2FRC algorithm has 4 subframes, and each subframe uses 4 combinations of pulse widths To represent the pulse width of 0-15. According to the principle of binary counting, the weight of binary counting can be selected for the fixed pulse length, that is, 1, 2, 4, 8, 16...etc.

In jPWM+kFRC hybrid modulation, FRC is equivalent to division, and the remainder must be added to each subframe, so each pulse used to add the remainder must be generated. For example, in 4PWM+2FRC, the display intensity 63 is divided into 4 subframes, and a combination method of the pulse width of each subframe is (15+1)/(15+1)/(15+1)/15.

In the 4PWM+2FRC mode, four values of A, B, C, and D need to be found, and in the 5PWM+1FRC mode, five values of A, B, C, D, and E need to be found, and the remainder is also needed. The present invention is as follows combination:

1.4PWM+2FRC, {+1, +2, A=1, B=2, C=4, D=8}

2.5PWM+1FRC, {+1, A=1, B=2, C=4, D=8, E=16}

As shown in FIG. 5 , grayscale data is stored in the data memory of the present invention, which is actually the information of gating ABCD... a certain pulse width. Bit5, Bit4, Bit3, Bit2, Bit1, Bit0 respectively correspond to {8, 4, 2, 1, 2, 1} in 4PWM+2FRC mode, and correspond to {16, 8, 4, 2 in 5PWM+1FRC mode , 1, 1}, so the binary representation of any value is the strobe signal. For example, 21=6'b010101, this is the strobe signal, in 5PWM+1FRC mode, corresponding to (E, D, C, B, A, +1), can be obtained by strobing C, D and the remainder pulse.

The design of the gray modulation unit of the present invention is shown in Fig. 6. P is the upper input when the level is high, and the lower input when the level is low, so that the pulse width can be strobed ingeniously. Figure 6 only draws a monochrome (R or G or B) part of a pixel, it can be seen that for 6-bit data, only 5 selectors can be implemented, which is much simpler than the original counter method circuit.

As shown in FIG. 7 , there is only one pulse generating unit in the present invention, and the generated pulses P0 . . . Pn are shared by gray scale modulation units of all pixels. Its logic control is relatively complicated, because the remainder pulse does not exist in every subframe. First analyze the generation of P0, as shown in Figure 7, the counter 0 is compared with the output of the P0 pulse width generator, if they are equal, the level of P0 is reversed, and the counter 0 is reset, if they are not equal, continue counting. The P0 pulse width generator determines the high-level duration of the pulse, which is related to the value of A and the remainder pulse, and which subframe it is in. The reset timing of the counter 0 and the duration of the reset are related to which subframe it is in and whether the maximum value of the counter is reached.

The generation of the pulses P1 . . . Pn is similar to P0, and the Pn pulse width generator needs to consider all pulse widths A, B . . . and all remainder pulses.

For example, the example mentioned above, 21=6'b010101, in 5PWM+1FRC mode, corresponding to (E, D, C, B, A, +1), can be obtained by gating C, D and the remainder pulse, if every If each subframe has a remainder pulse, you get 22, not 21. Therefore, the present invention needs to reasonably allocate the remainder pulses to a certain subframe.

Taking 5PWM+1FRC as an example, in subframe 0, p0=(+1), p1=(A+1), p2=(A+B+1), p3=(A+B+C+1), p4=(A+B+C+D+1), and the low level of pulse4 is (E).

Because the remainder pulse distribution is different, the width of each subframe is different. In 5PWM+1FRC mode, only subframe 0 has additional pulses. Subframe 0 is 31+1=32, and subframe 1 is 31, as shown in FIG. 8 .

In 4PWM+2FRC mode, the additional pulse of subframe 0 is 1, and the additional pulse of subframe 1 is 2. Subframe 0 is 15+1=16, subframe 1 is 15+2=17, subframe 2 is 15, and subframe 3 is 15, as shown in FIG. 9 .

The present invention adopts the way of pulse gating, and needs to generate a group of pulse widths ABCD... with different lengths in advance, and use A, B, C, D... as the unit of gating.

For example, 42=6'b101010, corresponding to b5, b4, b3, b2, b1, b0 respectively. In 5PWM+1FRC mode:

When P4=0, b5 is selected for 16 pulses, when P4=1 and P3=1, P2=0, b3 is selected for 4 pulses, P4=1 and P3=1, P2=1, P1=1, When P0 = 0, select b1 for one pulse. Each subframe lasts for 21 pulses, for a total of 42 over two subframes.

42=6'b101010, in 4PWM+2FRC mode:

Subframe 0: When P4=0, b5 is selected for 8 pulses, when P4=1 and P3=1, P2=0, b3 is selected for 2 pulses, P4=1 and P3=1, P2= 1. P1=1, P0=0 can select b1, this condition is not satisfied, so last 8+2+1=10 pulses;

Subframe 1: When P4=0, b5 is selected for 8 pulses, when P4=1 and P3=1, P2=0, b3 is selected for 2 pulses, P4=1 and P3=1, P2=1, When P1=1 and P0=0, select b1 for 2 pulses. Continuous 8+2+2=12 pulses;

Subframe 2: When P4=0, b5 is selected for 8 pulses, when P4=1 and P3=1, P2=0, b3 is selected for 2 pulses, P4=1 and P3=1, P2=1, When P1=0 and P0=0, b1 is selected, and there is no continuous pulse. Continuous 8+2=10 pulses;

Subframe 3: When P4=0, b5 is selected for 8 pulses, when P4=1 and P3=1, P2=0, b3 is selected for 2 pulses, P4=1 and P3=1, P2=1, When P1=0 and P0=0, b0 is selected, and there is no continuous pulse. Continuous 8+2=10 pulses;

So four subframes 10+12+10+10=42.

The present invention realizes grayscale modulation in a liquid crystal driver chip. First, a hardware design scheme of pulse gating is proposed. Considering the limitation of hardware resources, an improvement is made. After superimposing each pulse width, the grayscale data information , choose different pulse widths at different times to achieve 64 gray levels, which greatly saves the area, and the realization circuit is simpler.

It should be noted that the above descriptions for specific embodiments are relatively detailed, which should not be construed as limiting the scope of the patent protection of the present invention, and the scope of protection of the patent protection of the present invention should be determined by the appended claims.

Claims (4)

1. A realization circuit of liquid crystal grayscale, characterized in that it comprises a pulse generation unit, a grayscale modulation unit, a grayscale data reading control unit, a data memory, and a frame synchronization generation unit; The pulse generation unit is used to generate periodic pulse waveforms, which are used as the input of the gray scale modulation unit, and simultaneously generate a line synchronization signal; the pulse generation unit also includes a sub-frame counter, and each bit outputs a counter reset control signal , control a plurality of counters in parallel, and control their reset; the clock signal of the counter and the corresponding pulse width generator input a corresponding comparator, the output of the comparator is used as a selector selection signal for high or The corresponding pulse waveform is generated after the low level is selected; The grayscale data reading control unit is used to select an address according to the row synchronous signal, and read grayscale data from the data memory as the input of the grayscale modulation unit; The data memory is used to store grayscale data, and output the grayscale data according to the address input by the grayscale data reading control unit and the read application signal; The frame synchronization generating unit is used to receive the line synchronization signal, and generate a frame synchronization signal according to the size of the LCD panel; The gray-scale modulation unit is used to input pulses and gray-scale data, and realize output after combining pulses of each segment of gray-scale data. 2. The circuit according to claim 1, wherein the pulse width generator in the pulse generating unit is formed by combining a predetermined width value and a pre-allocated remainder pulse width. 3. The circuit according to claim 1, wherein the grayscale modulation unit outputs high or low level waveforms, and represents different grayscales according to the duration of the high and low levels. 4. The circuit according to claim 1, wherein the gray scale modulation unit further comprises: a plurality of selectors connected in cascade, each selector uses a pulse as a data selection signal, and its input signal is gray degree data and the output of the previous selector.

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