hsverilog: Synthesizable Verilog DSL supporting for multiple clock and reset
Modules
[Index]
Downloads
- hsverilog-0.1.0.tar.gz [browse] (Cabal source package)
- Package description (as included in the package)
Maintainer's Corner
For package maintainers and hackage trustees
Candidates
- No Candidates
| Versions [RSS] | 0.1.0 |
|---|---|
| Change log | ChangeLog.md |
| Dependencies | base (>=4.6 && <5), containers, shakespeare, text, transformers [details] |
| License | BSD-3-Clause |
| Author | Junji Hashimoto |
| Maintainer | junji.hashimoto@gmail.com |
| Category | Hardware |
| Bug tracker | https://github.com/junjihashimoto/hsverilog/issues |
| Source repo | head: git clone https://github.com/junjihashimoto/hsverilog.git |
| Uploaded | by junjihashimoto at 2015-02-19T23:59:58Z |
| Distributions | NixOS:0.1.0 |
| Reverse Dependencies | 1 direct, 0 indirect [details] |
| Downloads | 1210 total (2 in the last 30 days) |
| Rating | (no votes yet) [estimated by Bayesian average] |
| Your Rating | |
| Status | Docs available [build log] Last success reported on 2015-05-20 [all 2 reports] |
Readme for hsverilog-0.1.0
[back to package description]HsVerilog: Synthesizable Verilog DSL supporting for multiple clock and reset
Getting started
Install this from Hackage.
cabal update && cabal install hsverilog
Usage
Syntax is similar to Verilog. See tests/test.hs and following examples.
counter circuit
circuit "counter" $ do
clk <- input "clk" Bit
rstn <- input "rstn" Bit
_ <- output "dout" $ 7><0
reg "dout" (7><0) [Posedge clk,Negedge rstn] $ \dout ->
If (Not (S rstn)) 0 $
If (Eq dout 7)
0
(dout + 1)