A proposal for a friendlier microcontroller architecture using the beautiful RISC-V instruction set.

Version: 0.1.1

Editors:

• Liviu Ionescu

Warning: This draft specification is in a preliminary phase and may change at any time. For the moment it is more like a wish list than a real specs document.

• Introduction
• Memory Map
• The Startup Process
• Exceptions and Interrupts
• Control and Status Registers (CSRs)
• Hart Control Block (hcb)
• Hart Interrupt Controller (hic)
• Device Control Block (dcb)
• Device Real-Time Clock (rtclock)
• Device System Clock (sysclock)
• Device Watchdog Timer (wdog)
• Embedded ABI (EABI)
• RTOS Support Features
• Appendix A: Improvements upon RISC-V privileged <--- Read Me First!
• Appendix B: History
• Appendix C: Contributing

TODO:

• add MPU definitions
• add more details about the restrictions in user mode.

This document is released under a Creative Commons Attribution 4.0 International license.