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Table 5. State of the art model based on FPGA environments (model 2) Table 6. Epoch wise results (mse and time computation) for the second (state of the art) proposed model

Table 5 State of the art model based on FPGA environments (model 2) Table 6. Epoch wise results (mse and time computation) for the second (state of the art) proposed model

Related Figures (8)

Figure 1. PYNQ-Z2 FPGA development board structure FPGAs through the PYNQ interface, unlocking the potential for high-performance inference and acceleration [24].
Figure 1. PYNQ-Z2 FPGA development board structure FPGAs through the PYNQ interface, unlocking the potential for high-performance inference and acceleration [24].
Figure 2. Network configuration page
Figure 2. Network configuration page
Figure 3. Putty software configuration page
Figure 3. Putty software configuration page
Table 3. The first proposed model of FPGA based modulation classification detection Table 4. Epoch wise results (mse and time computation) for the first proposed model After uploading database file into notebook, here all data rows need to read and stored on separated array; the same procedure of the simulation stage is used over here unless the rows dimensions with is (50x50) points are resampled to match the DL model. A new dimension similar to (1x50x50) is made. Table 3 is demonstrating the model structure. This model is trained using ADAM algorithm with 20 epochs and batch size of 20 samples as illustrated. Thereafter, model is being trained for error minimization at the detection results, however, the results are given in the Table 4.
Table 3. The first proposed model of FPGA based modulation classification detection Table 4. Epoch wise results (mse and time computation) for the first proposed model After uploading database file into notebook, here all data rows need to read and stored on separated array; the same procedure of the simulation stage is used over here unless the rows dimensions with is (50x50) points are resampled to match the DL model. A new dimension similar to (1x50x50) is made. Table 3 is demonstrating the model structure. This model is trained using ADAM algorithm with 20 epochs and batch size of 20 samples as illustrated. Thereafter, model is being trained for error minimization at the detection results, however, the results are given in the Table 4.
4.3. Model 2 With the aim of reducing prediction errors and minimizing processing time, Model 2 has been constructed with three convolutional layers. While the structure of this model bears similarity to that proposed in the CPU (CNN) model, detailed configurations for Model 2 are provided in Table 5. Results
4.3. Model 2 With the aim of reducing prediction errors and minimizing processing time, Model 2 has been constructed with three convolutional layers. While the structure of this model bears similarity to that proposed in the CPU (CNN) model, detailed configurations for Model 2 are provided in Table 5. Results
Table 7. Configuration of second DL model [29]
Table 7. Configuration of second DL model [29]
Table 1. Comparison of different FPGA models using different networks
Table 1. Comparison of different FPGA models using different networks
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