Crystal equivalent circuit: The crystal equivalent circuit of the quartz crystal consists of a motional capacitance Cl, the motional inductance L1, a series resistance R1, and a shunt capacitance C0. The first three parameters are known as the "motional parameters". See figure 1.

Frequency tolerance: The maximum allowable frequency deviation from a specified nominal frequency at ambient room temperature (25°C + 3°C). Frequency tolerance is expressed in percent (%) or parts per millions (ppm).

Frequency stability: The maximum allowable frequency deviation from the ambient temperature over the temperature range. Frequency stability is expressed in percent (%) or parts per millions (ppm). The frequency stability is determined by cut type, angle cut, angle cut tolerance, mode of operation, package styles, and mechanical dimensions of the quartz blank.

Series vs. Parallel resonance: When a crystal is operating at series resonance (Fs), it looks resistive in the circuit. At this point \XL\ = \XC\. In series resonance, load capacitance does not have to be specified. The antiresonant frequency (Fa) occurs when the reactance in the series branch is equal to CO.
When a crystal is operating at parallel resonance, it looks inductive in the circuit. The crystal equivalent circuit can be simplified as a series resistance Re with a reactance Xe.
The difference in frequency between the Fs and Fa depends on the CO/C1 ratio of the crystal unit, and the inductance LI. In parallel resonance, the load capacitance shall be specified.

Aging: The relative frequency change over a certain period of time and is typically expressed as a maximum value in parts per million per year (ppm/year). Typically, aging is computed within the first 30 days to 90 days and predicted exponentially over a longer period usually a year.

Operating temperature: The minimum and maximum temperatures within which crystal unit operates under specified conditions.

Storage temperature: The minimum and maximum temperatures that the crystal unit can be safely stored. Drive level: A function of the driving or excitation current flowing through the crystal. The drive level is the amount of power dissipated in the crystal and is expressed in milliwatts or microwatts. Drive level should be kept at a safe minimum condition to assure proper start-up. Excessive drive level will result in possible long-term frequency drift or crystal fracture.

Figure 4 shows the relationship between drive level and circuit load capacitance and optimum value guarantee for start-up condition.

Motional capacitance C1: The capacitance of the nominal arm of the equivalent circuit. C1 results from the elasticity of the quartz blank.

Quality factor Q: The factor that represents the sharpness of the resonant curve. Quartz crystal has a very high Q compared to other resonators typically in 10,000 to 100,000s.

Delta F from series resonant to parallel resonant in ppm:

Procedure:
1. Connect the external resistance Ri in series with the crystal.
2. Adjust Ri value until oscillation stops.
3. Record Ri value.
4. Negative resistance -R = Ri+RI
5. Recommended - R value to be at least 5 to 10 times greater than Re.
See figure 9.

As grown quartz bars - Lumbering - Cutting - Measurement of angle - Precision lapping - Beveling - Etching and Cleaning - Base coating - Mounting - Fine frequency adjusting -Annealing - Sealing - Aging - Final tests and Inspections.

Crystal mounting methods: Quartz blank unit is mounted on holder mounts with conductive epoxy or solder (tuning fork). Precise amount of silver epoxy is applied with automounter equipment.

1. ASIC CHARACTERISTICS:
   1. Negative resistance.
   2. Small-signal gain analysis.
   3. Input and output resistance.
   4. Propagation delay between input and output of inverter.
   5. Gain-phase analysis.
   6. Supply voltage operational margin.
   7. Circuit configuration.
   8. Feedback resistor value (if integrated within the ASIC).
   9. Built-in load capacitance on XI and X2 ports.
   10. Sensitivity of inverter operation versus stray inductance or capacitance due to layout or attachment methods.

2. CRYSTAL CHARACTERISTICS:
   1. Mode of Operation (Fundamental -vs.- Overtone).
   2. Series -vs.- Parallel.
   3. If Parallel: State "Load Capacitance".
   4. If Overtone: specify design without inductor or conventional tuning tank LC Circuit.
   5. Maximum Resistance.
   6. Drive Level dependency.
   7. Operating Temperature.
   8. Frequency Accuracy at 25° C.
   9. Frequency Stability over Temperature.
   10. Aging.
   11. Pulling Characteristics.
   12. Spurious Responses.

3. CIRCUIT CONSIDERATIONS:
   1. Select the best value for Rf (feedback resistor).
      Recommend Value:
      Low kHz Range: between 10M Ohms to 20 M Ohms
      MHz Range: between 100k Ohms to 1 M Ohms

   2. Select Series Resistance Value (Rd) for impedance matching. Rd selection varies with ASIC negative resistance, output resistance and load impedance. Typical Value for Rd:
      0 Ohms (Short) to 1 k Ohms from 4 MHz to 30 MHz.

   3. Study the Voltage Gain from output to input Vi/Vo= C2/C1. It is very common to select equal values of C1 and C2 in the circuit, but sometimes it is necessary to make the output load capacitance (C2) higher to compensate for the signal losses through the crystal and feed back loop.

   4. Maximum Crystal Resistance Allowed. Low resistance is desirable for better operational margin and stability. However, crystal resistance varies with frequency, blank size. Low crystal resistance could affect yield and therefore cost.

   5. Typical Crystal Aging: + 5 ppm per year maximum. Aging over 10 years: + 10 ppm to + s15 ppm maximum. Tighter aging (up to +1 ppm per year max.) is available. Tighter aging requires extremely high design, manufacturing and additional post-tests.

   6. Inductorless Third (3rd) Overtone: The Inductorless 3rd-0vertone circuit is similar to the fundamental frequency circuit except the feedback resistor value is made much smaller (typical value varies between 2 kQ to 6 kQ). In this case, the component of inductive admittance due to the resistor is greater than the admittance of the loading capacitance at the fundamental frequency, thereby preventing oscillation at the fundamental frequency. In the meantime, the inductive admittance at the overtone is less than the admittance of the Load Capacitor thus enabling the oscillation at the third-overtone. (See fig 1.)
      
      U1: ASCI
      Y1: Crystal
      C₁ C₂: Load Capacitance

      Fig. 1

   Tuning Tank LC Overtone Circuit.
   

   1. In an overtone mode, an additional inductor LI and capacitance C_C is required to select the Srd-Overtone mode, while suppressing or rejecting the fundamental mode. Choose L_C and C_C component values in the Srd-overtone crystal circuit to satisfy the following conditions:

   2. The L_C / C_C component form a series resonant circuit at a frequency below the fundamental frequency, which makes the circuit look inductive at the fundamental frequency. This condition does not favor to oscillation at the fundamental mode.

   3. The LI / C_C and C2 components form a parallel resonant circuit at a frequency about half-way between the fundamental and Srd-Overtone frequency. This condition makes the circuit capacitive at the 3rd-Overtone frequency, which favors the oscillation at the desired Overtone mode. (See figure 2).
      

   4. The Lc tank may be located at either input or output of the inverter. However, the Lc tank at the out put is referred, because it helps to clean up all unwanted modes before signal goes through the crystal.

4. CONTROL UNWANTED MODES IN CRYSTALS:
   Unwanted modes are resonant modes in addition to the desired modes (Fundamental, Third-Overtone, Fifth overtone, etc.). The frequencies of these unwanted modes are usually slightly higher than the desired modes within couple of hundreds kilohertz. In oscillator applications, it is necessary to control unwanted modes as lower as possible to prevent circuit oscillating in the "spurious mode". See Figure 3. The design of large electrodes on crystal to produce large pulling is a common cause of promoting spurs. Unwanted modes are usually specified in terms of resistance or in terms of the ratio of resistance of the unwanted mode to the resistance of the main mode over a bandwidth of desired frequency. A resistance ratio of 2:1 or a minimum of 3dB separation is usually adequate.

A: This is the most common complaint heard from crystal users. Unless the crystal supplier knows this common mode of failure, and applies preventive measures, this common problem can be solved earlier in design stage. Some customers describe these crystals as "sleeping crystals". The circuit start-up sometimes and does not at other times, unless been touched with a scope probe or fingers. Abracon predicts this problem in our Design and Process Failure Mode Effect Analysis (DFMEAand PFMEA) with two main root causes:

1. Blank cleanliness.
2. Drive level dependency.
3. IC matching.

1. Blank cleanliness: We use special blank wafer ultrasonic cleaning procedure in De-ionized water and 99.99% Isopropyl Alcohol with modulated air method to guarantee highest quality.
2. Drive level dependency: On most production lots, we perform 100% DLD tests at five levels minimum starting from 1 pW to 500pW. The DLD test will guarantee that the changes in ESR and frequency are within maximum limits thus assure the initial power start-up.
   

   Typical FDLD: + 5ppm max.
   

   Typical RDLD: 25% max.

3. IC matching: Abracon offers IC matching process to our customers in early design stage. The IC matching process will identify the optimum values of load capacitors, feedback and series resistors, drive level vs. load cap, voltage margin, open-loop gain at resonance, and temperature characteristics.
   Please consult Beckwith Electronics for details.

   Q: How to specify a pulling crystal?

   A: Many applications in VCXO, PLL network require a crystal with pulling characteristics. The pullability of the crystal can be explained as follow:
   When a crystal is operating at parallel resonance, it looks inductive in the circuit. As the reactance changes, the frequency changes correspondingly, thus change the pullability of the crystal. The difference between the Fs and Fa depends on the ratio CO/C1 ratio of the crystal.

   The following crystal parameters specify the pullability:
   

4. Motional capacitance C1 in fF.
5. Motional inductance LI in mH
6. The difference of the parallel resonant frequency
   

   F = FL2 - FL1
   

7. Ratio of shunt capacitance to motional capacitance CO/C1. The smaller ratio the better the pulling. The pullability of the crystal can be designed to meet customer's requirements. However, the pulling function varies with package size, electrode size, frequency, load capacitance range, and operating mode. Please contact Abracon whenever you have a need for a pulling crystal.

   Q: What is the trend of crystal packaging and advantages?

   A:

8. Minimizing the size and weight of mobile communication application such as cellular phones, PCMCIA, PDA, etc.
9. Improve sealing technologies from resin sealing to seam sealing to Electron beam sealing.
10. Advanced small quartz blank design in smaller ceramic packages such as 5.0 x 3.2mm, 3.2 x 2.5mm, etc. The fundamental frequency increases up to 66MHz helps simplify circuit design and is more efficient compared to the old traditional third-overtone circuit complexity.
11. Features of E-Beam sealing:
    1. Tight stability and tight tolerance (+10ppm).
    2. Low ESR and high reliability by vacuum package.
    3. Resistance to shock and moisture.
    4. High productivity captured with seam sealing method.
    5. Miniaturization by fine processing of E-Beam.
12. LTCC packaging helps reducing size and external components.

A: Abracon offers quick-turn programmable oscillators in four different package styles; the ceramic package 7.0x5.0x1.6 mm, plastic molded package similar to Epson SG-8002, and the 14 pin and 8 pin dip packages. The single PLL architecture with EPROM programmable generates a custom frequency derived from an internal crystal between lOMHz to 25MHz. The main advantages of the programmable oscillators are:

• Easy customization and fast turnaround.
• Wide frequency ranges IMHz to 133MHz.
• Programming accuracy > 6 digits.
• Output control Synchronous or Asynchronous.
• Output levels CMOS or TTL.
• Fast rise and fall times.
• Fast programming time > 5 seconds per unit.
• Low skew, low jitter, high accuracy outputs.
• Enables design flexibility and easy of use.
• Powerdown and output enable options available.
• Configurable 5V or 3.3VDC operation in seconds.
• Reprogrammable for quick design changes (applied to blank only).
• Extended temperature -40°C to +85°C with good frequency vs. temperature characteristics.

Q: What is PLL technology?

A: A PLL allows a frequency to be generated from any other frequency, where:

A: Jitter is the uncertainty or short-term variations of a digital waveform timing from their ideal positions in time.
The waveform transition could be too early or too late compared to the ideal waveform timing.

A: We use LeCroy digitizing oscilloscope with jitter timing software for jitter measurement and analysis. The scope must have the bandwidth at least five times the frequency of the waveform since the waveform jitter is measured as each rising cycle crosses the threshold voltage. The larger number of continuous cycles the more accurate is the jitter distribution. Jitter is measured in cycle-to-cycle (or absolute jitter) or one sigma jitter (rms.) using the histogram analysis. Unit of jitter is ps.

A: Yes. Crystal oscillators can be designed to minimize their phase noise characteristics. Special applications such as wireless require best phase noise both at far-end and close-end. Crystal parameters and mounting methods directly affect close-end phase noise 300Hz offset from carrier. The oscillator front-end and output buffer primarily control phase noise with offset frequency from carrier greater or equal to 1kHz.

A: The crystal oscillator is typically used as a master clock for the microprocessor and its parameters are not affected by the internal characteristics of the microprocessor such as variation in load capacitance and other variables that could affect the change in frequency at room and over temperature. The over all frequency stability in crystal oscillators is typically +100ppm max. and includes frequency calibration at 25°C, over temperature, frequency changes due to load, supply, aging, vibration, and shock.

Q: What is the start-up time?

A: Start-up time is the delay time between the oscillation starts from noise until it reaches its full output amplitude when power is applied. The supply voltage must be applied with a defined rate or rise. The start-up time varies from microseconds to milliseconds depending on frequency, ASIC speed and logic. Please see figure 1.

A: When the voltage at the control pin is set to a logic low "0",the out put is in Tri-state mode that is High Impedance. The disabled current is usually lower than its normal operating current but not completely cut-off as it was seen in the Stand-by mode, where the oscillation is shut down completely.There is an internal pull-up resistor between control pin and supply (typically 1ook Ohms), therefore the control pin can be left open (floating) if unused.

Q: What is jitter and how to specify its maximum value?

A: Jitter is noise caused by many sources in crystal oscillators. Major sources of noise are:

• Power supply noise.
• Integer multiples of the signal source frequency (harmonics).
• Load and termination conditions.
• Amplifier noise.
• Circuit configuration (PLLs, Multiplier, Overtone, etc.)

• Make sure that the power supply noise is filtered by using by pass capacitors, chip beads, or RC filters.
• If jitter is critical in some applications, especially for high- fre quencies noise, use low harmonics outputs or sine output.
• Make sure that load and termination conditions are optimized to avoid reflected power back to its output.
• Typically, PLLs, Multiplier or Programmable designs produce higher jitter than the conventional fundamental design.
  It is very important to understand the jitter requirements from the application to specify the right specification for crystal oscillators.

We can classify two types of jitters:
• Cycle to cycle jitter
• Period jitter.

CYCLE TO CYCLE JITTER

The Cycle to cycle jitter is the maximum difference in time between several measured periods. Usually a minimum of ten (10) cycles is used where T1 to T10 were recorded . See fig. 2.

The period jitter is the maximum change of a clock edge. It is usually expressed as peak-to-peak jitter and can be converted to rms value by multiplying to (0.5) x (0.707). The period jitter can only be measured at each cycle but not multiple cycles. See figure 3.
Typical jitter recorded in Abracon oscillators varies from 20ps to 60ps rms.

A: Phase noise is the expression of noise in the frequency domain. It is a measure of the short-term frequency fluctuations of the oscillator. It is usually specified as the single sideband power density in a 1 Hz bandwidth at a specified offset frequency from the carrier.
In order to measure phase noise, it is necessary to pair a similar device-under-test with one unit set a VCXO and other set a fixed XO. Please see block diagram in figure 4.

CMOS RISE AND FALL TIMES

The rise and fall time on the CMOS technology depends on its speed (CMOS, HCMOS, ACMOS, BICMOS), the supply voltage, the load capacitance, and the load configuration. Typical rise and fall time for CMOS 4000 series is 30ns, HCMOS is 6ns, and for ACMOS (HCMOS, TTL compatible) is 3 ns max.

Typical rise and fall time is measured between 10% to 90% of its waveform level.

Due to the fast transition time of the ACMOS (HCMOS/TTL compatible) device, proper termination techniques must be used when testing or measuring electrical performance characteristics.
Termination is usually used to solve the problem of voltage prreflection, which essential cause steps in clock waveforms as well as overshoot and undershoot. Such effect could result in false clocking of data, as well as higher EMI and system noise.

1. Series termination;
2. Pull-up/Pull-down termination;
3. Parallel-AC termination

METHOD 1:

METHOD 2:

METHOD 3: