WO2025179489A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置

Info

Publication number
WO2025179489A1
WO2025179489A1 PCT/CN2024/079057 CN2024079057W WO2025179489A1 WO 2025179489 A1 WO2025179489 A1 WO 2025179489A1 CN 2024079057 W CN2024079057 W CN 2024079057W WO 2025179489 A1 WO2025179489 A1 WO 2025179489A1
Authority
WO
WIPO (PCT)
Prior art keywords
sub
panel
scan line
gate drive
drive circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/079057
Other languages
English (en)
French (fr)
Other versions
WO2025179489A9 (zh
Inventor
张庆凯
林奕呈
孟秋华
时凌云
高博
王秀荣
颜森
岳焕新
李林凤
梁增
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Beijing BOE Technology Development Co Ltd
BOE MLED Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Beijing BOE Technology Development Co Ltd
BOE MLED Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Beijing BOE Technology Development Co Ltd, BOE MLED Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to PCT/CN2024/079057 priority Critical patent/WO2025179489A1/zh
Priority to CN202480000360.3A priority patent/CN120883266A/zh
Publication of WO2025179489A1 publication Critical patent/WO2025179489A1/zh
Publication of WO2025179489A9 publication Critical patent/WO2025179489A9/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel and a display device.
  • the gate drive circuit GOA drive scanning method of AM (actively driven) Mini/Micro LED (mini light-emitting diode or micro light-emitting diode) spliced displays starts scanning for each spliced module simultaneously. This causes the time difference between the scanning moments of the two rows of pixels at the seam between the upper and lower modules (the last row of pixels in the upper module and the first row of pixels in the lower module) to reach the duration of one scanning cycle (1 frame). Therefore, the time difference between the image display of the two rows of pixels at the seam between the upper and lower modules is also the duration of one scanning cycle.
  • the upper and lower modules are prone to image desynchronization (screen tearing), affecting display quality.
  • one frame includes one scanning period (1Frame) and one blank period (1blank).
  • one Frame is the time it takes for the gate drive circuit GOA of the module to scan from the first row to the last row.
  • the purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and provide a display panel and a display device so as to solve the problem of screen tearing of spliced display panels.
  • a display panel comprising at least two sub-panels sequentially spliced along a column direction;
  • any of the sub-panels includes sub-pixels distributed in an array and scan lines corresponding to each sub-pixel row;
  • the sub-panel has a plurality of gate driving circuits for driving the respective scan lines;
  • the last row of the previous sub-panel The start signal of the gate driving circuit to which the scan line is electrically connected is at the same time as the start signal of the gate driving circuit to which the scan line in the first row of the subsequent sub-panel is electrically connected.
  • the display panel includes two sub-panels.
  • the sub-panel includes two gate driving circuits.
  • m gate driving circuits are provided on the sub-panel; m is a positive integer greater than 1;
  • the scan lines are divided into a plurality of sequentially adjacent scan line groups, each scan line group comprising m sequentially adjacent scan lines;
  • the m scan lines in the same scan line group are respectively driven by m gate driving circuits.
  • the gate driving circuits each include a plurality of shift registers cascaded in sequence
  • the jth scan line in the i-th scan line group is electrically connected to the i-th shift register of the j-th gate driving circuit; j is a positive integer between 1 and m.
  • the gate driving circuit includes a plurality of shift registers cascaded in sequence
  • the first reference gate driving circuit of the sub-panel is a gate driving circuit that drives the last row of scan lines of the sub-panel;
  • the second reference gate driving circuit of the sub-panel is a gate driving circuit that drives the first row of scan lines of the sub-panel;
  • the input end of the first stage shift register of the first reference gate driving circuit of the former sub-panel is electrically connected to the input end of the first stage shift register of the second reference gate driving circuit of the latter sub-panel.
  • the display panel includes a first sub-panel and a second sub-panel sequentially spliced along a column direction;
  • the first sub-panel has a first gate driving circuit and a second gate driving circuit for driving each of the scan lines; the first gate driving circuit is used to drive the odd-numbered scan lines of the first sub-panel, and the second gate driving circuit is used to drive the even-numbered scan lines of the first sub-panel;
  • the second sub-panel has a third gate driving circuit for driving each of the scan lines and a fourth gate driving circuit; the third gate driving circuit is used to drive the odd-numbered scan lines of the second sub-panel, and the fourth gate driving circuit is used to drive the even-numbered scan lines of the second sub-panel.
  • the number of scan lines of the sub-panel is an even number; the start signal of the second gate driving circuit of the first sub-panel and the start signal of the third gate driving circuit of the second sub-panel are at the same time.
  • the number of scan lines of the sub-panel is an odd number; the start signal of the first gate driving circuit of the first sub-panel and the start signal of the third gate driving circuit of the second sub-panel are at the same time.
  • a start time of the start signal of the first gate driving circuit is earlier than a start time of the start signal of the second gate driving circuit by half a scanning cycle.
  • the sub-panel has a light emitting control trace corresponding to each sub-pixel row, and the light emitting control trace is used to load a light emitting control signal to the pixel driving circuit;
  • the light-emitting control wirings are electrically connected to each other.
  • the display panel is a Mini LED display panel, a Micro LED display panel, an OLED display panel, a QLED display panel or an LCD display panel.
  • a display device comprising the above-mentioned display panel.
  • FIG1 is a schematic diagram of a display panel in one embodiment of the present disclosure.
  • FIG2 is a schematic diagram of a sub-panel in one embodiment of the present disclosure.
  • FIG3 is a schematic diagram of a film layer of a sub-panel in one embodiment of the present disclosure.
  • FIG4 is a schematic diagram of a film layer of a sub-panel in one embodiment of the present disclosure.
  • FIG5 is a schematic diagram of a film layer of a sub-pixel in one embodiment of the present disclosure.
  • FIG6 is a schematic diagram of a film layer of a sub-pixel in one embodiment of the present disclosure.
  • FIG7 is a schematic diagram of a film layer of a sub-pixel in one embodiment of the present disclosure.
  • FIG8 is a schematic diagram of a film layer of a sub-pixel in one embodiment of the present disclosure.
  • FIG9 is a schematic structural diagram of a display panel in one embodiment of the present disclosure.
  • FIG. 10 is a timing diagram corresponding to scan lines of each sub-pixel row of the display panel in FIG. 9 in one embodiment of the present disclosure.
  • FIG11 is a schematic structural diagram of a display panel in one embodiment of the present disclosure.
  • FIG. 12 is a timing diagram corresponding to scan lines of each sub-pixel row of the display panel in FIG. 11 in one embodiment of the present disclosure.
  • FIG13 is a timing diagram of a start signal in one embodiment of the present disclosure.
  • FIG14 is a timing diagram of simultaneously loading light-emitting control signals on each sub-pixel row in one embodiment of the present disclosure.
  • AA display area
  • BB peripheral area
  • Buff inorganic buffer layer
  • CFL color filter layer
  • CGL Charge generation layer
  • COML common electrode layer
  • CVD1 first inorganic encapsulation layer
  • CVD2 second inorganic encapsulation layer
  • DBP driving backplane
  • DH row direction
  • DL data line
  • DRL driving layer
  • DV column square
  • EBL electron blocking layer
  • EFL light-emitting functional layer
  • EFU light-emitting functional unit
  • EIL electron injection layer
  • ELS light-emitting stack structure
  • EML organic light-emitting layer
  • ETL electron transport layer
  • GI gate insulating layer
  • GOA gate drive circuit
  • GOA1 first gate drive circuit
  • GOA3 third gate drive circuit
  • GOA4 fourth gate drive circuit
  • GT gate layer
  • HBL
  • a transistor refers to an element including at least three terminals: a gate, a source, and a drain.
  • the transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the source, the channel region, and the drain.
  • the channel region refers to the region through which current mainly flows.
  • the functions of the "source” and the “drain” are sometimes interchanged, that is, the "source” and the “drain” can be interchanged.
  • one of the "source” and the “drain” is referred to as the first pole of the transistor, and the other is referred to as the second pole of the transistor, and the gate is referred to as the control terminal of the transistor.
  • at least part of the signal has a high level and a low level; one of the high level and the low level can be used as the on-level of the signal, and the on-level of the signal can turn on the controlled transistor; the other of the high level and the low level can be used as the off-level of the signal, and the off-level of the signal can turn off the controlled transistor.
  • a signal that controls a P-type transistor the signal can be loaded to the control terminal of the P-type transistor
  • its on-level is a low level
  • its off-level is a high level
  • a signal controlling an N-type transistor the signal can be applied to the control terminal of the N-type transistor
  • its on-level is a high level
  • its off-level is a low level.
  • Structural layer A is located on the side of structural layer B facing away from the substrate SBT. This means that structural layer A is formed on the side of structural layer B facing away from the substrate SBT.
  • structural layer B is a patterned structure, part of structural layer A may be located at the same physical height as structural layer B or lower than the physical height of structural layer B, with the substrate SBT serving as a height reference.
  • the present disclosure provides a display device, including a display panel PNL.
  • the display device can be any product or component with a display function, such as a TV, an all-in-one conference machine, or an advertising screen.
  • the display panel PNL is a display panel PNL with a display size of not less than 80 inches, and in particular, a display panel PNL with a display size of not less than 100 inches.
  • the display panel PNL can also be a small or medium-sized display panel PNL, such as a direct-display Mini LED display panel or a direct-display Micro LED display panel.
  • the display panel PNL includes at least two sub-panels SPNL sequentially spliced along a column direction. In this way, a larger display panel PNL can be formed using smaller sub-panels SPNL, thereby reducing the cost of the display panel PNL.
  • the sub-panel SPNL includes a display area AA and a peripheral area BB located at least on one side of the display area AA.
  • the sub-panel SPNL is provided with array-distributed display units, each of which includes a sub-pixel PIX and a pixel driving circuit PDC for driving the sub-pixel PIX.
  • BB does not have a display unit, or the display unit is not used to display images.
  • the sub-panel SPNL is provided with a plurality of scan lines GL extending along the row direction DH in the display area AA, and each scan line GL is provided in a one-to-one correspondence with each display unit row.
  • the pixel driving circuit PDC of each display unit in the display unit row is electrically connected to the corresponding scan line GL.
  • the sub-panel SPNL is also provided with a plurality of data lines DL extending along the column square DV in the display area AA, and each data line DL is provided in a one-to-one correspondence with each display unit column.
  • the pixel driving circuit PDC of each display unit in the display unit column is electrically connected to the corresponding data line DL.
  • the pixel driving circuit PDC of each display unit is connected to one scan line GL and one data line DL.
  • the driving voltage loaded on the data line DL can be written into the pixel driving circuit PDC, thereby causing the sub-pixel PIX to emit light.
  • the pixel drive circuit PDC includes at least a data write transistor, a drive transistor and a storage capacitor, and the control terminal of the drive transistor can be electrically connected to an electrode plate of the storage capacitor.
  • the source of the data write transistor can be electrically connected to the data line DL, and the control terminal of the data write transistor can be electrically connected to the scan line GL.
  • the pixel drive circuit PDC is configured so that when a scan signal is loaded on the scan line GL, the data write transistor is turned on, thereby causing the drive voltage on the data line DL to be written to the control terminal and storage capacitor of the drive transistor. When the data write transistor is turned off, the drive voltage can be maintained by the storage capacitor.
  • the drive transistor can output a drive current to drive the sub-pixel PIX to emit light under the control of the voltage on its control terminal.
  • the pixel drive circuit PDC of the embodiment of the present disclosure may also include other transistors or capacitors to enable the pixel drive circuit PDC to have better driving performance.
  • the pixel drive circuit PDC can be a pixel drive circuit of 7T1C (7 thin film transistors TFT and a storage capacitor), 8T1C (8 thin film transistors TFT and a storage capacitor) or other architectures.
  • the sub-pixel PIX can be a current-driven self-luminous element, for example, it can be any one of OLED, QLED, Micro LED, Mini LED and other light-emitting elements.
  • the sub-pixel PIX can include sub-pixels PIX of multiple different colors, for example, a red sub-pixel for emitting red light, a blue sub-pixel for emitting green light and a green sub-pixel for emitting green light.
  • the sub-pixels PIX in the display area AA can also have sub-pixels PIX of other colors (for example, sub-pixels PIX for emitting green light). a yellow sub-pixel for emitting yellow light, a cyan sub-pixel for emitting cyan light, a white sub-pixel for emitting white light, etc.).
  • the sub-panel SPNL may include a base substrate SBT, a driving layer DRL, and a pixel layer PIXL stacked in sequence.
  • Sub-pixels PIX are provided in the pixel layer PIXL, and the driving layer DRL is provided with a pixel driving circuit PDC for driving the sub-pixels PIX; each sub-pixel PIX can emit light to display a picture under the drive of the pixel driving circuit PDC.
  • the sub-pixel PIX is a thin-film self-luminous element, such as an OLED, QLED, PLED or other light-emitting element.
  • the sub-panel SPNL further includes an encapsulation layer located on the side of the pixel layer PIXL away from the base substrate SBT, which can encapsulate and protect the pixel layer PIXL.
  • the encapsulation layer is a thin-film encapsulation layer TFE.
  • the display panel PNL may also be other types of panels.
  • the display panel PNL may be a Mini LED display panel, a Micro LED display panel, or other display panels.
  • the film layer structure of the sub-panel SPNL may differ from the example shown in FIG3 .
  • the PNL may also be an LCD display panel; in such an LCD display panel PNL, the structure of the sub-panel SPNL also differs from the example shown in FIG3 .
  • the film structure and spacing of the sub-panel SPNL are exemplarily described by taking the sub-pixel PIX of the display panel PNL as a thin-film self-luminous element as an example.
  • the substrate substrate SBT can be a substrate substrate SBT of an inorganic material, or a substrate substrate SBT of an organic material; of course, it can also be a composite substrate formed by stacking a substrate substrate SBT of an inorganic material and a substrate substrate SBT of an organic material.
  • the material of the substrate substrate SBT can be a glass material such as soda-lime glass, quartz glass, sapphire glass, etc.
  • the material of the substrate substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or a combination thereof.
  • the substrate substrate SBT can also be a flexible substrate substrate SBT, for example, the material of the substrate substrate SBT can include polyimide.
  • any pixel driving circuit PDC may include a thin film transistor TFT and a storage capacitor. Further, the thin film transistor TFT may be selected from the top
  • the material of the active layer of the thin film transistor TFT can be amorphous silicon semiconductor material, low-temperature polycrystalline silicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material or other types of semiconductor materials; the thin film transistor TFT can be an N-type thin film transistor TFT or a P-type thin film transistor TFT.
  • the types of any two transistors may be the same or different.
  • some transistors may be N-type transistors and some transistors may be P-type transistors.
  • the material of the active layer of some transistors may be a low-temperature polysilicon semiconductor material, and the material of the active layer of some transistors may be a metal oxide semiconductor material.
  • the thin film transistor TFT is a low-temperature polysilicon transistor. In some other embodiments of the present disclosure, some thin film transistors TFT are low-temperature polysilicon transistors, and some thin film transistors TFT are metal oxide transistors.
  • the driving layer DRL may include a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source/drain metal layer SD, a planarization layer PLN, etc. stacked between the substrate SBT and the pixel layer PIXL.
  • Each thin film transistor TFT and the storage capacitor may be formed by film layers such as the semiconductor layer SCL, the gate insulating layer GI, the gate layer GT, the interlayer dielectric layer ILD, the source/drain metal layer SD, etc. The positional relationship of each film layer may be determined according to the film layer structure of the thin film transistor TFT.
  • the semiconductor layer SCL may be used to form the channel region of the transistor, and may also be formed into partial wiring or conductive structure by conductorization when necessary.
  • the gate layer may be used to form one or more gate layer wirings such as scan wiring, reset control wiring, and light emission control wiring, may also be used to form the control terminal of the transistor, and may also be used to form part or all of the electrode plates of the storage capacitor.
  • the source/drain metal layer may be used to form source/drain metal layer wirings such as data wiring and drive power supply voltage wiring, and may also be used to form part of the electrode plates of the storage capacitor.
  • the driving layer DRL may further include other film layers as needed, for example, it may further include a light shielding layer located between the semiconductor layer SCL and the substrate SBT.
  • any of the above-mentioned film layers such as the semiconductor layer SCL, the gate layer GT, and the source/drain metal layer SD may also be multi-layered.
  • the driving layer DRL may include two different semiconductor layers SCL, or two or three source/drain metal layers.
  • the insulating film layers in the driving layer DRL can be adaptively increased or decreased, or new insulating film layers can be added as needed.
  • the driving layer DRL may further include a passivation layer.
  • the passivation layer may be provided on a surface of the source/drain metal layer SD away from the substrate SBT, so as to protect the source/drain metal layer SD.
  • the driving layer DRL may include an inorganic buffer layer Buff, a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source/drain metal layer SD, and a planarization layer PLN stacked in sequence, and the thin film transistor TFT formed in this way is a top-gate thin film transistor TFT.
  • the sub-pixel PIX in the pixel layer PIXL is a thin-film light-emitting element, which may include two stacked electrodes and a light-emitting functional unit EFU sandwiched between the two electrodes.
  • the pixel layer PIXL may include a pixel electrode layer PEL, a light-emitting functional layer EFL, and a common electrode layer COML, which are stacked in sequence.
  • the pixel electrode layer PEL includes multiple pixel electrodes PE in the display area of the sub-panel SPNL.
  • the portion of the light-emitting functional layer EFL connected to the pixel electrodes PE serves as the light-emitting functional unit EFU of the sub-pixel PIX.
  • the common electrode layer COML serves as a common electrode electrically connected to the light-emitting functional unit EFU of each sub-pixel PIX.
  • the pixel layer PIXL may also include a pixel definition layer PDL located between the pixel electrode layer PEL and the light-emitting functional layer EFL.
  • the pixel definition layer PDL has a plurality of through pixel openings arranged in a one-to-one correspondence with the plurality of pixel electrodes PE, and any pixel opening exposes at least a portion of the corresponding pixel electrode.
  • the pixel definition layer PDL covers the edge of the pixel electrode PE and exposes at least a portion of the internal area of the pixel electrode PE, so that the pixel definition layer PDL can effectively define the actual effective area of the pixel electrode PE (the area directly connected to the light-emitting functional unit EFU), and further define the light-emitting area and light-emitting area of the sub-pixel PIX.
  • the light-emitting functional layer EFL at least covers the pixel electrode PE exposed by the pixel definition layer PDL.
  • the common electrode layer COML can cover the light-emitting functional layer EFL in the display area.
  • the pixel electrode PE and the common electrode layer COML provide carriers such as electrons and holes to the light-emitting functional layer EFL, so that the light-emitting functional layer EFL emits light.
  • the portion of the light-emitting functional layer EFL located between the pixel electrode PE and the common electrode layer COML can serve as a light-emitting functional unit EFU.
  • the pixel electrode PE, the common electrode layer COML and the pixel electrode PE can serve as a light-emitting functional unit EFU.
  • the electrode layer COML and the light emitting functional unit EFU form a sub-pixel PIX, wherein one of the pixel electrode PE and the common electrode layer COML serves as an anode of the sub-pixel PIX, and the other serves as a cathode of the sub-pixel PIX.
  • the pixel electrode PE serves as an anode of the sub-pixel PIX
  • the common electrode layer COML serves as a cathode of the sub-pixel PIX
  • the light-emitting functional unit may include an organic light-emitting layer (EML), and may include one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).
  • the organic light-emitting layer (EML) may include a light-emitting layer host material and a light-emitting layer guest material.
  • the light-emitting layer guest material may be a fluorescent dopant or a phosphorescent dopant, and in particular, may be a thermally activated delayed fluorescent material.
  • a charge generation layer CGL
  • CGL charge generation layer
  • the light-emitting functional unit EFU may include a quantum dot layer QDL, and may include one or more of a hole injection layer HIL, an electron transport layer ETL, an electron blocking layer EBL, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL.
  • the quantum dot layer QDL may include quantum dot particles, which may be interconnected via surface modification groups.
  • a charge generation layer CGL may also be provided in the light-emitting functional unit EFU.
  • the light-emitting functional unit EFU may include a single light-emitting stack structure ELS, or may include a stack of multiple light-emitting stack structures ELS.
  • a charge generation layer CGL may be provided between two adjacent light-emitting stack structures ELS.
  • Each light-emitting stack structure ELS is provided with one or more light-emitting layers, which may be either an organic light-emitting layer EML or a quantum dot layer QDL.
  • the thin film encapsulation layer TFE can be provided on the surface of the pixel layer PIXL away from the substrate SBT, which can include inorganic encapsulation layers and organic encapsulation layers alternately stacked.
  • the inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the pixel layer PIXL and Causes aging of the material in the pixel layer PIXL.
  • the edge of the inorganic encapsulation layer may be located in the peripheral area.
  • the organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce the stress between the inorganic encapsulation layers.
  • the edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer.
  • the thin film encapsulation layer TFE includes a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2 sequentially stacked on the side of the pixel layer PIXL away from the substrate SBT.
  • the sub-panel SPNL may not be provided with a thin film encapsulation layer, but may use other methods to encapsulate and protect the pixel layer.
  • the sub-panel SPNL may further include a touch function layer TSL.
  • the touch function layer TSL may be disposed on a side of the thin film encapsulation layer TFE away from the driving backplane DBP, so that the sub-panel SPNL has a touch function.
  • the sub-panel SPNL may further include a color filter layer CFL.
  • the color filter layer CFL may be disposed on a side of the thin film encapsulation layer TFE away from the driving backplane DBP to reduce reflection of ambient light and improve display quality.
  • the display panel PNL includes at least two sub-panels SPNL sequentially spliced along the column direction. Any one of the sub-panels SPNL includes array-distributed sub-pixels PIX and scan lines GL corresponding to each sub-pixel row.
  • the sub-pixels PIX are provided with the above-mentioned pixel driving circuit PDC, and the pixel driving circuit PDC is used to drive the sub-pixels PIX; the sub-panel SPNL has a plurality of gate driving circuits GOA for driving each of the scan lines GL.
  • the start signal of the gate driving circuit GOA electrically connected to the scan line GL in the last row of the previous sub-panel SPNL is the same as the start signal of the gate driving circuit GOA electrically connected to the scan line GL in the first row of the next sub-panel SPNL.
  • the "previous” and “next” mentioned in this embodiment refer to the upper and lower positional relationship between two adjacent sub-panels SPNL.
  • the previous sub-panel SPNL may refer to the sub-panel SPNL located at the top
  • the next sub-panel SPNL may refer to the sub-panel SPNL located at the bottom
  • the two sub-panels SPNL are spliced in sequence.
  • the timing of the start signal is the same, which may mean that the input terminals of the two gate drive circuits GOA share the same start signal or the input terminals of the two gate drive circuits GOA are connected to the start signal. The timing of the start signal is the same.
  • the display panel PNL includes two sub-panels SPNL.
  • the sub-panel SPNL includes two gate driving circuits GOA, which drive the scan lines GL, thereby facilitating separate scanning of odd and even rows of the scan lines GL of the sub-panel SPNL.
  • m gate drive circuits GOA are set on the sub-panel SPNL; m is a positive integer greater than 1, for example, m can be a positive integer such as 2, 3, 4, etc.; the scan line GL is divided into a plurality of sequentially adjacent scan line groups GLS, and the scan line group GLS includes m sequentially adjacent scan lines GL; the m scan lines GL in the same scan line group GLS are respectively driven by m gate drive circuits GOA.
  • the number of gate driving circuits GOA on the same sub-panel SPNL may be two, three, four, etc.
  • the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2 which are sequentially spliced in the column direction.
  • the number of scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 is 180 rows, and the first sub-panel SPNL1 is located above the second sub-panel SPNL2.
  • the first sub-panel SPNL1 is provided with a first gate drive circuit GOA1 and a second gate drive circuit GOA2
  • the second sub-panel SPNL2 is provided with a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4.
  • two gate drive circuits GOA are provided on the first sub-panel SPNL1 and the second sub-panel SPNL2.
  • the scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 are respectively divided into 90 adjacent rows.
  • the scan line group GLS includes two scan lines GL that are sequentially adjacent to each other.
  • the scan line group GLS includes a first scan line GL1 and a second scan line GL2 that are sequentially adjacent to each other.
  • the two scan lines GL in the same scan line group GLS are driven by two gate driving circuits GOA respectively, that is, in the first sub-panel SPNL1, the first scan line GL1 in the same scan line group GLS is driven by the first gate driving circuit GOA1, and the second scan line GL2 in the same scan line group GLS is driven by the second gate driving circuit GOA2; in the second sub-panel SPNL2, the first scan line GL1 in the same scan line group GLS is driven by the third gate driving circuit GOA3, and the second scan line GL2 in the same scan line group GLS is driven by the fourth gate driving circuit GOA4, so as to realize the separate scanning of the odd and even row scan lines GL of the same sub-panel SPNL through the two gate driving circuits GOA, so that the scanning time difference between the 180th row scan line GL of the first sub-panel SPNL1 and the first row scan line GL of the second sub-panel SPNL2 is half of the scanning period of the sub-panel SPNL, which is beneficial to solve the screen
  • the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2, which are sequentially spliced along the column direction.
  • the number of scan lines GL in the first sub-panel SPNL1 and the second sub-panel SPNL2 is 179 rows, and the first sub-panel SPNL1 is located above the second sub-panel SPNL2.
  • the first sub-panel SPNL1 is provided with a first gate drive circuit GOA1 and a second gate drive circuit GOA2
  • the second sub-panel SPNL2 is provided with a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4.
  • the first sub-panel SPNL1 and the second sub-panel SPNL2 are each provided with two gate drive circuits GOA.
  • the scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 are respectively divided into 90 sequentially adjacent scan line groups GLS, the first 89 scan line groups GLS include two sequentially adjacent scan lines GL, in other words, the first 89 scan line groups GLS include a first scan line GL1 and a second scan line GL2 that are sequentially adjacent; the 90th scan line group GLS includes one scan line GL, in other words, the 90th scan line group GLS includes a first scan line GL1.
  • the two scan lines GL in the same scan line group GLS are driven by two gate drive circuits GOA respectively, that is, in the first sub-panel SPNL1, the first scan line GL1 in the same scan line group GLS is driven by the first gate drive circuit GOA1, and the second scan line GL2 in the same scan line group GLS is driven by the second gate drive circuit GOA2; in the second sub-panel SPNL2, the first scan line GL1 in the same scan line group GLS is driven by the second gate drive circuit GOA2.
  • the third gate driving circuit GOA3 It is driven by the third gate driving circuit GOA3, and the second scanning line GL2 in the same scanning line group GLS is driven by the fourth gate driving circuit GOA4; and in the first sub-panel SPNL1, the first scanning line GL1 in the 90th scanning line group GLS is driven by the first gate driving circuit GOA1; in the second sub-panel SPNL2, the first scanning line GL1 in the 90th scanning line group GLS is driven by the third gate driving circuit GOA3, so as to realize the separate scanning of the odd and even row scanning lines GL of the same sub-panel SPNL through the two gate driving circuits GOA, so that the scanning time difference between the 179th row scanning line GL of the first sub-panel SPNL1 and the first row scanning line GL of the second sub-panel SPNL2 is half of the scanning period of the sub-panel SPNL, which is beneficial to solve the screen tearing phenomenon of the spliced display panel PNL, so as to improve the display quality.
  • m can be 3.
  • three gate drive circuits GOA can be used to achieve independent scanning of the odd and even scan lines GL of the same sub-panel SPNL. That is, each scan line group GLS includes three scan lines GL, and the three scan lines GL are driven by three gate drive circuits GOA, respectively.
  • the scanning time difference between the last scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 is one-third of the scanning period of the sub-panel SPNL.
  • m can be 4.
  • four gate drive circuits GOA can be used to achieve independent scanning of the odd and even scan lines GL of the same sub-panel SPNL.
  • the scanning time difference between the last scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 is one-quarter of the scanning period of the sub-panel SPNL.
  • the gate drive circuits GOA each include a plurality of shift registers SR cascaded in sequence.
  • the j-th scan line GL in the i-th scan line group GLS is electrically connected to the i-th shift register SR of the j-th gate drive circuit GOA;
  • i is a positive integer, for example, i can be a positive integer of 1, 2, 3, etc.;
  • j is a positive integer between 1 and m, for example, j can be a positive integer of 1, 2, 3, ..., m.
  • the multiple gate drive circuits GOA on the sub-panel SPNL operate in sequence according to a preset order; wherein the output end of the last shift register SR of the gate drive circuit GOA that works first is connected to the input end of the first shift register SR of the gate drive circuit GOA that works subsequently.
  • the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2 sequentially spliced in a column direction.
  • the number of scan lines GL in the first sub-panel SPNL1 and the second sub-panel SPNL2 is 180 rows, and the first sub-panel SPNL1 is located above the second sub-panel SPNL2.
  • the first sub-panel SPNL1 is provided with a first gate driver.
  • the second sub-panel SPNL2 is provided with a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4.
  • each gate drive circuit GOA includes 90 shift registers SR connected in cascade, that is, each gate drive circuit GOA includes a first shift register SR1, a second shift register SR2, a third shift register SR3, ..., a ninetieth shift register SR90 connected in cascade.
  • the scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 are respectively divided into 90 adjacent scan line groups GLS.
  • the scan line group GLS includes two adjacent scan lines GL.
  • the scan line group GLS includes a first scan line GL1 and a second scan line GL2 that are adjacent to each other.
  • the two scan lines GL in the same scan line group GLS are driven by two gate drive circuits GOA respectively.
  • the first scan line GL1 in the first scan line group GLS is electrically connected to the first shift register SR1 of the first gate drive circuit GOA1
  • the second scan line GL2 in the first scan line group GLS is electrically connected to the first shift register SR1 of the second gate drive circuit GOA2
  • the first scan line GL1 in the second scan line group GLS is electrically connected to the second shift register SR2 of the first gate drive circuit GOA1
  • the second scan line GL2 in the second scan line group GLS is electrically connected to the second shift register SR2 of the second gate drive circuit GOA2.
  • the second shift register SR2 of the gate drive circuit GOA2 is electrically connected, the first scan line GL1 in the third scan line group GLS is electrically connected to the third shift register SR3 of the first gate drive circuit GOA1, the second scan line GL2 in the third scan line group GLS is electrically connected to the third shift register SR3 of the second gate drive circuit GOA2,..., the first scan line GL1 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the first gate drive circuit GOA1, and the second scan line GL2 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the second gate drive circuit GOA2.
  • the first scan line GL1 in the first scan line group GLS is electrically connected to the first shift register SR1 of the third gate drive circuit GOA3
  • the second scan line GL2 in the first scan line group GLS is electrically connected to the first shift register SR1 of the fourth gate drive circuit GOA4
  • the first scan line GL1 in the second scan line group GLS is electrically connected to the second shift register SR2 of the third gate drive circuit GOA3
  • the second scan line GL2 in the second scan line group GLS is electrically connected to the second shift register SR2 of the fourth gate drive circuit GOA4
  • the first scan line GL1 in the third scan line group GLS is electrically connected to the third gate drive circuit GOA3.
  • the third shift register SR3 of the drive circuit GOA3 is electrically connected, the second scan line GL2 in the third scan line group GLS is electrically connected to the third shift register SR3 of the fourth gate drive circuit GOA4, ..., the first scan line GL1 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the third gate drive circuit GOA3, and the second scan line GL2 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the fourth gate drive circuit GOA4.
  • the odd and even scan lines GL of the same sub-panel SPNL can be scanned separately by the two gate drive circuits GOA, so that the scanning time difference between the 180th scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 is half of the scanning period of the sub-panel SPNL, which is beneficial to solving the screen tearing phenomenon of the spliced display panel PNL and improving the display quality.
  • the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2, which are sequentially spliced along the column direction.
  • the number of scan lines GL in the first sub-panel SPNL1 and the second sub-panel SPNL2 is 179 rows, and the first sub-panel SPNL1 is located above the second sub-panel SPNL2.
  • the first sub-panel SPNL1 is provided with a first gate drive circuit GOA1 and a second gate drive circuit GOA2
  • the second sub-panel SPNL2 is provided with a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4.
  • the first gate drive circuit GOA1 and the third gate drive circuit GOA3 both include 90 shift registers SR connected in cascade, that is, the first gate drive circuit GOA1 and the third gate drive circuit GOA3 both include a first shift register SR1, a second shift register SR2, a third shift register SR3, ..., a ninetieth shift register SR90 connected in cascade, and the second gate drive circuit GOA2 and the fourth gate drive circuit GOA4 both include 89 shift registers SR connected in cascade, that is, the second gate drive circuit GOA2 and the fourth gate drive circuit GOA4 both include a first shift register SR1, a second shift register SR2, a third shift register SR3, ..., a ninetieth shift register SR90 connected in cascade.
  • the first sub-panel SPNL1 and the second sub-panel SPNL2 are divided into 90 scan line groups GLS, wherein the first 89 scan line groups GLS include two scan lines GL that are adjacent to each other.
  • the first 89 scan line groups GLS include a first scan line GL1 and a second scan line GL2 that are adjacent to each other.
  • the 90th scan line group GLS includes one scan line GL.
  • the 90th scan line group GLS includes the first scan line GL1.
  • the same scan line The two scan lines GL in the group GLS are driven by two gate drive circuits GOA respectively.
  • the first scan line GL1 in the first scan line group GLS is electrically connected to the first shift register SR1 of the first gate drive circuit GOA1
  • the second scan line GL2 in the first scan line group GLS is electrically connected to the first shift register SR1 of the second gate drive circuit GOA2
  • the first scan line GL1 in the second scan line group GLS is electrically connected to the second shift register SR2 of the first gate drive circuit GOA1
  • the second The second scan line GL2 in the scan line group GLS is electrically connected to the second shift register SR2 of the second gate drive circuit GOA2
  • the first scan line GL1 in the third scan line group GLS is electrically connected to the third shift register SR3 of the first gate drive circuit GOA1
  • the second scan line GL2 in the third scan line group GLS is electrically connected to the third shift register SR3 of the second gate drive circuit GOA2,...
  • the first scan line GL1 in the 90th scan line group GLS is electrically connected to the first shift
  • the first scan line GL1 in the first scan line group GLS is electrically connected to the first shift register SR1 of the third gate drive circuit GOA3, the second scan line GL2 in the first scan line group GLS is electrically connected to the first shift register SR1 of the fourth gate drive circuit GOA4, the first scan line GL1 in the second scan line group GLS is electrically connected to the second shift register SR2 of the third gate drive circuit GOA3, the second scan line GL2 in the second scan line group GLS is electrically connected to the second shift register SR2 of the fourth gate drive circuit GOA4, the first scan line GL1 in the third scan line group GLS is electrically connected to the third shift register SR3 of the third gate drive circuit GOA3, the second scan line GL2 in the third scan line group GLS is electrically connected to the third shift register SR3 of the fourth gate drive circuit GOA4,..., the first scan line GL1 in the 90th scan line group GLS is electrically connected to the ninetieth shift
  • the scanning time difference between the 179th row scan line GL of the first sub-panel SPNL1 and the first row scan line GL of the second sub-panel SPNL2 is half of the scanning period of the sub-panel SPNL, which is beneficial to solve the screen tearing phenomenon of the spliced display panel PNL and improve the display quality.
  • the gate drive circuit GOA includes a plurality of shift registers SR cascaded in sequence; in two adjacent sub-panels SPNL, the input terminal of the first stage shift register SR of the first reference gate drive circuit of the previous sub-panel SPNL is It is electrically connected to the input end of the first-stage shift register SR of the second reference gate drive circuit of the latter sub-panel SPNL; the first reference gate drive circuit of the sub-panel SPNL is the gate drive circuit GOA that drives the last row of scan lines GL of the sub-panel SPNL; the second reference gate drive circuit of the sub-panel SPNL is the gate drive circuit GOA that drives the first row of scan lines GL of the sub-panel SPNL.
  • the first reference gate drive circuit is the second gate drive circuit GOA2
  • the second reference gate drive circuit is the third gate drive circuit GOA3
  • the input end of the first shift register SR1 of the second gate drive circuit GOA2 is electrically connected to the input end of the first shift register SR1 of the third gate drive circuit GOA3, so that the start signal of the second gate drive circuit GOA2 is multiplexed as the start signal of the third gate drive circuit GOA3.
  • the number of wiring is reduced, so that the odd-numbered scan lines GL of the first sub-panel SPNL1 and the even-numbered scan lines GL of the second sub-panel SPNL2 are scanned at the same time, and the even-numbered scan lines GL of the first sub-panel SPNL1 and the odd-numbered scan lines GL of the second sub-panel SPNL2 are scanned at the same time, so that the scanning time difference between the 180th scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 is half of the scanning period of the sub-panel SPNL, which is beneficial to solve the screen tearing phenomenon of the spliced display panel PNL and improve the display quality.
  • the first reference gate drive circuit is the first gate drive circuit GOA1
  • the second reference gate drive circuit is the third gate drive circuit GOA3
  • the input end of the first shift register SR1 of the first gate drive circuit GOA1 is electrically connected to the input end of the first shift register SR1 of the third gate drive circuit GOA3, so that the start signal of the first gate drive circuit GOA1 is multiplexed as the start signal of the third gate drive circuit GOA3.
  • the number of wiring is reduced, so that the odd-numbered scan lines GL of the first sub-panel SPNL1 and the odd-numbered scan lines GL of the second sub-panel SPNL2 are scanned at the same time, and the even-numbered scan lines GL of the first sub-panel SPNL1 and the even-numbered scan lines GL of the second sub-panel SPNL2 are scanned at the same time, so that the scanning time difference between the 179th row scan line GL of the first sub-panel SPNL1 and the first row scan line GL of the second sub-panel SPNL2 is half of the scanning period of the sub-panel SPNL, which is beneficial to solve the screen tearing phenomenon of the spliced display panel PNL and improve the display quality.
  • the display panel PNL It includes a first sub-panel SPNL1 and a second sub-panel SPNL2 which are spliced in sequence along the column direction;
  • the first sub-panel SPNL1 has a first gate drive circuit GOA1 and a second gate drive circuit GOA2 for driving each of the scan lines GL;
  • the first gate drive circuit GOA1 is used to drive the odd-numbered scan lines GL of the first sub-panel SPNL1, and the second gate drive circuit GOA2 is used to drive the even-numbered scan lines GL of the first sub-panel SPNL1;
  • the second sub-panel SPNL2 has a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4 for driving each of the scan lines GL;
  • the third gate drive circuit GOA3 is used to drive the odd-numbered scan lines GL of the second sub-panel SPNL2, and the fourth gate drive circuit GOA4 is used to drive the even-numbered scan lines GL of the second sub-panel SPNL2.
  • the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2 that are sequentially spliced along the column direction.
  • the number of scan lines GL in the first sub-panel SPNL1 and the second sub-panel SPNL2 is 180 rows, and the first sub-panel SPNL1 is located above the second sub-panel SPNL2.
  • the first sub-panel SPNL1 is provided with a first gate drive circuit GOA1 and a second gate drive circuit GOA2
  • the second sub-panel SPNL2 is provided with a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4.
  • the scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 are each divided into 90 sequentially adjacent scan line groups GLS.
  • the scan line group GLS includes two sequentially adjacent scan lines GL.
  • the scan line group GLS includes a first scan line GL1 and a second scan line GL2 that are sequentially adjacent.
  • the two scan lines GL in the same scan line group GLS are driven by two gate drive circuits GOA respectively, that is, in the first sub-panel SPNL1, the first scan line GL1 in the same scan line group GLS is driven by the first gate drive circuit GOA1, and the second scan line GL2 in the same scan line group GLS is driven by the second gate drive circuit GOA2; in the second sub-panel SPNL2, the first scan line GL1 in the same scan line group GLS is driven by the third gate drive circuit GOA3, and the second scan line GL2 in the same scan line group GLS is driven by the fourth gate drive circuit GOA4.
  • the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2 sequentially spliced in the column direction.
  • the number of scan lines GL in the first sub-panel SPNL1 and the second sub-panel SPNL2 is 179 rows.
  • the first sub-panel SPNL1 is located above the second sub-panel SPNL2.
  • the first sub-panel SPNL1 is provided with a first gate drive circuit GOA1 and a second gate drive circuit GOA2, and the second sub-panel SPNL2 is provided with a third gate drive circuit GOA1.
  • the scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 are respectively divided into 90 sequentially adjacent scan line groups GLS, the first 89 scan line groups GLS include two sequentially adjacent scan lines GL, in other words, the first 89 scan line groups GLS include a first scan line GL1 and a second scan line GL2 that are sequentially adjacent, and the 90th scan line group GLS includes one scan line GL, in other words, the 90th scan line group GLS includes the first scan line GL1.
  • the first scan line GL1 in the same scan line group GLS is driven by the first gate drive circuit GOA1
  • the second scan line GL2 in the same scan line group GLS is driven by the second gate drive circuit GOA2
  • the first scan line GL1 in the same scan line group GLS is driven by the third gate drive circuit GOA3
  • the second scan line GL2 in the same scan line group GLS is driven by the fourth gate drive circuit GOA4
  • the first scan line GL1 in the 90th scan line group GLS is driven by the first gate drive circuit GOA1
  • the second sub-panel SPNL2 the first scan line GL1 in the 90th scan line group GLS is driven by the third gate drive circuit GOA3.
  • the number of rows of the scan lines GL is an even number, for example, the number of rows of the scan lines GL may be 2, 4, 100, 180, etc.
  • the start signal of the second gate driving circuit GOA2 of the first sub-panel SPNL1 and the start signal of the third gate driving circuit GOA3 of the second sub-panel SPNL2 are generated at the same time.
  • the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2 that are sequentially spliced in the column direction.
  • the number of scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 is 180 rows, and the first sub-panel SPNL1 is located above the second sub-panel SPNL2.
  • the first sub-panel SPNL1 is provided with a first gate drive circuit GOA1 and a second gate drive circuit GOA2
  • the second sub-panel SPNL2 is provided with a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4.
  • two gate drive circuits GOA are provided on the first sub-panel SPNL1 and the second sub-panel SPNL2.
  • Each gate drive circuit GOA includes 90 shift registers SR that are cascaded in sequence, that is, each gate drive circuit GOA includes a first shift register SR1, a second shift register SR2, a third shift register SR3, ..., a ninetieth shift register SR90 that are cascaded in sequence; the scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 are respectively divided into 90 adjacent scan lines.
  • Scan line group GLS the scan line group GLS includes two scan lines GL that are adjacent to each other in sequence. In other words, the scan line group GLS includes a first scan line GL1 and a second scan line GL2 that are adjacent to each other in sequence.
  • the two scan lines GL in the same scan line group GLS are driven by two gate drive circuits GOA respectively.
  • the first scan line GL1 in the first scan line group GLS is electrically connected to the first shift register SR1 of the first gate drive circuit GOA1
  • the second scan line GL2 in the first scan line group GLS is electrically connected to the first shift register SR1 of the second gate drive circuit GOA2
  • the first scan line GL1 in the second scan line group GLS is electrically connected to the second shift register SR2 of the first gate drive circuit GOA1
  • the second scan line GL2 in the second scan line group GLS is electrically connected to the second shift register SR2 of the second gate drive circuit GOA2.
  • the second shift register SR2 of the gate drive circuit GOA2 is electrically connected, the first scan line GL1 in the third scan line group GLS is electrically connected to the third shift register SR3 of the first gate drive circuit GOA1, the second scan line GL2 in the third scan line group GLS is electrically connected to the third shift register SR3 of the second gate drive circuit GOA2,..., the first scan line GL1 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the first gate drive circuit GOA1, and the second scan line GL2 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the second gate drive circuit GOA2.
  • the first scan line GL1 in the first scan line group GLS is electrically connected to the first shift register SR1 of the third gate drive circuit GOA3
  • the second scan line GL2 in the first scan line group GLS is electrically connected to the first shift register SR1 of the fourth gate drive circuit GOA4
  • the first scan line GL1 in the second scan line group GLS is electrically connected to the second shift register SR2 of the third gate drive circuit GOA3
  • the second scan line GL2 in the second scan line group GLS is electrically connected to the second shift register SR2 of the fourth gate drive circuit GOA4.
  • the first scan line GL1 in the third scan line group GLS is electrically connected to the third shift register SR3 of the third gate drive circuit GOA3, the second scan line GL2 in the third scan line group GLS is electrically connected to the third shift register SR3 of the fourth gate drive circuit GOA4, ..., the first scan line GL1 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the third gate drive circuit GOA3, the second scan line GL2 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the fourth gate drive circuit GOA4.
  • the input end of the first shift register SR1 of the first gate drive circuit GOA1 is electrically connected to the input end of the first shift register SR1 of the fourth gate drive circuit GOA4.
  • the first shift register SR1 of the first gate drive circuit GOA1 and the first shift register SR1 of the fourth gate drive circuit GOA4 are connected so that the start signal at the same time is loaded, so that the odd-numbered scan lines GL of the first sub-panel SPNL1 and the even-numbered scan lines GL of the second sub-panel SPNL2 are scanned at the same time, which takes half the duration of the scanning cycle; thereafter, the even-numbered scan lines GL of the first sub-panel SPNL1 and the odd-numbered scan lines GL of the second sub-panel SPNL2 are scanned at the same time, and this process also takes half the duration of the scanning cycle; in short, the scanning time difference from the 180th scan line GL of the first sub-panel SPNL1 to the first scan line GL of the second sub-panel SPNL2 is half the duration of the scanning
  • the two gate drive circuits GOA can realize separate scanning of the odd and even row scan lines GL of the same sub-panel SPNL, so that the scanning time difference between the 180th row scan line GL of the first sub-panel SPNL1 and the first row scan line GL of the second sub-panel SPNL2 is half of the scanning period of the sub-panel SPNL, which is beneficial to solve the screen tearing phenomenon of the spliced display panel PNL and improve the display quality.
  • the even-numbered scan lines GL of the first sub-panel SPNL1 and the odd-numbered scan lines GL of the second sub-panel SPNL2 are first scanned simultaneously, and then the odd-numbered scan lines GL of the first sub-panel SPNL1 and the even-numbered scan lines GL of the second sub-panel SPNL2 are scanned simultaneously, so that the odd and even-numbered scan lines GL of the same sub-panel SPNL can be scanned separately through two gate drive circuits GOA, so that the scanning time difference between the 180th scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 is half of the scanning period of the sub-panel SPNL, which is beneficial to solving the screen tearing phenomenon of the spliced display panel PNL and improving the display quality.
  • the input end of the first shift register SR1 of the first gate drive circuit GOA1 is loaded with the first start signal GSTV1
  • the input end of the first shift register SR1 of the second gate drive circuit GOA2 is loaded with the second start signal GSTV2
  • the input end of the first shift register SR1 of the third gate drive circuit GOA3 is loaded with the second start signal GSTV2
  • the input end of the first shift register SR1 of the fourth gate drive circuit GOA4 is loaded with the first start signal GSTV1
  • the moment when the conduction level of the first start signal GSTV1 starts is 1/2 scanning cycle earlier than the moment when the conduction level of the second start signal GSTV2 starts.
  • the number of rows of the scan lines GL is an odd number; the start signal of the first gate driving circuit GOA1 of the first sub-panel SPNL1 and the start signal of the third gate driving circuit GOA3 of the second sub-panel SPNL2 are at the same time.
  • the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2 sequentially spliced along a column direction.
  • the number of scan lines GL in the first sub-panel SPNL1 and the second sub-panel SPNL2 is 179 rows, and the first sub-panel SPNL1 is located above the second sub-panel SPNL2.
  • the first sub-panel SPNL1 is provided with a first gate drive circuit GOA1 and a second gate drive circuit GOA2
  • the second sub-panel SPNL2 is provided with a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4.
  • two gate drive circuits GOA are provided on the first sub-panel SPNL1 and the second sub-panel SPNL2, and the first gate drive circuit GOA1 and the third gate drive circuit GOA3 both include 90 shift registers SR cascaded in sequence, that is, the first gate drive circuit GOA1 and the third gate drive circuit GOA3 both include a first shift register SR1, a second shift register SR2, a third shift register SR3, ..., a ninetieth shift register SR90 cascaded in sequence, and the second gate drive circuit GOA2 and the fourth gate drive circuit GOA4 both include 89 shift registers SR cascaded in sequence, that is, the second gate drive circuit GOA2 and the fourth gate drive circuit GOA4 both include a first shift register SR1, a second shift register SR2, a third shift register SR3, ..., an eighty-ninth shift register SR89 cascaded in sequence.
  • the scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 are respectively divided into 90 sequentially adjacent scan line groups GLS.
  • the first 89 scan line groups GLS include two sequentially adjacent scan lines GL.
  • the first 89 scan line groups GLS include a first scan line GL1 and a second scan line GL2 that are sequentially adjacent.
  • the 90th scan line group GLS includes one scan line GL.
  • the 90th scan line group GLS includes a first scan line GL1.
  • the two scan lines GL in the same scan line group GLS are driven by two gate drive circuits GOA respectively.
  • the first scan line GL1 in the first scan line group GLS is electrically connected to the first shift register SR1 of the first gate drive circuit GOA1
  • the second scan line GL2 in the first scan line group GLS is electrically connected to the first shift register SR1 of the second gate drive circuit GOA2
  • the first scan line GL1 in the second scan line group GLS is electrically connected to the second shift register SR2 of the first gate drive circuit GOA1
  • the second The second scan line GL2 in the scan line group GLS is electrically connected to the second shift register SR2 of the second gate drive circuit GOA2
  • the first scan line GL1 in the third scan line group GLS is electrically connected to the third shift register SR3 of the first gate drive circuit GOA1
  • the second scan line GL2 in the third scan line group GLS is electrically connected to the third shift register SR3 of the second gate drive circuit GOA2
  • the first scan line GL1 in the 90th scan line group GLS is electrically connected to
  • An input terminal of the first shift register SR1 of the first gate drive circuit GOA1 is electrically connected to an input terminal of the first shift register SR1 of the third gate drive circuit GOA3, so that the first shift register SR1 of the first gate drive circuit GOA1 and the first shift register SR1 of the third gate drive circuit GOA3 are loaded with the same start signal.
  • the odd-numbered scan lines GL of the first sub-panel SPNL1 and the odd-numbered scan lines GL of the second sub-panel SPNL2 are scanned simultaneously, which takes half a scan cycle. Thereafter, the even-numbered scan lines GL of the first sub-panel SPNL1 and the even-numbered scan lines GL of the second sub-panel SPNL2 are scanned simultaneously, which also only takes half a scan cycle.
  • the scanning time difference from the 179th scan line GL of the first sub-panel SPNL1 to the first scan line GL of the second sub-panel SPNL2 is half a scan cycle.
  • the odd and even scan lines GL of the same sub-panel SPNL can be scanned separately through the two gate drive circuits GOA, so that the scanning time difference between the 179th scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 is half of the scanning period of the sub-panel SPNL, which is beneficial to solve the screen tearing phenomenon of the spliced display panel PNL.
  • Improve display quality is beneficial to solve the screen tearing phenomenon of the spliced display panel PNL.
  • the even-numbered scan lines GL of the first sub-panel SPNL1 and the even-numbered scan lines GL of the second sub-panel SPNL2 are scanned simultaneously, and then the odd-numbered scan lines GL of the first sub-panel SPNL1 and the odd-numbered scan lines GL of the second sub-panel SPNL2 are scanned simultaneously; so that the odd and even-numbered scan lines GL of the same sub-panel SPNL can be scanned separately through two gate drive circuits GOA, so that the scanning time difference between the 179th scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 is half of the scanning period of the sub-panel SPNL, which is beneficial to solving the screen tearing phenomenon of the spliced display panel PNL, so as to improve the display quality.
  • the first start signal GSTV1 is loaded at the input of the first shift register SR1 of the first gate drive circuit GOA1
  • the second start signal GSTV2 is loaded at the input of the first shift register SR1 of the second gate drive circuit GOA2
  • the first start signal GSTV1 is loaded at the input of the first shift register SR1 of the third gate drive circuit GOA3
  • the second start signal GSTV2 is loaded at the input of the first shift register SR1 of the fourth gate drive circuit GOA4.
  • the on-level start time of the first start signal GSTV1 is 1/2 of a scan cycle earlier than the on-level start time of the second start signal GSTV2.
  • the on-level of the first start signal GSTV1 and the second start signal GSTV2 is low, and the off-level is high. In other embodiments of the present disclosure, the on-level of the first start signal GSTV1 and the second start signal GSTV2 is high, and the off-level is low.
  • the display panel PNL is a Mini LED display panel, a Micro LED display panel, an OLED display panel, a QLED display panel, or an LCD display panel.
  • the display panel PNL is a Mini LED.
  • the display panel PNL is a Micro LED.
  • the sub-panel SPNL has light-emitting control lines corresponding to each sub-pixel row, and the light-emitting control lines are used to load light-emitting control signals EM to the pixel driving circuit PDC; and each of the light-emitting control lines is electrically connected to each other.
  • the conduction level of the light emitting control signal EM takes effect after all the scanning lines GL of the rows have been scanned.
  • the conduction level of the light emitting control signal EM takes effect after all the gate drive circuits GOA have been scanned. That is, at the first gate drive circuit, the conduction level of the light emitting control signal EM takes effect.
  • the on-level of the light-emitting control signal EM takes effect, causing each sub-pixel PIX to emit light simultaneously.
  • the first gate drive circuit GOA1, the second gate drive circuit GOA2, the third gate drive circuit GOA3, and the fourth gate drive circuit GOA4 shown in FIG. 14 are gate drive circuits GOA corresponding to each of the four sub-panels SPNL.
  • the first sub-panel SPNL corresponds to the first gate drive circuit GOA1
  • the second sub-panel SPNL corresponds to the second gate drive circuit GOA2
  • the third sub-panel SPNL corresponds to the third gate drive circuit GOA3
  • the fourth sub-panel SPNL corresponds to the fourth gate drive circuit GOA4.
  • the conduction level of the light-emitting control signal EM is connected to light up all the sub-pixels PIX. In this way, there is no lighting time difference between the sub-pixels PIX of the 180th row of the first sub-panel SPNL1 and the first row of the second sub-panel SPNL2, which can effectively solve the screen tearing phenomenon.
  • the conduction level of the light-emitting control signal EM is connected to light up all the sub-pixels PIX. In this way, there is no lighting time difference between the sub-pixels PIX of the 179th row of the first sub-panel SPNL1 and the first row of the second sub-panel SPNL2, which can effectively solve the screen tearing phenomenon.
  • the method of controlling the lighting time of the sub-pixel PIX needs to be used when the scanning frequency is high, that is, it needs to be used when the display panel PNL is scanned quickly, such as a scanning frequency of 120Hz or 144Hz, etc., to avoid the shutdown time of each sub-panel SPNL in each frame being too long, which causes the human eye to recognize screen flickering.

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Abstract

一种显示面板(PNL)及显示装置，显示面板(PNL)包括沿列方向依次拼接的至少两个子面板(SPNL)；任意一个子面板(SPNL)包括阵列分布的子像素(PIX)和与各个子像素行一一对应的扫描线(GL)；子面板(SPNL)具有用于驱动各个扫描线(GL)的多个栅极驱动电路(GOA)；其中，在相邻的两个子面板(SPNL)中，前一个子面板(SPNL)的最后一行扫描线(GL)所电连接的栅极驱动电路(GOA)的起始信号，与后一个子面板(SPNL)的第一行扫描线(GL)所电连接的栅极驱动电路(GOA)的起始信号的时刻相同。有利于解决拼接显示面板(PNL)的画面撕裂的问题。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示面板及显示装置。
背景技术
目前，AM(有源驱动)的Mini/Micro LED(迷你发光二极管或者微型发光二极管)拼接显示屏的栅极驱动电路GOA驱动扫描方式为每个拼接模组同时开始扫描。这导致上下模组拼缝处的两行像素(上模组的最后一行像素和下模组的第一行像素)的扫描时刻的时间差达到一个扫描周期(1Frame)的时长。因此，上下模组拼缝处的两行像素的图像显示的时间差也为一个扫描周期的时长。在播放快速移动的画面时，则上下模组容易出现画面不同步的现象(画面撕裂)，影响显示质量。
可以理解的是，一帧包括一个扫描周期(1Frame)和一个空白周期(1blank)。具体地，1Frame为模组的栅极驱动电路GOA从第一行扫描到最后一行的时间。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于克服上述现有技术的不足，提供一种显示面板及显示装置，以便于解决拼接显示面板的画面撕裂的问题。
根据本公开的一个方面，提供一种显示面板，包括沿列方向依次拼接的至少两个子面板；
任意一个所述子面板包括阵列分布的子像素和与各个子像素行一一对应的扫描线；
所述子面板具有用于驱动各个所述扫描线的多个栅极驱动电路；
其中，在相邻的两个所述子面板中，前一个所述子面板的最后一行 所述扫描线所电连接的所述栅极驱动电路的起始信号，与后一个所述子面板的第一行所述扫描线所电连接的所述栅极驱动电路的起始信号的时刻相同。
在本公开的一种实施方式中，所述显示面板包括两个子面板。
在本公开的一种实施方式中，所述子面板包括两个栅极驱动电路。
在本公开的一种实施方式中，所述子面板上设置m个栅极驱动电路；m为大于1的正整数；
所述扫描线分为多个依次相邻的扫描线组，所述扫描线组包括依次相邻的m个扫描线；
同一所述扫描线组中的m个所述扫描线分别通过m个所述栅极驱动电路驱动。
在本公开的一种实施方式中，所述栅极驱动电路均包括依次级联的多个移位寄存器；
第i个所述扫描线组中的第j个所述扫描线，与第j个所述栅极驱动电路的第i个所述移位寄存器电连接；j为在1～m之间的正整数。
在本公开的一种实施方式中，所述栅极驱动电路包括依次级联的多个移位寄存器；
所述子面板的第一参考栅极驱动电路为驱动所述子面板的最后一行扫描线的栅极驱动电路；所述子面板的第二参考栅极驱动电路为驱动所述子面板的第一行扫描线的栅极驱动电路；
在相邻的两个子面板中，前一个所述子面板的第一参考栅极驱动电路的第一级移位寄存器的输入端与后一个所述子面板的第二参考栅极驱动电路的第一级移位寄存器的输入端电连接。
在本公开的一种实施方式中，所述显示面板包括沿列方向依次拼接的第一子面板和第二子面板；
所述第一子面板具有用于驱动各个所述扫描线的第一栅极驱动电路和第二栅极驱动电路；所述第一栅极驱动电路用于驱动所述第一子面板的奇数行扫描线，第二栅极驱动电路用于驱动所述第一子面板的偶数行扫描线；
所述第二子面板具有用于驱动各个所述扫描线的第三栅极驱动电路 和第四栅极驱动电路；所述第三栅极驱动电路用于驱动所述第二子面板的奇数行扫描线，第四栅极驱动电路用于驱动第二子面板的偶数行扫描线。
在本公开的一种实施方式中，所述子面板的扫描线的行数为偶数；所述第一子面板的所述第二栅极驱动电路的起始信号与所述第二子面板的所述第三栅极驱动电路的起始信号的时刻相同。
在本公开的一种实施方式中，所述子面板的扫描线的行数为奇数；所述第一子面板的所述第一栅极驱动电路的起始信号与所述第二子面板的所述第三栅极驱动电路的起始信号的时刻相同。
在本公开的一种实施方式中，所述第一栅极驱动电路的起始信号的开始时刻比所述第二栅极驱动电路的起始信号的开始时刻早二分之一个扫描周期。
在本公开的一种实施方式中，所述子面板具有与各个子像素行一一对应的发光控制走线，所述发光控制走线用于向像素驱动电路加载发光控制信号；
各个所述发光控制走线相互电连接。
在本公开的一种实施方式中，所述显示面板为Mini LED显示面板、Micro LED显示面板、OLED显示面板、QLED显示面板或者LCD显示面板。
根据本公开的另一个方面，还提供一种显示装置，包括上述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开的一种实施方式中，显示面板的示意图。
图2为本公开的一种实施方式中，子面板的示意图。
图3为本公开的一种实施方式中，子面板的膜层示意图。
图4为本公开的一种实施方式中，子面板的膜层示意图。
图5为本公开的一种实施方式中，子像素的膜层示意图。
图6为本公开的一种实施方式中，子像素的膜层示意图。
图7为本公开的一种实施方式中，子像素的膜层示意图。
图8为本公开的一种实施方式中，子像素的膜层示意图。
图9为本公开的一种实施方式中，显示面板的结构示意图。
图10为本公开的一种实施方式中，图9中显示面板的各个子像素行的扫描线对应的时序图。
图11为本公开的一种实施方式中，显示面板的结构示意图。
图12为本公开的一种实施方式中，图11中显示面板的各个子像素行的扫描线对应的时序图。
图13为本公开的一种实施方式中，起始信号的时序图。
图14为本公开的一种实施方式中，各个子像素行同时加载发光控制信号的时序图。
附图标记说明：
AA、显示区；BB、外围区；Buff、无机缓冲层；CFL、彩膜层；CGL、
电荷产生层；COML、公共电极层；CVD1、第一无机封装层；CVD2、第二无机封装层；DBP、驱动背板；DH、行方向；DL、数据线；DRL、驱动层；DV、列方形；EBL、电子阻挡层；EFL、发光功能层；EFU、发光功能单元；EIL、电子注入层；ELS、发光堆叠结构；EML、有机发光层；ETL、电子传输层；GI、栅极绝缘层；GL、扫描线；GL1、第一扫描走线；GL2、第二扫描走线；GLS、扫描线组；GOA、栅极驱动电路；GOA1、第一栅极驱动电路；GOA2、第二栅极驱动电路；GOA3、第三栅极驱动电路；GOA4、第四栅极驱动电路；GT、栅极层；HBL、空穴阻挡层；HIL、空穴注入层；HTL、空穴传输层；IJP、有机封装层；ILD、层间电介质层；PDC、像素驱动电路；PDL、像素定义层；PE、像素电极；PEL、像素电极层；PIX、子像素；PIXL、像素层；PLN、平 坦化层；PNL、显示面板；QDL、量子点层；SBT、衬底基板；SCL、半导体层；SD、源漏金属层；SPNL、子面板；SPNL1、第一子面板；SPNL2、第二子面板；SR、移位寄存器；TFE、薄膜封装层；TFT、薄膜晶体管；TSL、触控功能层；SR1、第一移位寄存器；SR2、第二移位寄存器；SR3、第三移位寄存器；SR89、第八十九移位寄存器；SR90、第九十移位寄存器；
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
在本公开实施方式中，晶体管是指至少包括栅极、源极以及漏极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区，并且电流可以流过源极、沟道区以及漏极。沟道区是指电流主要流过的区域。在本公开实施方式中， 在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换，即“源极”和“漏极”可以互相调换。在本公开实施方式中，对于任意一个晶体管，将“源极”和“漏极”中的一者称为该晶体管的第一极，且另一者称为该晶体管的第二极，将栅极称为该晶体管的控制端。在本公开实施方式中，至少部分信号具有高电平和低电平；高电平和低电平中的一者可以作为该信号的导通电平，该信号的导通电平可以使得所控制的晶体管导通；高电平和低电平中的另一者可以作为该信号的截止电平，该信号的截止电平可以使得所控制的晶体管截止。举例而言，对于控制P型晶体管的信号(该信号能够加载至P型晶体管的控制端)，其导通电平为低电平，其截止电平为高电平。再举例而言，对于控制N型晶体管的信号(该信号能够加载至N型晶体管的控制端)，其导通电平为高电平，其截止电平为低电平。
结构层A位于结构层B背离衬底基板SBT的一侧，可以理解为，结构层A在结构层B背离衬底基板SBT的一侧形成。当结构层B为图案化结构时，结构层A的部分结构也可以位于结构层B的同一物理高度或低于结构层B的物理高度，其中，衬底基板SBT为高度基准。
本公开提供一种显示装置，包括显示面板PNL。该显示装置可以为TV(电视机)、会议一体机、广告屏等任何具有显示功能的产品或部件。在一种示例中，显示面板PNL为显示尺寸不小于80寸的显示面板PNL，尤其是为不小于100寸的显示面板PNL。当然的，显示面板PNL也可以为中小尺寸的显示面板PNL，例如可以为直接显示的Mini LED显示面板或者直接显示的Micro LED显示面板。
在本公开实施方式中，参见图1，显示面板PNL包括沿列方向依次拼接的至少两个子面板SPNL。如此，可以采用较小尺寸的子面板SPNL形成较大尺寸的显示面板PNL，进而降低显示面板PNL的成本。
在本公开的一种实施方式中，参见图2，该子面板SPNL包括显示区AA和位于显示区AA至少一侧的外围区BB。在显示区AA中，子面板SPNL设置有阵列分布的显示单元，所述显示单元包括子像素PIX和驱动所述子像素PIX的像素驱动电路PDC。所述子面板SPNL在外围区 BB不设置显示单元，或者所设置的显示单元不用于显示画面。
参见图2，所述子面板SPNL在所述显示区AA设置有沿行方向DH延伸的多个扫描线GL，各个扫描线GL与各个显示单元行一一对应设置。所述显示单元行的各个显示单元的像素驱动电路PDC，均与对应的扫描线GL电连接。所述子面板SPNL在显示区AA还设置有沿列方形DV延伸的多个数据线DL，各个数据线DL与各个显示单元列一一对应设置。所述显示单元列的各个显示单元的像素驱动电路PDC，均与对应的数据线DL电连接。如此，每个显示单元的像素驱动电路PDC与一个扫描线GL和一个数据线DL连接。当扫描线GL上加载扫描信号时，可以使得数据线DL上加载的驱动电压写入像素驱动电路PDC中，进而使得子像素PIX的发光。
可选的，像素驱动电路PDC至少包括数据写入晶体管、驱动晶体管和存储电容，驱动晶体管的控制端可以与存储电容的一个电极板电连接。数据写入晶体管的源极可以与数据线DL电连接，且数据写入晶体管的控制端可以与扫描线GL电连接。该像素驱动电路PDC被配置为，当扫描线GL上加载扫描信号时，该数据写入晶体管被导通，进而使得数据线DL上的驱动电压被写入驱动晶体管的控制端和存储电容。当该数据写入晶体管关断后，该驱动电压可以被该存储电容保持。驱动晶体管能够在其控制端上的电压的控制下，输出驱动电流以驱动子像素PIX发光。可以理解的是，本公开实施方式的像素驱动电路PDC还可以包括其他晶体管或者电容，以使得该像素驱动电路PDC具有更好的驱动性能。例如，该像素驱动电路PDC可以为7T1C(7个薄膜晶体管TFT和一个存储电容)、8T1C(8个薄膜晶体管TFT和一个存储电容)或者其他架构的像素驱动电路。
可选的，子像素PIX可以为电流驱动的自发光元件，例如可以为OLED、QLED、Micro LED、Mini LED等发光元件中的任意一种。在该实施方式中，子像素PIX可以包括多种不同颜色的子像素PIX，例如包括用于发出红光的红色子像素、用于发出绿光的蓝色子像素和用于发出绿光的绿色子像素。可以理解的是，在本公开的其他实施方式中，显示区AA中的子像素PIX也可以具有其他颜色的子像素PIX(例如用于发 出黄光的黄色子像素、用于发出青光的青色子像素、用于发出白光的白色子像素等)。
在本公开的一种实施方式中，参见图3，子面板SPNL可以包括依次层叠设置的衬底基板SBT、驱动层DRL和像素层PIXL。像素层PIXL中设置有子像素PIX，且驱动层DRL设置有用于驱动子像素PIX的像素驱动电路PDC；各个子像素PIX可以在像素驱动电路PDC的驱动下发光以显示画面。在图3的示例中，子像素PIX为薄膜型自发光元件，例如可以为OLED、QLED、PLED等发光元件。在该图3的示例中，子面板SPNL还包括位于像素层PIXL远离衬底基板SBT一侧的封装层，该封装层可以对像素层PIXL进行封装保护。在一种示例中，封装层为薄膜封装层TFE。
可以理解的是，在本公开实施方式中，显示面板PNL还可以为其他类型的面板。例如，显示面板PNL还可以为Mini LED显示面板、Micro LED显示面板等显示面板。在该显示面板PNL中，子面板SPNL的膜层结构可以与图3的示例不同。PNL还可以为LCD显示面板；在该LCD显示面板PNL中，子面板SPNL的结构也与图3的示例不同。
如下，以显示面板PNL的子像素PIX为薄膜型自发光元件为例，对子面板SPNL的膜层结构和远离进行示例性说明。
在该示例中，衬底基板SBT可以为无机材料的衬底基板SBT，也可以为有机材料的衬底基板SBT；当然的，也可以为无机材料的衬底基板SBT和有机材料的衬底基板SBT层叠而成的复合基板。举例而言，在本公开的一些实施方式中，衬底基板SBT的材料可以为钠钙玻璃、石英玻璃、蓝宝石玻璃等玻璃材料。在本公开的另外一些实施方式中，衬底基板SBT的材料可以为聚甲基丙烯酸甲酯、聚乙烯醇、聚乙烯基苯酚、聚醚砜、聚酰亚胺、聚酰胺、聚缩醛、聚碳酸酯、聚对苯二甲酸乙二酯、聚萘二甲酸乙二酯或其组合。在本公开的另一些实施方式中，衬底基板SBT也可以为柔性衬底基板SBT，例如衬底基板SBT的材料可以包括聚酰亚胺。
可选的，在驱动层DRL中，任意一个像素驱动电路PDC可以包括有薄膜晶体管TFT和存储电容。进一步地，薄膜晶体管TFT可以选自顶 栅型薄膜晶体管TFT、底栅型薄膜晶体管TFT或者双栅型薄膜晶体管TFT；薄膜晶体管TFT的有源层的材料可以为非晶硅半导体材料、低温多晶硅半导体材料、金属氧化物半导体材料、有机半导体材料、碳纳米管半导体材料或者其他类型的半导体材料；薄膜晶体管TFT可以为N型薄膜晶体管TFT或者P型薄膜晶体管TFT。
可以理解的是，像素驱动电路中的各个晶体管中，任意两个晶体管之间的类型可以相同或者不相同。示例性地，在一些实施方式中，在一个像素驱动电路中，部分晶体管可以为N型晶体管且部分晶体管可以为P型晶体管。再示例性地，在另一些实施方式中，在一个像素驱动电路中，部分晶体管的有源层的材料可以为低温多晶硅半导体材料，且部分晶体管的有源层的材料可以为金属氧化物半导体材料。在本公开的一些实施方式中，薄膜晶体管TFT为低温多晶硅晶体管。在本公开的另外一些实施方式中，部分薄膜晶体管TFT为低温多晶硅晶体管，部分薄膜晶体管TFT为金属氧化物晶体管。
可选的，驱动层DRL可以包括层叠于衬底基板SBT和像素层PIXL之间的半导体层SCL、栅极绝缘层GI、栅极层GT、层间电介质层ILD、源漏金属层SD、平坦化层PLN等。各个薄膜晶体管TFT和存储电容可以由半导体层SCL、栅极绝缘层GI、栅极层GT、层间电介质层ILD、源漏金属层SD等膜层形成。其中，各个膜层的位置关系可以根据薄膜晶体管TFT的膜层结构确定。进一步地，半导体层SCL可以用于形成晶体管的沟道区，在必要时也可以通过导体化而形成部分走线或者导电结构。栅极层可以用于形成扫描走线、复位控制走线、发光控制走线等栅极层走线中的一种或者多种，也可以用于形成晶体管的控制端，还可以用于形成存储电容的部分或者全部电极板。源漏金属层可以用于形成数据走线、驱动电源电压走线等源漏金属层走线，也可以用于形成存储电容的部分电极板。当然的，在本公开的其他实施方式中，驱动层DRL还可以根据需要而包括其他膜层，例如还可以包括位于半导体层SCL和衬底基板SBT之间的遮光层等。根据需要，上述半导体层SCL、栅极层GT、源漏金属层SD等膜层中的任意一种还可以为多层，例如驱动层DRL中可以包括不同的两层半导体层SCL，或者包括两层或者三层源漏金属 层SD，或者包括两层或者三层的栅极层GT；相应的，驱动层DRL中的绝缘性膜层(例如栅极绝缘层GI、层间电介质层ILD、平坦化层PLN等)可以适应性的增加或者减少，或者根据需要增设新的绝缘性膜层。
可选的，驱动层DRL还可以包括有钝化层，钝化层可以设于源漏金属层SD远离衬底基板SBT的表面，以便保护源漏金属层SD。
作为一种示例，参见图3，驱动层DRL可以包括依次层叠设置的无机缓冲层Buff、半导体层SCL、栅极绝缘层GI、栅极层GT、层间电介质层ILD、源漏金属层SD和平坦化层PLN，如此所形成的薄膜晶体管TFT为顶栅型薄膜晶体管TFT。
在本公开的一种实施方式中，参见图4和图5，像素层PIXL中的子像素PIX为薄膜型发光元件，其可以包括层叠设置的两个电极以及夹设于两个电极之间的发光功能单元EFU。
举例而言，参见图4，像素层PIXL可以包括依次层叠设置的像素电极层PEL、发光功能层EFL和公共电极层COML。其中，像素电极层PEL在子面板SPNL的显示区具有多个像素电极PE；发光功能层EFL与像素电极PE连接的部分作为子像素PIX的发光功能单元EFU，公共电极层COML作为公共电极与各个子像素PIX的发光功能单元EFU电连接。
进一步的，像素层PIXL还可以包括位于像素电极层PEL和发光功能层EFL之间的像素定义层PDL。像素定义层PDL具有与多个像素电极PE一一对应设置的多个贯通的像素开口，任意一个像素开口暴露对应的像素电极的至少部分区域。例如，像素定义层PDL覆盖像素电极PE的边缘且暴露像素电极PE的至少部分内部区域，以使得像素定义层PDL可以有效的定义像素电极PE的实际有效区域(直接与发光功能单元EFU连接的区域)，进而定义子像素PIX的发光区域和发光面积。发光功能层EFL至少覆盖被像素定义层PDL所暴露的像素电极PE。公共电极层COML在显示区可以覆盖发光功能层EFL。像素电极PE和公共电极层COML向发光功能层EFL提供电子、空穴等载流子，以使得发光功能层EFL发光。发光功能层EFL位于像素电极PE和公共电极层COML之间的部分，可以作为发光功能单元EFU。像素电极PE、公共 电极层COML、发光功能单元EFU形成子像素PIX。其中，像素电极PE和公共电极层COML中的一者作为子像素PIX的阳极，且另一者作为子像素PIX的阴极。
在一种示例中，像素电极PE作为子像素PIX的阳极，且公共电极层COML作为子像素PIX的阴极。
可以理解的是，发光元件的类型不同，发光功能单元EFU的材料和膜层不同。
举例而言，参见图5，当发光元件为OLED时，发光功能单元EFU可以包括有机发光层EML，以及可以包括有空穴注入层HIL、空穴传输层HTL、电子阻挡层EBL、空穴阻挡层HBL、电子传输层ETL和电子注入层EIL中的一种或者多种。进一步的，有机发光层EML可以包括发光层主体材料和发光层客体材料，该发光层客体材料可以为荧光掺杂剂或者磷光掺杂剂，尤其是可以为热激活延迟荧光材料。参见图6，当该OLED采用堆叠结构时，发光功能层EFL中还可以设置有电荷产生层CGL。
再举例而言，参见图7，当发光元件为QLED时，发光功能单元EFU可以包括量子点层QDL，以及可以包括空穴注入层HIL、电子传输层ETL、电子阻挡层EBL、空穴阻挡层HBL、电子传输层ETL和电子注入层EIL中的一种或者多种。进一步的，量子点层QDL可以具有量子点颗粒，量子点颗粒之间可以通过表面修饰基团相互连接。参见图8，当该QLED采用堆叠结构时，发光功能单元EFU中还可以设置有电荷产生层CGL。
在本公开实施方式中，参见图5～图8，发光功能单元EFU可以包括一层发光堆叠结构ELS，也可以包括层叠的多层发光堆叠结构ELS。当发光功能单元EFU包括多层发光堆叠结构ELS时，相邻两层发光堆叠结构ELS之间可以设置有电荷产生层CGL。其中，每一层发光堆叠结构ELS均设置有一层或者多层发光层，该发光层可以为有机发光层EML或者量子点层QDL中的任意一者。
参见图3，薄膜封装层TFE可以设于像素层PIXL远离衬底基板SBT的表面，其可以包括交替层叠设置的无机封装层和有机封装层。无机封装层可以有效的阻隔外界的水分和氧气，避免水氧入侵像素层PIXL而 导致像素层PIXL中的材料老化。可选地，无机封装层的边缘可以位于外围区。有机封装层位于相邻的两层无机封装层之间，以便实现平坦化和减弱无机封装层之间的应力。其中，有机封装层的边缘可以位于显示区的边缘和无机封装层的边缘之间。示例性地，薄膜封装层TFE包括依次层叠于像素层PIXL远离衬底基板SBT一侧的第一无机封装层CVD1、有机封装层IJP和第二无机封装层CVD2。当然的，在本公开的其他实施方式中，子面板SPNL也可以不设置薄膜封装层，而是采用其他方式对像素层进行封装和保护。
在本公开的一些实施方式中，参见图3，子面板SPNL还可以包括触控功能层TSL，触控功能层TSL可以设置于薄膜封装层TFE远离驱动背板DBP的一侧，以使得该子面板SPNL具有触控功能。
在本公开的一些实施方式中，参见图3，子面板SPNL还可以包括彩膜层CFL，彩膜层CFL可以设置于薄膜封装层TFE远离驱动背板DBP的一侧，以降低对环境光线的反射，提高显示质量。
在本公开的一种实施方式中，参见图9，显示面板PNL包括沿列方向依次拼接的至少两个子面板SPNL。任意一个所述子面板SPNL包括阵列分布的子像素PIX和与各个子像素行一一对应的扫描线GL，所述子像素PIX设有上述的像素驱动电路PDC，所述像素驱动电路PDC用于驱动所述子像素PIX；所述子面板SPNL具有用于驱动各个所述扫描线GL的多个栅极驱动电路GOA。其中，在相邻的两个所述子面板SPNL中，前一个所述子面板SPNL的最后一行所述扫描线GL所电连接的所述栅极驱动电路GOA的起始信号，与后一个所述子面板SPNL的第一行所述扫描线GL所电连接的所述栅极驱动电路GOA的起始信号的时刻相同。
可以理解的是，本实施方式中所述的“前一个”和“后一个”是指在相邻的两个子面板SPNL中的上下位置关系。例如，前一个子面板SPNL可以是指位置靠上的子面板SPNL，后一个子面板SPNL可以是指位置靠下的子面板SPNL，两个子面板SPNL依次拼接。在一种示例中，所述起始信号的时刻相同，可以是指两个栅极驱动电路GOA的输入端共用同一个起始信号或两个栅极驱动电路GOA的输入端分别接入的起 始信号的时刻相同。
在相邻的两个子面板SPNL中，通过将前一个子面板SPNL的最后一行扫描线GL所电连接的栅极驱动电路GOA的起始信号与后一个子面板SPNL的第一行扫描线GL所电连接的栅极驱动电路GOA的起始信号的时刻设为相同，在驱动相邻两个子面板SPNL的扫描线GL时，能够使得子面板SPNL的奇偶行扫描线GL分别单独驱动，从而可以减小前一个子面板SPNL的最后一行扫描线GL与后一个子面板SPNL的第一行扫描线GL的扫描时间差，有利于解决拼接显示面板PNL的画面撕裂的现象，以提高显示质量，便于应用在可定制的拼接尺寸的显示产品中。
在本公开的一种实施方式中，参见图9，所述显示面板PNL包括两个子面板SPNL，换言之，两个沿列方向拼接的子面板SPNL共同组成了本实施方式的显示面板PNL。
在本公开的一种实施方式中，参见图9，所述子面板SPNL包括两个栅极驱动电路GOA，通过两个栅极驱动电路GOA驱动扫描线GL，便于对子面板SPNL的扫描线GL的奇偶行单独进行扫描。
在本公开的一种实施方式中，所述子面板SPNL上设置m个栅极驱动电路GOA；m为大于1的正整数，例如，m可以为2、3、4等的正整数；所述扫描线GL分为多个依次相邻的扫描线组GLS，所述扫描线组GLS包括依次相邻的m个扫描线GL；同一所述扫描线组GLS中的m个所述扫描线GL分别通过m个所述栅极驱动电路GOA驱动。
可选的，同一所述子面板SPNL上的栅极驱动电路GOA数量可以为两个、三个、四个等。
在一种示例中，参见图9和图10，显示面板PNL包括沿列方向依次拼接的第一子面板SPNL1和第二子面板SPNL2。第一子面板SPNL1和第二子面板SPNL2的扫描线GL的数量均为180行，第一子面板SPNL1位于第二子面板SPNL2的上方。第一子面板SPNL1设有第一栅极驱动电路GOA1和第二栅极驱动电路GOA2，第二子面板SPNL2设有第三栅极驱动电路GOA3和第四栅极驱动电路GOA4，换言之，第一子面板SPNL1和第二子面板SPNL2上均设有两个栅极驱动电路GOA。第一子面板SPNL1和第二子面板SPNL2的扫描线GL分别分为90个依次相邻 的扫描线组GLS，扫描线组GLS包括依次相邻的两个扫描线GL，换言之，扫描线组GLS包括依次相邻的第一扫描走线GL1和第二扫描走线GL2。其中，同一个扫描线组GLS中的两个扫描线GL分别通过两个栅极驱动电路GOA驱动，即在第一子面板SPNL1中，同一个扫描线组GLS中的第一扫描走线GL1通过第一栅极驱动电路GOA1驱动，同一个扫描线组GLS中的第二扫描走线GL2通过第二栅极驱动电路GOA2驱动；在第二子面板SPNL2中，同一个扫描线组GLS中的第一扫描走线GL1通过第三栅极驱动电路GOA3驱动，同一个扫描线组GLS中的第二扫描走线GL2通过第四栅极驱动电路GOA4驱动，以便于通过两个栅极驱动电路GOA实现同一子面板SPNL的奇偶行扫描线GL的单独扫描，使得第一子面板SPNL1的第180行扫描线GL与第二子面板SPNL2的第一行扫描线GL的扫描时间差为子面板SPNL扫描周期的一半，有利于解决拼接显示面板PNL的画面撕裂的现象，以提高显示质量。
在另一种示例中，参见图11和图12，显示面板PNL包括沿列方向依次拼接的第一子面板SPNL1和第二子面板SPNL2。第一子面板SPNL1和第二子面板SPNL2的扫描线GL的数量均为179行，第一子面板SPNL1位于第二子面板SPNL2的上方。第一子面板SPNL1设有第一栅极驱动电路GOA1和第二栅极驱动电路GOA2，第二子面板SPNL2设有第三栅极驱动电路GOA3和第四栅极驱动电路GOA4，换言之，第一子面板SPNL1和第二子面板SPNL2上均设有两个栅极驱动电路GOA。第一子面板SPNL1和第二子面板SPNL2的扫描线GL分别分为90个依次相邻的扫描线组GLS，前89个扫描线组GLS包括依次相邻的两个扫描线GL，换言之，前89个扫描线组GLS包括依次相邻的第一扫描走线GL1和第二扫描走线GL2；第90个扫描线组GLS包括一个扫描线GL，换言之，第90个扫描线组GLS包括第一扫描走线GL1。其中，除第90个扫描线组GLS以外，同一个扫描线组GLS中的两个扫描线GL分别通过两个栅极驱动电路GOA驱动，即在第一子面板SPNL1中，同一个扫描线组GLS中的第一扫描走线GL1通过第一栅极驱动电路GOA1驱动，同一个扫描线组GLS中的第二扫描走线GL2通过第二栅极驱动电路GOA2驱动；在第二子面板SPNL2中，同一个扫描线组GLS中的第一扫描走线GL1 通过第三栅极驱动电路GOA3驱动，同一个扫描线组GLS中的第二扫描走线GL2通过第四栅极驱动电路GOA4驱动；而在第一子面板SPNL1中，第90个扫描线组GLS中的第一扫描走线GL1通过第一栅极驱动电路GOA1驱动；在第二子面板SPNL2中，第90个扫描线组GLS中的第一扫描走线GL1通过第三栅极驱动电路GOA3驱动，以便于通过两个栅极驱动电路GOA实现同一子面板SPNL的奇偶行扫描线GL的单独扫描，使得第一子面板SPNL1的第179行扫描线GL与第二子面板SPNL2的第一行扫描线GL的扫描时间差为子面板SPNL扫描周期的一半，有利于解决拼接显示面板PNL的画面撕裂的现象，以提高显示质量。
在其它示例中，以此类推，m可以为3，此时能够通过三个栅极驱动电路GOA实现同一子面板SPNL的奇偶行扫描线GL的单独扫描，即每个扫描线组GLS中包括三条扫描线GL，且三条扫描线GL分别通过三个栅极驱动电路GOA来驱动，从而使得第一子面板SPNL1的最后一行扫描线GL与第二子面板SPNL2的第一行扫描线GL的扫描时间差为子面板SPNL扫描周期的三分之一。m可以为4，此时能够通过四个栅极驱动电路GOA实现同一子面板SPNL的奇偶行扫描线GL的单独扫描，从而使得第一子面板SPNL1的最后一行扫描线GL与第二子面板SPNL2的第一行扫描线GL的扫描时间差为子面板SPNL扫描周期的四分之一。
在本公开的一种实施方式中，所述栅极驱动电路GOA均包括依次级联的多个移位寄存器SR。第i个所述扫描线组GLS中的第j个所述扫描线GL，与第j个所述栅极驱动电路GOA的第i个所述移位寄存器SR电连接；i为正整数，例如i可以为1、2、3等的正整数；j为在1～m之间的正整数，例如，j可以为1、2、3、…、m的正整数。所述子面板SPNL上的多个栅极驱动电路GOA按照预设顺序依次工作；其中，先工作的栅极驱动电路GOA的最后一个移位寄存器SR的输出端与随后工作的栅极驱动电路GOA的第一个移位寄存器SR的输入端相连接。
在一种示例中，参见图9和图10，显示面板PNL包括沿列方向依次拼接的第一子面板SPNL1和第二子面板SPNL2。第一子面板SPNL1和第二子面板SPNL2的扫描线GL的数量均为180行，第一子面板SPNL1位于第二子面板SPNL2的上方。第一子面板SPNL1设有第一栅极驱动 电路GOA1和第二栅极驱动电路GOA2，第二子面板SPNL2设有第三栅极驱动电路GOA3和第四栅极驱动电路GOA4，换言之，第一子面板SPNL1和第二子面板SPNL2上均设有两个栅极驱动电路GOA。每个栅极驱动电路GOA均包括依次级联的90个移位寄存器SR，即每个栅极驱动电路GOA均包括依次级联的第一移位寄存器SR1、第二移位寄存器SR2、第三移位寄存器SR3、…、第九十移位寄存器SR90。第一子面板SPNL1和第二子面板SPNL2的扫描线GL分别分为90个依次相邻的扫描线组GLS，扫描线组GLS包括依次相邻的两个扫描线GL，换言之，扫描线组GLS包括依次相邻的第一扫描走线GL1和第二扫描走线GL2。其中，同一个扫描线组GLS中的两个扫描线GL分别通过两个栅极驱动电路GOA驱动，换言之，在第一子面板SPNL1中，第一个扫描线组GLS中的第一扫描走线GL1与第一栅极驱动电路GOA1的第一移位寄存器SR1电连接，第一个扫描线组GLS中的第二扫描走线GL2与第二栅极驱动电路GOA2的第一移位寄存器SR1电连接，第二个扫描线组GLS中的第一扫描走线GL1与第一栅极驱动电路GOA1的第二移位寄存器SR2电连接，第二个扫描线组GLS中的第二扫描走线GL2与第二栅极驱动电路GOA2的第二移位寄存器SR2电连接，第三个扫描线组GLS中的第一扫描走线GL1与第一栅极驱动电路GOA1的第三移位寄存器SR3电连接，第三个扫描线组GLS中的第二扫描走线GL2与第二栅极驱动电路GOA2的第三移位寄存器SR3电连接，…，第90个扫描线组GLS中的第一扫描走线GL1与第一栅极驱动电路GOA1的第九十移位寄存器SR90电连接，第90个扫描线组GLS中的第二扫描走线GL2与第二栅极驱动电路GOA2的第九十移位寄存器SR90电连接。在第二子面板SPNL2中，第一个扫描线组GLS中的第一扫描走线GL1与第三栅极驱动电路GOA3的第一移位寄存器SR1电连接，第一个扫描线组GLS中的第二扫描走线GL2与第四栅极驱动电路GOA4的第一移位寄存器SR1电连接，第二个扫描线组GLS中的第一扫描走线GL1与第三栅极驱动电路GOA3的第二移位寄存器SR2电连接，第二个扫描线组GLS中的第二扫描走线GL2与第四栅极驱动电路GOA4的第二移位寄存器SR2电连接，第三个扫描线组GLS中的第一扫描走线GL1与第三栅极 驱动电路GOA3的第三移位寄存器SR3电连接，第三个扫描线组GLS中的第二扫描走线GL2与第四栅极驱动电路GOA4的第三移位寄存器SR3电连接，…，第90个扫描线组GLS中的第一扫描走线GL1与第三栅极驱动电路GOA3的第九十移位寄存器SR90电连接，第90个扫描线组GLS中的第二扫描走线GL2与第四栅极驱动电路GOA4的第九十移位寄存器SR90电连接。如此，以便于通过两个栅极驱动电路GOA实现同一子面板SPNL的奇偶行扫描线GL的单独扫描，使得第一子面板SPNL1的第180行扫描线GL与第二子面板SPNL2的第一行扫描线GL的扫描时间差为子面板SPNL扫描周期的一半，有利于解决拼接显示面板PNL的画面撕裂的现象，以提高显示质量。
在另一种示例中，参见图11和图12，显示面板PNL包括沿列方向依次拼接的第一子面板SPNL1和第二子面板SPNL2。第一子面板SPNL1和第二子面板SPNL2的扫描线GL的数量均为179行，第一子面板SPNL1位于第二子面板SPNL2的上方。第一子面板SPNL1设有第一栅极驱动电路GOA1和第二栅极驱动电路GOA2，第二子面板SPNL2设有第三栅极驱动电路GOA3和第四栅极驱动电路GOA4，换言之，第一子面板SPNL1和第二子面板SPNL2上均设有两个栅极驱动电路GOA。第一栅极驱动电路GOA1和第三栅极驱动电路GOA3均包括依次级联的90个移位寄存器SR，即第一栅极驱动电路GOA1和第三栅极驱动电路GOA3均包括依次级联的第一移位寄存器SR1、第二移位寄存器SR2、第三移位寄存器SR3、…、第九十移位寄存器SR90，而第二栅极驱动电路GOA2和第四栅极驱动电路GOA4均包括依次级联的89个移位寄存器SR，即第二栅极驱动电路GOA2和第四栅极驱动电路GOA4均包括依次级联的第一移位寄存器SR1、第二移位寄存器SR2、第三移位寄存器SR3、…、第八十九移位寄存器SR89；第一子面板SPNL1和第二子面板SPNL2的扫描线GL分别分为90个依次相邻的扫描线组GLS，前89个扫描线组GLS包括依次相邻的两个扫描线GL，换言之，前89个扫描线组GLS包括依次相邻的第一扫描走线GL1和第二扫描走线GL2；第90个扫描线组GLS包括一个扫描线GL，换言之，第90个扫描线组GLS包括第一扫描走线GL1；其中，除第90个扫描线组GLS以外，同一个扫描线 组GLS中的两个扫描线GL分别通过两个栅极驱动电路GOA驱动，换言之，在第一子面板SPNL1中，第一个扫描线组GLS中的第一扫描走线GL1与第一栅极驱动电路GOA1的第一移位寄存器SR1电连接，第一个扫描线组GLS中的第二扫描走线GL2与第二栅极驱动电路GOA2的第一移位寄存器SR1电连接，第二个扫描线组GLS中的第一扫描走线GL1与第一栅极驱动电路GOA1的第二移位寄存器SR2电连接，第二个扫描线组GLS中的第二扫描走线GL2与第二栅极驱动电路GOA2的第二移位寄存器SR2电连接，第三个扫描线组GLS中的第一扫描走线GL1与第一栅极驱动电路GOA1的第三移位寄存器SR3电连接，第三个扫描线组GLS中的第二扫描走线GL2与第二栅极驱动电路GOA2的第三移位寄存器SR3电连接，…，第90个扫描线组GLS中的第一扫描走线GL1与第一栅极驱动电路GOA1的第九十移位寄存器SR90电连接。在第二子面板SPNL2中，第一个扫描线组GLS中的第一扫描走线GL1与第三栅极驱动电路GOA3的第一移位寄存器SR1电连接，第一个扫描线组GLS中的第二扫描走线GL2与第四栅极驱动电路GOA4的第一移位寄存器SR1电连接，第二个扫描线组GLS中的第一扫描走线GL1与第三栅极驱动电路GOA3的第二移位寄存器SR2电连接，第二个扫描线组GLS中的第二扫描走线GL2与第四栅极驱动电路GOA4的第二移位寄存器SR2电连接，第三个扫描线组GLS中的第一扫描走线GL1与第三栅极驱动电路GOA3的第三移位寄存器SR3电连接，第三个扫描线组GLS中的第二扫描走线GL2与第四栅极驱动电路GOA4的第三移位寄存器SR3电连接，…，第90个扫描线组GLS中的第一扫描走线GL1与第三栅极驱动电路GOA3的第九十移位寄存器SR90电连接。以便于通过两个栅极驱动电路GOA实现同一子面板SPNL的奇偶行扫描线GL的单独扫描，使得第一子面板SPNL1的第179行扫描线GL与第二子面板SPNL2的第一行扫描线GL的扫描时间差为子面板SPNL扫描周期的一半，有利于解决拼接显示面板PNL的画面撕裂的现象，以提高显示质量。
在本公开的一种实施方式中，所述栅极驱动电路GOA包括依次级联的多个移位寄存器SR；在相邻的两个子面板SPNL中，前一个所述子面板SPNL的第一参考栅极驱动电路的第一级移位寄存器SR的输入端 与后一个所述子面板SPNL的第二参考栅极驱动电路的第一级移位寄存器SR的输入端电连接；所述子面板SPNL的第一参考栅极驱动电路为驱动所述子面板SPNL的最后一行扫描线GL的栅极驱动电路GOA；所述子面板SPNL的第二参考栅极驱动电路为驱动所述子面板SPNL的第一行扫描线GL的栅极驱动电路GOA。
在一种示例中，第一参考栅极驱动电路为第二栅极驱动电路GOA2，第二参考栅极驱动电路为第三栅极驱动电路GOA3，第二栅极驱动电路GOA2的第一移位寄存器SR1的输入端与第三栅极驱动电路GOA3的第一移位寄存器SR1的输入端电连接，以使得第二栅极驱动电路GOA2的起始信号复用为第三栅极驱动电路GOA3的起始信号，相比于在第三栅极驱动电路GOA3单独加载起始信号，减少了走线的数量，从而使得第一子面板SPNL1的奇数行扫描线GL与第二子面板SPNL2的偶数行扫描线GL同时进行扫描，第一子面板SPNL1的偶数行扫描线GL与第二子面板SPNL2的奇数行扫描线GL同时进行扫描，以使得第一子面板SPNL1的第180行扫描线GL与第二子面板SPNL2的第一行扫描线GL的扫描时间差为子面板SPNL扫描周期的一半，有利于解决拼接显示面板PNL的画面撕裂的现象，以提高显示质量。
在另一种示例中，第一参考栅极驱动电路为第一栅极驱动电路GOA1，第二参考栅极驱动电路为第三栅极驱动电路GOA3，第一栅极驱动电路GOA1的第一移位寄存器SR1的输入端与第三栅极驱动电路GOA3的第一移位寄存器SR1的输入端电连接，以使得第一栅极驱动电路GOA1的起始信号复用为第三栅极驱动电路GOA3的起始信号，相比于在第三栅极驱动电路GOA3单独加载起始信号，减少了走线的数量，从而使得第一子面板SPNL1的奇数行扫描线GL与第二子面板SPNL2的奇数行扫描线GL同时进行扫描，第一子面板SPNL1的偶数行扫描线GL与第二子面板SPNL2的偶数行扫描线GL同时进行扫描，以使得第一子面板SPNL1的第179行扫描线GL与第二子面板SPNL2的第一行扫描线GL的扫描时间差为子面板SPNL扫描周期的一半，有利于解决拼接显示面板PNL的画面撕裂的现象，以提高显示质量。
在本公开的一种实施方式中，参见图9和图11，所述显示面板PNL 包括沿列方向依次拼接的第一子面板SPNL1和第二子面板SPNL2；所述第一子面板SPNL1具有用于驱动各个所述扫描线GL的第一栅极驱动电路GOA1和第二栅极驱动电路GOA2；所述第一栅极驱动电路GOA1用于驱动所述第一子面板SPNL1的奇数行扫描线GL，第二栅极驱动电路GOA2用于驱动所述第一子面板SPNL1的偶数行扫描线GL；所述第二子面板SPNL2具有用于驱动各个所述扫描线GL的第三栅极驱动电路GOA3和第四栅极驱动电路GOA4；所述第三栅极驱动电路GOA3用于驱动所述第二子面板SPNL2的奇数行扫描线GL，第四栅极驱动电路GOA4用于驱动第二子面板SPNL2的偶数行扫描线GL。
在一种示例中，参见图9和图10，显示面板PNL包括沿列方向依次拼接的第一子面板SPNL1和第二子面板SPNL2。第一子面板SPNL1和第二子面板SPNL2的扫描线GL的数量均为180行，第一子面板SPNL1位于第二子面板SPNL2的上方。第一子面板SPNL1设有第一栅极驱动电路GOA1和第二栅极驱动电路GOA2，第二子面板SPNL2设有第三栅极驱动电路GOA3和第四栅极驱动电路GOA4。第一子面板SPNL1和第二子面板SPNL2的扫描线GL分别分为90个依次相邻的扫描线组GLS，扫描线组GLS包括依次相邻的两个扫描线GL，换言之，扫描线组GLS包括依次相邻的第一扫描走线GL1和第二扫描走线GL2。其中，同一个扫描线组GLS中的两个扫描线GL分别通过两个栅极驱动电路GOA驱动，即在第一子面板SPNL1中，同一个扫描线组GLS中的第一扫描走线GL1通过第一栅极驱动电路GOA1驱动，同一个扫描线组GLS中的第二扫描走线GL2通过第二栅极驱动电路GOA2驱动；在第二子面板SPNL2中，同一个扫描线组GLS中的第一扫描走线GL1通过第三栅极驱动电路GOA3驱动，同一个扫描线组GLS中的第二扫描走线GL2通过第四栅极驱动电路GOA4驱动。
在另一种示例中，参见图11和图12，显示面板PNL包括沿列方向依次拼接的第一子面板SPNL1和第二子面板SPNL2。第一子面板SPNL1和第二子面板SPNL2的扫描线GL的数量均为179行，第一子面板SPNL1位于第二子面板SPNL2的上方。第一子面板SPNL1设有第一栅极驱动电路GOA1和第二栅极驱动电路GOA2，第二子面板SPNL2设有第三栅 极驱动电路GOA3和第四栅极驱动电路GOA4。第一子面板SPNL1和第二子面板SPNL2的扫描线GL分别分为90个依次相邻的扫描线组GLS，前89个扫描线组GLS包括依次相邻的两个扫描线GL，换言之，前89个扫描线组GLS包括依次相邻的第一扫描走线GL1和第二扫描走线GL2，第90个扫描线组GLS包括一个扫描线GL，换言之，第90个扫描线组GLS包括第一扫描走线GL1。其中，除第90个扫描线组GLS以外，在第一子面板SPNL1中，同一个扫描线组GLS中的第一扫描走线GL1通过第一栅极驱动电路GOA1驱动，同一个扫描线组GLS中的第二扫描走线GL2通过第二栅极驱动电路GOA2驱动；在第二子面板SPNL2中，同一个扫描线组GLS中的第一扫描走线GL1通过第三栅极驱动电路GOA3驱动，同一个扫描线组GLS中的第二扫描走线GL2通过第四栅极驱动电路GOA4驱动；而在第一子面板SPNL1中，第90个扫描线组GLS中的第一扫描走线GL1通过第一栅极驱动电路GOA1驱动；在第二子面板SPNL2中，第90个扫描线组GLS中的第一扫描走线GL1通过第三栅极驱动电路GOA3驱动。
在本公开的一种实施方式中，所述扫描线GL的行数为偶数，例如扫描线GL的行数可以为2、4、100、180等等。所述第一子面板SPNL1的所述第二栅极驱动电路GOA2的起始信号与所述第二子面板SPNL2的所述第三栅极驱动电路GOA3的起始信号的时刻相同。
在一种示例中，参见图9和图10，显示面板PNL包括沿列方向依次拼接的第一子面板SPNL1和第二子面板SPNL2。第一子面板SPNL1和第二子面板SPNL2的扫描线GL的数量均为180行，第一子面板SPNL1位于第二子面板SPNL2的上方。第一子面板SPNL1设有第一栅极驱动电路GOA1和第二栅极驱动电路GOA2，第二子面板SPNL2设有第三栅极驱动电路GOA3和第四栅极驱动电路GOA4，换言之，第一子面板SPNL1和第二子面板SPNL2上均设有两个栅极驱动电路GOA。每个栅极驱动电路GOA均包括依次级联的90个移位寄存器SR，即每个栅极驱动电路GOA均包括依次级联的第一移位寄存器SR1、第二移位寄存器SR2、第三移位寄存器SR3、…、第九十移位寄存器SR90；第一子面板SPNL1和第二子面板SPNL2的扫描线GL分别分为90个依次相邻的扫 描线组GLS，扫描线组GLS包括依次相邻的两个扫描线GL，换言之，扫描线组GLS包括依次相邻的第一扫描走线GL1和第二扫描走线GL2。其中，同一个扫描线组GLS中的两个扫描线GL分别通过两个栅极驱动电路GOA驱动，换言之，在第一子面板SPNL1中，第一个扫描线组GLS中的第一扫描走线GL1与第一栅极驱动电路GOA1的第一移位寄存器SR1电连接，第一个扫描线组GLS中的第二扫描走线GL2与第二栅极驱动电路GOA2的第一移位寄存器SR1电连接，第二个扫描线组GLS中的第一扫描走线GL1与第一栅极驱动电路GOA1的第二移位寄存器SR2电连接，第二个扫描线组GLS中的第二扫描走线GL2与第二栅极驱动电路GOA2的第二移位寄存器SR2电连接，第三个扫描线组GLS中的第一扫描走线GL1与第一栅极驱动电路GOA1的第三移位寄存器SR3电连接，第三个扫描线组GLS中的第二扫描走线GL2与第二栅极驱动电路GOA2的第三移位寄存器SR3电连接，…，第90个扫描线组GLS中的第一扫描走线GL1与第一栅极驱动电路GOA1的第九十移位寄存器SR90电连接，第90个扫描线组GLS中的第二扫描走线GL2与第二栅极驱动电路GOA2的第九十移位寄存器SR90电连接。在第二子面板SPNL2中，第一个扫描线组GLS中的第一扫描走线GL1与第三栅极驱动电路GOA3的第一移位寄存器SR1电连接，第一个扫描线组GLS中的第二扫描走线GL2与第四栅极驱动电路GOA4的第一移位寄存器SR1电连接，第二个扫描线组GLS中的第一扫描走线GL1与第三栅极驱动电路GOA3的第二移位寄存器SR2电连接，第二个扫描线组GLS中的第二扫描走线GL2与第四栅极驱动电路GOA4的第二移位寄存器SR2电连接，第三个扫描线组GLS中的第一扫描走线GL1与第三栅极驱动电路GOA3的第三移位寄存器SR3电连接，第三个扫描线组GLS中的第二扫描走线GL2与第四栅极驱动电路GOA4的第三移位寄存器SR3电连接，…，第90个扫描线组GLS中的第一扫描走线GL1与第三栅极驱动电路GOA3的第九十移位寄存器SR90电连接，第90个扫描线组GLS中的第二扫描走线GL2与第四栅极驱动电路GOA4的第九十移位寄存器SR90电连接。第一栅极驱动电路GOA1的第一移位寄存器SR1的输入端与第四栅极驱动电路GOA4的第一移位寄存器SR1的输入端电 连接，以使得第一栅极驱动电路GOA1的第一移位寄存器SR1与第四栅极驱动电路GOA4的第一移位寄存器SR1加载相同时刻的起始信号，从而使得第一子面板SPNL1的奇数行扫描线GL与第二子面板SPNL2的偶数行扫描线GL同时进行扫描，耗费半个扫描周期的时长；之后第一子面板SPNL1的偶数行扫描线GL与第二子面板SPNL2的奇数行扫描线GL同时进行扫描，此过程也耗费半个扫描周期的时长；总之，从第一子面板SPNL1的第180行扫描线GL到第二子面板SPNL2的第一行扫描线GL扫描时间差为半个扫描周期的时长。如此，以便于通过两个栅极驱动电路GOA实现同一子面板SPNL的奇偶行扫描线GL的单独扫描，使得第一子面板SPNL1的第180行扫描线GL与第二子面板SPNL2的第一行扫描线GL的扫描时间差为子面板SPNL扫描周期的一半，有利于解决拼接显示面板PNL的画面撕裂的现象，以提高显示质量。
在另一种示例中，先将第一子面板SPNL1的偶数行扫描线GL与第二子面板SPNL2的奇数行扫描线GL同时进行扫描，之后将第一子面板SPNL1的奇数行扫描线GL与第二子面板SPNL2的偶数行扫描线GL同时进行扫描，以便于通过两个栅极驱动电路GOA实现同一子面板SPNL的奇偶行扫描线GL的单独扫描，使得第一子面板SPNL1的第180行扫描线GL与第二子面板SPNL2的第一行扫描线GL的扫描时间差为子面板SPNL扫描周期的一半，有利于解决拼接显示面板PNL的画面撕裂的现象，以提高显示质量。
其中，参见图9和图13，第一栅极驱动电路GOA1的第一移位寄存器SR1的输入端加载第一起始信号GSTV1，第二栅极驱动电路GOA2的第一移位寄存器SR1的输入端加载第二起始信号GSTV2，第三栅极驱动电路GOA3的第一移位寄存器SR1的输入端加载第二起始信号GSTV2，第四栅极驱动电路GOA4的第一移位寄存器SR1的输入端加载第一起始信号GSTV1，且第一起始信号GSTV1的导通电平开始的时刻比第二起始信号GSTV2的导通电平开始的时刻早1/2个扫描周期。在本实施方式中，第一起始信号GSTV1和第二起始信号GSTV2的导通电平为低电平，截止电平为高电平。在本公开的另一些实施方式中，第一起始信号GSTV1和第二起始信号GSTV2的导通电平为高电平，截止电平为低电 平。
在本公开的一种实施方式中，所述扫描线GL的行数为奇数；所述第一子面板SPNL1的所述第一栅极驱动电路GOA1的起始信号与所述第二子面板SPNL2的所述第三栅极驱动电路GOA3的起始信号的时刻相同。
在一种示例中，参见图11和图12，显示面板PNL包括沿列方向依次拼接的第一子面板SPNL1和第二子面板SPNL2。第一子面板SPNL1和第二子面板SPNL2的扫描线GL的数量均为179行，第一子面板SPNL1位于第二子面板SPNL2的上方。第一子面板SPNL1设有第一栅极驱动电路GOA1和第二栅极驱动电路GOA2，第二子面板SPNL2设有第三栅极驱动电路GOA3和第四栅极驱动电路GOA4，换言之，第一子面板SPNL1和第二子面板SPNL2上均设有两个栅极驱动电路GOA，第一栅极驱动电路GOA1和第三栅极驱动电路GOA3均包括依次级联的90个移位寄存器SR，即第一栅极驱动电路GOA1和第三栅极驱动电路GOA3均包括依次级联的第一移位寄存器SR1、第二移位寄存器SR2、第三移位寄存器SR3、…、第九十移位寄存器SR90，而第二栅极驱动电路GOA2和第四栅极驱动电路GOA4均包括依次级联的89个移位寄存器SR，即第二栅极驱动电路GOA2和第四栅极驱动电路GOA4均包括依次级联的第一移位寄存器SR1、第二移位寄存器SR2、第三移位寄存器SR3、…、第八十九移位寄存器SR89。第一子面板SPNL1和第二子面板SPNL2的扫描线GL分别分为90个依次相邻的扫描线组GLS，前89个扫描线组GLS包括依次相邻的两个扫描线GL，换言之，前89个扫描线组GLS包括依次相邻的第一扫描走线GL1和第二扫描走线GL2；第90个扫描线组GLS包括一个扫描线GL，换言之，第90个扫描线组GLS包括第一扫描走线GL1。其中，除第90个扫描线组GLS以外，同一个扫描线组GLS中的两个扫描线GL分别通过两个栅极驱动电路GOA驱动，换言之，在第一子面板SPNL1中，第一个扫描线组GLS中的第一扫描走线GL1与第一栅极驱动电路GOA1的第一移位寄存器SR1电连接，第一个扫描线组GLS中的第二扫描走线GL2与第二栅极驱动电路GOA2的第一移位寄存器SR1电连接，第二个扫描线组GLS中的第一扫描走线GL1与第一栅极驱动电路GOA1的第二移位寄存器SR2电连接，第二个 扫描线组GLS中的第二扫描走线GL2与第二栅极驱动电路GOA2的第二移位寄存器SR2电连接，第三个扫描线组GLS中的第一扫描走线GL1与第一栅极驱动电路GOA1的第三移位寄存器SR3电连接，第三个扫描线组GLS中的第二扫描走线GL2与第二栅极驱动电路GOA2的第三移位寄存器SR3电连接，…，第90个扫描线组GLS中的第一扫描走线GL1与第一栅极驱动电路GOA1的第九十移位寄存器SR90电连接；在第二子面板SPNL2中，第一个扫描线组GLS中的第一扫描走线GL1与第三栅极驱动电路GOA3的第一移位寄存器SR1电连接，第一个扫描线组GLS中的第二扫描走线GL2与第四栅极驱动电路GOA4的第一移位寄存器SR1电连接，第二个扫描线组GLS中的第一扫描走线GL1与第三栅极驱动电路GOA3的第二移位寄存器SR2电连接，第二个扫描线组GLS中的第二扫描走线GL2与第四栅极驱动电路GOA4的第二移位寄存器SR2电连接，第三个扫描线组GLS中的第一扫描走线GL1与第三栅极驱动电路GOA3的第三移位寄存器SR3电连接，第三个扫描线组GLS中的第二扫描走线GL2与第四栅极驱动电路GOA4的第三移位寄存器SR3电连接，…，第90个扫描线组GLS中的第一扫描走线GL1与第三栅极驱动电路GOA3的第九十移位寄存器SR90电连接。第一栅极驱动电路GOA1的第一移位寄存器SR1的输入端与第三栅极驱动电路GOA3的第一移位寄存器SR1的输入端电连接，以使得第一栅极驱动电路GOA1的第一移位寄存器SR1与第三栅极驱动电路GOA3的第一移位寄存器SR1加载相同时刻的起始信号。第一子面板SPNL1的奇数行扫描线GL与第二子面板SPNL2的奇数行扫描线GL同时进行扫描，耗费半个扫描周期的时长；之后第一子面板SPNL1的偶数行扫描线GL与第二子面板SPNL2的偶数行扫描线GL同时进行扫描，也只耗费半个扫描周期的时长；总之，从第一子面板SPNL1的第179行扫描线GL到第二子面板SPNL2的第一行扫描线GL扫描时间差为半个扫描周期的时长。如此，以便于通过两个栅极驱动电路GOA实现同一子面板SPNL的奇偶行扫描线GL的单独扫描，使得第一子面板SPNL1的第179行扫描线GL与第二子面板SPNL2的第一行扫描线GL的扫描时间差为子面板SPNL扫描周期的一半，有利于解决拼接显示面板PNL的画面撕裂的现象，以 提高显示质量。
在另一种示例中，使得第一子面板SPNL1的偶数行扫描线GL与第二子面板SPNL2的偶数行扫描线GL同时进行扫描，之后第一子面板SPNL1的奇数行扫描线GL与第二子面板SPNL2的奇数行扫描线GL同时进行扫描；以便于通过两个栅极驱动电路GOA实现同一子面板SPNL的奇偶行扫描线GL的单独扫描，使得第一子面板SPNL1的第179行扫描线GL与第二子面板SPNL2的第一行扫描线GL的扫描时间差为子面板SPNL扫描周期的一半，有利于解决拼接显示面板PNL的画面撕裂的现象，以提高显示质量。
其中，参见图11和图13，第一栅极驱动电路GOA1的第一移位寄存器SR1的输入端加载第一起始信号GSTV1，第二栅极驱动电路GOA2的第一移位寄存器SR1的输入端加载第二起始信号GSTV2，第三栅极驱动电路GOA3的第一移位寄存器SR1的输入端加载第一起始信号GSTV1，第四栅极驱动电路GOA4的第一移位寄存器SR1的输入端加载第二起始信号GSTV2，且第一起始信号GSTV1的导通电平开始的时刻比第二起始信号GSTV2的导通电平开始的时刻早1/2个扫描周期。在本实施方式中，第一起始信号GSTV1和第二起始信号GSTV2的导通电平为低电平，截止电平为高电平。在本公开的另一些实施方式中，第一起始信号GSTV1和第二起始信号GSTV2的导通电平为高电平。截止电平为低电平。
在本公开的一种实施方式中，所述显示面板PNL为Mini LED显示面板、Micro LED显示面板、OLED显示面板、QLED显示面板或者LCD显示面板。在一种示例中，显示面板PNL为Mini LED。在另一种示例中，显示面板PNL为Micro LED。
在本公开的一种实施方式中，所述子面板SPNL具有与各个子像素行一一对应的发光控制走线，所述发光控制走线用于向像素驱动电路PDC加载发光控制信号EM；各个所述发光控制走线相互电连接。
具体的，参见图14，发光控制信号EM的导通电平开始的时刻在所有行的扫描线GL扫描完之后生效，换言之，在所有栅极驱动电路GOA扫描完之后，发光控制信号EM的导通电平开始生效，即在第一栅极驱 动电路GOA1、第二栅极驱动电路GOA2、第三栅极驱动电路GOA3和第四栅极驱动电路GOA4扫描完之后，发光控制信号EM的导通电平开始生效，以使得各个子像素PIX同时进行发光。需要说明的是，在本实施方式中，图14中所示的第一栅极驱动电路GOA1、第二栅极驱动电路GOA2、第三栅极驱动电路GOA3和第四栅极驱动电路GOA4分别为四个子面板SPNL一一对应的栅极驱动电路GOA。例如，第一个子面板SPNL对应第一栅极驱动电路GOA1，第二个子面板SPNL对应第二栅极驱动电路GOA2，第三个子面板SPNL对应第三栅极驱动电路GOA3，第四个子面板SPNL对应第四栅极驱动电路GOA4，在整个显示面板PNL的所有栅极驱动电路GOA扫描完之后，发光控制信号EM将显示面板PNL的所有子像素PIX同时点亮；发光控制信号EM的导通电平为低电平，截止电平为高电平。
在一种示例中，第一子面板SPNL1和第二子面板SPNL2的180行扫描线GL扫描完之后，开始接入发光控制信号EM的导通电平，从而点亮所有的子像素PIX，如此，第一子面板SPNL1的第180行和第二子面板SPNL2的第一行的子像素PIX不存在点亮时间差，能够有效解决画面撕裂现象。
在另一种示例中，第一子面板SPNL1和第二子面板SPNL2的179行扫描线GL扫描完之后，开始接入发光控制信号EM的导通电平，从而点亮所有的子像素PIX，如此，第一子面板SPNL1的第179行和第二子面板SPNL2的第一行的子像素PIX不存在点亮时间差，能够有效解决画面撕裂现象。
需要说明的是，控制子像素PIX点亮时间的方式需要在扫描频率较高时使用，即需要在显示面板PNL进行快速扫描的情况下使用，例如扫描频率为120Hz或144Hz等，以避免每个子面板SPNL每一帧的关闭时间过长而导致人眼识别到屏幕闪烁的情况。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说 明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (13)

  1. 一种显示面板，包括沿列方向依次拼接的至少两个子面板；
    任意一个所述子面板包括阵列分布的子像素和与各个子像素行一一对应的扫描线；
    所述子面板具有用于驱动各个所述扫描线的多个栅极驱动电路；
    其中，在相邻的两个所述子面板中，前一个所述子面板的最后一行所述扫描线所电连接的所述栅极驱动电路的起始信号，与后一个所述子面板的第一行所述扫描线所电连接的所述栅极驱动电路的起始信号的时刻相同。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板包括两个子面板。
  3. 根据权利要求1所述的显示面板，其中，所述子面板包括两个栅极驱动电路。
  4. 根据权利要求1所述的显示面板，其中，所述子面板上设置m个栅极驱动电路；m为大于1的正整数；
    所述扫描线分为多个依次相邻的扫描线组，所述扫描线组包括依次相邻的m个扫描线；
    同一所述扫描线组中的m个所述扫描线分别通过m个所述栅极驱动电路驱动。
  5. 根据权利要求4所述的显示面板，其中，所述栅极驱动电路均包括依次级联的多个移位寄存器；
    第i个所述扫描线组中的第j个所述扫描线，与第j个所述栅极驱动电路的第i个所述移位寄存器电连接；j为在1～m之间的正整数。
  6. 根据权利要求1所述的显示面板，其中，所述栅极驱动电路包括依次级联的多个移位寄存器；
    所述子面板的第一参考栅极驱动电路为驱动所述子面板的最后一行扫描线的栅极驱动电路；所述子面板的第二参考栅极驱动电路为驱动所述子面板的第一行扫描线的栅极驱动电路；
    在相邻的两个子面板中，前一个所述子面板的第一参考栅极驱动电路的第一级移位寄存器的输入端与后一个所述子面板的第二参考栅极驱 动电路的第一级移位寄存器的输入端电连接。
  7. 根据权利要求1所述的显示面板，其中，所述显示面板包括沿列方向依次拼接的第一子面板和第二子面板；
    所述第一子面板具有用于驱动各个所述扫描线的第一栅极驱动电路和第二栅极驱动电路；所述第一栅极驱动电路用于驱动所述第一子面板的奇数行扫描线，第二栅极驱动电路用于驱动所述第一子面板的偶数行扫描线；
    所述第二子面板具有用于驱动各个所述扫描线的第三栅极驱动电路和第四栅极驱动电路；所述第三栅极驱动电路用于驱动所述第二子面板的奇数行扫描线，第四栅极驱动电路用于驱动第二子面板的偶数行扫描线。
  8. 根据权利要求7所述的显示面板，其中，所述子面板的扫描线的行数为偶数；所述第一子面板的所述第二栅极驱动电路的起始信号与所述第二子面板的所述第三栅极驱动电路的起始信号的时刻相同。
  9. 根据权利要求7所述的显示面板，其中，所述子面板的扫描线的行数为奇数；所述第一子面板的所述第一栅极驱动电路的起始信号与所述第二子面板的所述第三栅极驱动电路的起始信号的时刻相同。
  10. 根据权利要求8～9任一项所述的显示面板，其中，所述第一栅极驱动电路的起始信号的开始时刻比所述第二栅极驱动电路的起始信号的开始时刻早二分之一个扫描周期。
  11. 根据权利要求1～9任一项所述的显示面板，其中，所述子面板具有与各个子像素行一一对应的发光控制走线，所述发光控制走线用于向像素驱动电路加载发光控制信号；
    各个所述发光控制走线相互电连接。
  12. 根据权利要求1～9任一项所述的显示面板，其中，所述显示面板为Mini LED显示面板、Micro LED显示面板、OLED显示面板、QLED显示面板或者LCD显示面板。
  13. 一种显示装置，其中，包括如权利要求1～12任一项所述的显示面板。
PCT/CN2024/079057 2024-02-28 2024-02-28 显示面板及显示装置 Pending WO2025179489A1 (zh)

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