WO2025086498A1 - 像素驱动电路以及显示面板 - Google Patents

像素驱动电路以及显示面板 Download PDF

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Publication number
WO2025086498A1
WO2025086498A1 PCT/CN2024/074828 CN2024074828W WO2025086498A1 WO 2025086498 A1 WO2025086498 A1 WO 2025086498A1 CN 2024074828 W CN2024074828 W CN 2024074828W WO 2025086498 A1 WO2025086498 A1 WO 2025086498A1
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WIPO (PCT)
Prior art keywords
transistor
electrode
driving circuit
pixel driving
node
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PCT/CN2024/074828
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English (en)
French (fr)
Inventor
谷朝辉
李皓哲
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EverDisplay Optronics Shanghai Co Ltd
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EverDisplay Optronics Shanghai Co Ltd
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Publication of WO2025086498A1 publication Critical patent/WO2025086498A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present invention relates to the field of display panel circuits, and in particular to a pixel driving circuit and a display panel.
  • the OLED display panel includes a pixel array and a pixel driving circuit that controls the pixel array.
  • the light-emitting pixels in the pixel array emit light under the joint action of the pixel driving circuit, the scanning driving circuit and the light-emitting driving circuit.
  • the present invention provides a pixel driving circuit and a display panel to at least solve the above problems.
  • One aspect of the present invention provides a pixel driving circuit, comprising:
  • a first transistor wherein a first electrode of the first transistor is connected to the data signal, a second electrode is connected to the third node, and a gate is connected to the second scanning signal;
  • a second transistor wherein a first electrode of the second transistor is connected to the first node, a second electrode of the second transistor is connected to the fourth node, and a gate of the second transistor is connected to the second node;
  • a third transistor wherein a first electrode of the third transistor is connected to the third node, a second electrode of the third transistor is connected to the second node, and a gate of the third transistor is connected to a third scanning signal;
  • a fourth transistor wherein a first electrode of the fourth transistor is connected to the first power supply voltage, a second electrode of the fourth transistor is connected to the first node, and a gate of the fourth transistor is connected to a light emitting control signal;
  • a fifth transistor wherein a first electrode of the fifth transistor is connected to the fourth node, a second electrode of the fifth transistor is connected to the first electrode of the light emitting diode, and a gate of the fifth transistor is connected to the light emitting control signal;
  • a sixth transistor wherein a first electrode of the sixth transistor is connected to the third node, a second electrode of the sixth transistor is connected to the first reference voltage, and a gate of the sixth transistor is connected to the first scanning signal;
  • a seventh transistor wherein a second electrode of the seventh transistor is connected to the fourth node, and a gate of the seventh transistor is connected to a fourth scanning signal;
  • a first capacitor wherein a first electrode of the first capacitor is connected to the second node, and a second electrode of the first capacitor is connected to the first node;
  • a second capacitor wherein a first electrode of the second capacitor is connected to the first node, and a second electrode is connected to the light emitting control signal.
  • the second electrode of the light emitting diode is connected to a second power supply voltage.
  • a first electrode of the seventh transistor is connected to a second power supply voltage.
  • a first electrode of the seventh transistor is connected to a second reference voltage.
  • the first transistor to the seventh transistor are all P-type MOS transistors.
  • the first transistor to the second transistor and the fourth transistor to the seventh transistor are all P-type MOS transistors, and the third transistor is an N-type MOS transistor.
  • the frequencies of the light emitting control signal, the third scanning signal and the fourth scanning signal are the same, the frequencies of the first scanning signal and the second scanning signal are the same, and the frequency of the light emitting control signal is at least twice that of the first scanning signal.
  • the first falling edge of the third scan signal is at the same time as the falling edge of the first scan signal, and the first rising edge of the third scan signal is at the same time as the rising edge of the second scan signal.
  • the first rising edge of the third scan signal is at the same time as the falling edge of the first scan signal, and the first falling edge of the third scan signal is at the same time as the rising edge of the second scan signal.
  • the first falling edge and the first rising edge of the fourth scanning signal are at the same time as the falling edge and the rising edge of the first scanning signal.
  • Another aspect of the present invention further provides a display panel, comprising any one of the above-mentioned pixel driving circuits.
  • the pixel driving circuit and display panel of the present invention form the main components of the emission charge recovery structure and the high-frequency anode reset structure through the high-frequency third scanning signal, the fourth scanning signal, the third transistor and the seventh transistor, thereby reducing the brightness fluctuation of the display panel caused by the defective charge emission and improving the picture quality; at the same time, by storing the gate-source potential difference by capacitor and connecting the constant potential as a reference point, the influence of the voltage drop of the power supply voltage on the brightness is reduced; in addition, by separating the threshold voltage sampling and the data storage, full compensation is achieved at a high refresh rate, thereby improving the picture quality.
  • FIG1 is a schematic diagram showing a circuit structure of a display panel of the present invention.
  • FIG2 is a circuit diagram showing a first embodiment of a pixel driving circuit according to the present invention.
  • FIG3 is a waveform diagram showing the operation of the pixel driving circuit shown in FIG2 ;
  • FIG4 is a schematic diagram showing the working state of the pixel driving circuit at stage t1 in FIG3 ;
  • FIG5 is a schematic diagram showing the working state of the pixel driving circuit in phase t2 in FIG3 ;
  • FIG6 is a schematic diagram showing the working state of the pixel driving circuit at stage t3 in FIG3 ;
  • FIG. 7 is a schematic diagram showing the working state of the pixel driving circuit at stage t4 in FIG. 3 ;
  • FIG8 is a schematic diagram showing the working state of the pixel driving circuit at stage t5 in FIG3 ;
  • FIG9 is a schematic diagram showing the working state of the pixel driving circuit at stage t6 in FIG3 ;
  • FIG10 is a schematic diagram showing the working state of the pixel driving circuit at stage t7 in FIG3 ;
  • FIG11 is a schematic diagram showing the working state of the pixel driving circuit at stage t8 in FIG3 ;
  • FIG12 is a circuit diagram showing a second embodiment of a pixel driving circuit according to the present invention.
  • FIG13 is a waveform diagram showing the operation of the pixel driving circuit shown in FIG12 ;
  • FIG. 14 is a circuit diagram showing a third embodiment of a pixel driving circuit according to the present invention.
  • Reference numerals 10 Display Panel 11 Display area 111 Pixel driving circuit 121 Data Driver DATA Data signal ELVDD First power supply voltage ELVSS Second supply voltage EM lighting control signal Scan1 The first scanning signal Scan2 The second scanning signal Scan3 The third scanning signal Scan4 The fourth scanning signal Ref1 First reference voltage Ref2 Second reference voltage T1 first transistor T2 Second transistor T3 The third transistor T4 Fourth transistor T5 Fifth transistor T6 Sixth transistor T7 Seventh transistor C1 First capacitor C2 Second capacitor N1 First Node N2 Second Node N3 Third Node N4 Fourth Node D Light Emitting Diode
  • FIG1 is a schematic diagram of the circuit structure of a display panel of the present invention.
  • FIG2 is a circuit diagram of a first embodiment of a pixel driving circuit of the present invention.
  • FIG12 is a circuit diagram of a second embodiment of a pixel driving circuit of the present invention.
  • FIG14 is a circuit diagram of a third embodiment of a pixel driving circuit of the present invention. As shown in FIGS.
  • the present invention discloses some pixel driving circuits 111 and a display panel 10, wherein the pixel driving circuit 111 at least includes: a first transistor to a seventh transistor, a first capacitor to a second capacitor, 1 data signal line, 1 light emitting control signal line, and 4 scanning signal lines.
  • the pixel driving circuit 111 and the display panel 10 of the present invention control the third transistor T3 and the seventh transistor T7 through the high-frequency third scanning signal Scan3 and the fourth scanning signal Scan4, which together form the main components of the emission charge recovery structure and the high-frequency anode reset structure, thereby reducing the brightness fluctuation of the display panel caused by the emission of defective charges and improving the picture quality.
  • one aspect of the present invention provides a display panel 10, which includes a display area 11 and a non-display area.
  • a scanning drive circuit, a light-emitting drive circuit and a data driver 121 are located in the non-display area of the display panel 10.
  • a plurality of data signal lines are connected to the data driver 121, and the data driver 121 provides data signals DATA to the light-emitting pixels through the plurality of data signal lines.
  • the display area 11 includes light-emitting pixels arranged in an array, and each light-emitting pixel has a pixel drive circuit 111 for controlling its light emission.
  • the light-emitting pixel emits light at least under the joint action of the scanning drive circuit, the light-emitting drive circuit, the pixel drive circuit 111 and the data driver 121.
  • the pixel driving circuit 111 of the first embodiment of the present invention includes: a first transistor T1 to a seventh transistor T7, and a first capacitor C1 to a second capacitor C2.
  • the first electrode of the first transistor T1 is connected to the data signal DATA
  • the second electrode is connected to the third node N3, and the gate is connected to the second scan signal Scan2.
  • the first electrode of the second transistor T2 is connected to the first node N1, the second electrode is connected to the fourth node N4, and the gate is connected to the second node N2.
  • the first electrode of the third transistor T3 is connected to the third node N3, the second electrode is connected to the second node N2, and the gate is connected to the third scan signal Scan3.
  • the first electrode of the fourth transistor T4 is connected to the first power supply voltage ELVDD, the second electrode is connected to the first node N1, and the gate is connected to the light control signal EM.
  • the first electrode of the fifth transistor T5 is connected to the fourth node N4, the second electrode is connected to the first electrode of the light emitting diode D, and the gate is connected to the light control signal EM.
  • the first electrode of the sixth transistor T6 is connected to the third node N3, the second electrode is connected to the first reference voltage Ref1, and the gate is connected to the first scan signal Scan1.
  • the second electrode of the seventh transistor T7 is connected to the fourth node N4, and the gate is connected to the fourth scan signal Scan4.
  • the first electrode of the first capacitor C1 is connected to the second node N2, and the second electrode is connected to the first node N1.
  • the first electrode of the second capacitor C2 is connected to the first node N1, and the second electrode is connected to the light emitting control signal EM.
  • the first electrode of the seventh transistor T7 is connected to the second power supply voltage ELVSS.
  • the second electrode of the light emitting diode D is connected to the second power supply voltage ELVSS.
  • the light emitting diode D can be OLED or AMOLED. Active-matrix organic light emitting diode (AMOLED), the first electrode of the light emitting diode D is an anode, and the second electrode is a cathode.
  • the first power supply voltage ELVDD is a positive power supply voltage
  • the second power supply voltage ELVSS is a negative power supply voltage, but it is not limited thereto.
  • the first transistor T1 to the seventh transistor T7 are all P-type MOS tubes.
  • P-type MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET
  • the control end of the PMOS tube is the gate
  • the first pole is the source
  • the second pole is the drain
  • the first pole is the drain and the second pole is the source.
  • the on level of the PMOS tube is a low level
  • the off level is a high level.
  • the high and low levels of the transistors when they are turned on and off in the following text are all based on PMOS tubes as an example. When other corresponding transistor types are selected according to design requirements, the high and low levels of their on and off will also change accordingly.
  • the first reference voltage Ref1 is constant, and its voltage is lower than the lowest potential of the data signal DATA. In other embodiments, the first reference voltage Ref1 can also be slightly adjusted to meet specific display requirements.
  • Fig. 3 shows a waveform diagram of the pixel driving circuit shown in Fig. 2 when it is working.
  • Fig. 4 shows a schematic diagram of the working state of the pixel driving circuit at stage t1 in Fig. 3.
  • Fig. 5 shows a schematic diagram of the working state of the pixel driving circuit at stage t2 in Fig. 3.
  • Fig. 6 shows a schematic diagram of the working state of the pixel driving circuit at stage t3 in Fig. 3.
  • Fig. 7 shows a schematic diagram of the working state of the pixel driving circuit at stage t4 in Fig. 3.
  • Fig. 8 shows a schematic diagram of the working state of the pixel driving circuit at stage t5 in Fig. 3.
  • Fig. 3 shows a waveform diagram of the pixel driving circuit shown in Fig. 2 when it is working.
  • Fig. 4 shows a schematic diagram of the working state of the pixel driving circuit at stage t1 in Fig. 3.
  • Fig. 5 shows a schematic diagram of
  • FIG. 9 shows a schematic diagram of the working state of the pixel driving circuit at stage t6 in Fig. 3.
  • Fig. 10 shows a schematic diagram of the working state of the pixel driving circuit at stage t7 in Fig. 3.
  • Fig. 11 shows a schematic diagram of the working state of the pixel driving circuit at stage t8 in Fig. 3.
  • the pixel driving circuit 111 in this embodiment can operate at a low frequency, where the low frequency means that the operating frequency is less than 60Hz, but the minimum operating frequency is 1Hz, but it is not limited to this.
  • FIG. 3 is a timing diagram of the pixel driving circuit 111 of the present invention when the operating frequency is 60Hz and black insertion and light emission are performed twice in each frame.
  • the pixel driving circuit 111 of the present invention can also insert black and emit light multiple times in each frame, and it only needs to repeat the t5 to t8 stages after the t1 to t4 stages. The following is an example of two times:
  • the light control signal EM, the third scan signal Scan3 and the fourth scan signal Scan4 all include two falling edges and two rising edges.
  • the first scan signal Scan1 and the second scan signal Scan2 all include only one falling edge and one rising edge. That is, within one frame time, the frequencies of the light control signal EM, the third scan signal Scan3 and the fourth scan signal Scan4 are the same, the frequencies of the first scan signal Scan1 and the second scan signal Scan2 are the same, and the frequency of the light control signal EM is twice that of the first scan signal Scan1.
  • the first falling edge of the third scan signal Scan3 is at the same time as the falling edge of the first scan signal Scan1
  • the first rising edge of the third scan signal Scan3 is at the same time as the rising edge of the second scan signal Scan2.
  • the first falling edge and the first rising edge of the fourth scan signal Scan4 are at the same time as the falling edge and the rising edge of the first scan signal Scan1.
  • the working process of the pixel driving circuit 111 is divided into 8 stages, namely t1 to t8.
  • the light-emitting diode D in the above-mentioned pixel driving circuit 111 completes the process from black insertion to light emission twice.
  • the “ ⁇ ” in FIGS. 4 to 11 indicates that the transistor is cut off.
  • the relationship between the input and light emission of the pixel driving circuit 111 in the above-mentioned 8 processes is analyzed below in combination with the waveform diagram of FIG3 and the circuit diagram of FIG2 :
  • the light-emitting control signal EM is input at a low level
  • the first scan signal Scan1 is input at a low level
  • the second scan signal Scan2 is input at a high level
  • the third scan signal Scan3 is input at a low level
  • the fourth scan signal Scan4 is input at a low level.
  • the first transistor T1 is turned off, and the second transistor T2 to the seventh transistor T7 are turned on.
  • the seventh transistor T7 since the seventh transistor T7 is turned on, the light-emitting diode D is short-circuited, and no light is emitted at this time.
  • This phase is a reset phase.
  • the first reference voltage Ref1 writes a low potential to the second node N2, that is, the gate of the second transistor T2, through the sixth transistor T6 and the third transistor T3 to reset the second transistor T2.
  • the third transistor T3 is turned on and captures the charge from the first reference voltage Ref1 through the sixth transistor T6.
  • the light emitting control signal EM is input at a high level
  • the first scanning signal Scan1 is input at a low level
  • the second scanning signal Scan2 is input at a high level
  • the third scanning signal Scan3 is input at a low level
  • the fourth scanning signal Scan4 is input at a low level.
  • T1 the fourth transistor T4 and the fifth transistor T5 are turned off
  • the second transistor T2, the third transistor T3, the sixth transistor T6 and the seventh transistor T7 are turned on.
  • the light-emitting control signal EM inputs a high level to turn off the fourth transistor T4 and the fifth transistor T5, and the light-emitting diode D does not emit light.
  • the first reference voltage Ref1 continues to write a low potential to the second node N2, that is, the gate of the second transistor T2, through the sixth transistor T6 and the third transistor T3, to record the threshold voltage Vth of the second transistor T2.
  • the potential of the first node N1 is raised through the coupling of the second capacitor C2.
  • the second transistor T2 since the gate potential is the first reference voltage Ref1, the second transistor T2 is in the open state, and the second transistor T2 connects the first node N1 and the fourth node N4. Therefore, the potential of the first node N1 will drop to VRef1-Vth, and the potential difference stored in the first capacitor C1 is Vth.
  • the third transistor T3 is turned on and continues to capture the charge from the first reference voltage Ref1 through the sixth transistor T6.
  • the light-emitting control signal EM inputs a high level
  • the first scan signal Scan1 inputs a high level
  • the second scan signal Scan2 inputs a low level
  • the third scan signal Scan3 inputs a low level
  • the fourth scan signal Scan4 inputs a high level.
  • the fourth transistor T4 to the seventh transistor T7 are turned off, and the first transistor T1 to the third transistor T3 are turned on.
  • the light-emitting control signal EM inputs a high level to turn off the fourth transistor T4 and the fifth transistor T5, and the light-emitting diode D does not emit light.
  • the data signal DATA writes the data potential to the second node N2, that is, the gate of the second transistor T2, through the first transistor T1 and the third transistor T3.
  • the corresponding potential change of the first node N1 due to capacitive coupling is:
  • the potential difference stored in the first capacitor C1 is Vth+ ⁇ VN2- ⁇ VN1.
  • the light-emitting current is independent of the potential value of the first power supply voltage ELVDD, thereby reducing the influence of the voltage drop (IR drop) of the first power supply voltage ELVDD on the brightness, and improving the uneven brightness caused by the voltage drop (IR drop) under large-size panels.
  • the third transistor T3 is turned on and captures the charge from the data signal DATA through the first transistor T1.
  • the sampling and data storage of the threshold voltage Vth of the second transistor T2 are separated, so that the threshold voltage Vth compensation can be carried out simultaneously between adjacent rows, thereby greatly relaxing the number of rows and high refresh rate. Limiting the compensation time enables full compensation at high refresh rates and improves image quality.
  • the light-emitting control signal EM is input at a low level
  • the first scan signal Scan1 is input at a high level
  • the second scan signal Scan2 is input at a high level
  • the third scan signal Scan3 is input at a high level
  • the fourth scan signal Scan4 is input at a high level.
  • the first transistor T1, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are turned off, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned on.
  • the first power supply voltage ELVDD and the second power supply voltage ELVSS act on both ends of the light-emitting diode D to make it emit light.
  • the third transistor T3 is turned off and emits charges into the first capacitor C1, causing the potential of the second node N2 to rise, the brightness of the light-emitting diode D to gradually decrease, and then the brightness of the display panel to decrease.
  • the light emitting control signal EM inputs a low level
  • the first scanning signal Scan1 inputs a high level
  • the second scanning signal Scan2 inputs a high level
  • the third scanning signal Scan3 inputs a low level
  • the fourth scanning signal Scan4 inputs a low level.
  • the first transistor T1 and the sixth transistor T6 are turned off, and the second transistor T2 to the fifth transistor T5 and the seventh transistor T7 are turned on.
  • the first power supply voltage ELVDD and the second power supply voltage ELVSS act on both ends of the light emitting diode D to make it emit light.
  • the third transistor T3 is turned on again, and the charge is captured from the first capacitor C1, and the charge is recovered and bound in the channel defect of the third transistor T3, so that the potential of the second node N2 drops.
  • the light-emitting control signal EM inputs a high level
  • the first scan signal Scan1 inputs a high level
  • the second scan signal Scan2 inputs a high level
  • the third scan signal Scan3 inputs a low level
  • the fourth scan signal Scan4 inputs a low level.
  • the first transistor T1 and the fourth transistor T4 to the sixth transistor T6 are turned off, and the second transistor T2 and the third transistor T3 to the seventh transistor T7 are turned on.
  • the light-emitting control signal EM inputs a high level to turn off the fourth transistor T4 and the fifth transistor T5, and the light-emitting diode D does not emit light.
  • the third transistor T3 remains turned on and continues to capture charges from the first capacitor C1, recovering the charges bound in the channel defects of the third transistor T3, so that the potential of the second node N2 continues to drop.
  • the light emitting control signal EM is input at a high level
  • the first scanning signal Scan1 is input at a high level
  • the second scanning signal Scan2 is input at a high level
  • the third scanning signal Scan3 is input at a low level
  • the fourth scanning signal Scan4 is input at a high level.
  • the first transistor T1 and the fourth transistor T4 to the seventh transistor T7 are turned off, and the second transistor T2 and the first transistor T3 are turned off.
  • the third transistor T3 is turned on.
  • the light-emitting control signal EM is input at a high level to turn off the fourth transistor T4 and the fifth transistor T5, and the light-emitting diode D does not emit light.
  • the third transistor T3 remains turned on and continues to capture charges from the first capacitor C1, recovering the charges bound in the channel defects of the third transistor T3, so that the potential of the second node N2 continues to drop.
  • the light emitting control signal EM inputs a low level
  • the first scanning signal Scan1 inputs a high level
  • the second scanning signal Scan2 inputs a high level
  • the third scanning signal Scan3 inputs a high level
  • the fourth scanning signal Scan4 inputs a high level.
  • the first transistor T1, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are turned off, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned on.
  • the first power supply voltage ELVDD and the second power supply voltage ELVSS act on both ends of the light emitting diode D, causing it to emit light, and the brightness reaches the brightness before the third transistor T3 emits charge.
  • the third transistor T3 is turned off again, and emits charge to the first capacitor C1 again, causing the potential of the second node N2 to rise again.
  • the pixel driving circuit 111 uses the high-frequency third scanning signal Scan3 and the fourth scanning signal Scan4 to control the third transistor T3 and the seventh transistor T7 to realize the emission charge recovery and the high-frequency anode reset.
  • the charging process is divided into three steps: the reset of the driving transistor, the recording of the driving transistor threshold voltage Vth, and the writing of the driving transistor data.
  • the driving transistor is the second transistor T2.
  • This embodiment can achieve the following beneficial effects through the above design: First, the recording of the driving transistor threshold voltage Vth and the writing of the driving transistor threshold voltage data are separated, and the compensation process of the driving transistor threshold voltage Vth can be overlapped in adjacent rows, so it is not limited by the number of rows and the refresh rate, so the compensation effect has a greater advantage in the case of large size and high refresh rate. Second, since the compensation time of the driving transistor can be set to be very long, the first capacitor C1 can be set to be very large. At this time, the errors other than the fluctuation of the driving transistor threshold voltage Vth, such as leakage and capacitance coupling related errors, will be diluted, further improving the compensation effect.
  • the brightness of the light emitting diode D is determined by the voltage difference between the first reference voltage Ref1 and the data signal DATA, and has nothing to do with the first power supply voltage ELVDD. Therefore, the voltage drop on the first power supply voltage ELVDD will not affect the brightness of the light emitting diode D, and the voltage drop (IR drop) will be significantly reduced.
  • the first capacitor C1 will connect the first node The potential difference between N1 and the second node N2 is maintained.
  • the high-frequency signal of the third scanning signal Scan3 can recycle the defective charge slowly emitted after the third transistor T3 is turned off into the channel defect at the t5 and t7 stages.
  • This process can be repeated many times within a frame, and the brightness fluctuation caused by the emitted charge is converted into high frequency, thereby reducing the degree of flicker.
  • the high-frequency reset of the anode of the light-emitting diode D in this embodiment can also reduce the degree of flicker.
  • FIG12 shows a circuit diagram of a second embodiment of a pixel driving circuit of the present invention.
  • FIG13 shows a waveform diagram of the pixel driving circuit shown in FIG12 when it is working.
  • the third transistor T3 of the pixel driving circuit 111 of the second embodiment of the present invention is an N-type MOS tube, that is, a wide bandgap, low leakage material is used to further reduce the release of charge, such as indium gallium zinc oxide (IGZO) or amorphous silicon (a-Si), etc.
  • IGZO indium gallium zinc oxide
  • a-Si amorphous silicon
  • the first rising edge of the third scanning signal Scan3 is the same as the falling edge of the first scanning signal Scan1
  • the first falling edge of the third scanning signal Scan3 is the same as the rising edge of the second scanning signal Scan2.
  • the other circuit components and connection methods of this embodiment are the same as those of the first embodiment, and the waveform diagrams are only different as above.
  • this embodiment can achieve the same working process and beneficial effects as the first embodiment.
  • this embodiment changes the third transistor T3 into a low leakage transistor at an ultra-low refresh rate, such as 1Hz or lower, so that the brightness change caused by leakage can be reduced on the basis of achieving the beneficial effects of the first embodiment, thereby achieving an ultra-low refresh rate.
  • FIG14 shows a circuit diagram of a third embodiment of a pixel driving circuit of the present invention.
  • the pixel driving circuit 111 of the third embodiment of the present invention has a first electrode of the seventh transistor T7 connected to the second reference voltage Ref2, and other circuit components, connection methods, and waveform diagrams of the working process are the same as those of the first embodiment.
  • the second reference voltage Ref2 is constant, and its voltage is lower than the lowest potential of the data signal DATA.
  • the first reference voltage Ref1 can also be slightly adjusted to meet specific display requirements.
  • the potential connected to the seventh transistor T7 is changed from the second power supply voltage ELVSS to an independent second reference voltage Ref2.
  • the independent adjustment capability of the second reference voltage Ref2 can be used to adjust the Vds voltage across the second transistor T2 when charging, so as to finely optimize the short circuit. Time afterimage and compensation effects.
  • an embodiment of the present invention further provides a display device, including the display panel 10 provided in the embodiment of the present invention.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • the implementation of the display device can refer to the embodiment of the display panel 10 above, and the repeated technical solutions and technical effects will not be repeated.
  • the pixel driving circuit 111 and the display panel 10 of the present invention control the third transistor T3 and the seventh transistor T7 through the high-frequency third scanning signal Scan3 and the fourth scanning signal Scan4, and together form the main components of the emission charge recovery structure and the high-frequency anode reset structure, thereby reducing the brightness fluctuation of the display panel caused by defective charge emission and improving the picture quality; at the same time, by storing the gate-source potential difference and connecting the constant potential as a reference point through the first capacitor C1, the influence of the voltage drop of the power supply voltage on the brightness is reduced; in addition, by separating the sampling of the threshold voltage Vth and the data storage, full compensation is achieved at a high refresh rate, thereby improving the picture quality.

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Abstract

提供了一种像素驱动电路以及显示面板，其中像素驱动电路包括：第一晶体管(T1)至第七晶体管(T7)、第一电容(C1)至第二电容(C2)、1条数据信号线、1条发光控制信号线、4条扫描信号线。像素驱动电路以及显示面板，通过高频的第三扫描信号(Scan)、第四扫描信号(Scan)、第三晶体管(T3）以及第七晶体管(T7)共同形成发射电荷回收结构和高频阳极重置结构的主要组成部分，从而降低缺陷电荷发射造成的显示面板的亮度波动，提升画面质量；同时，通过电容存储栅源电位差和连接恒定电位作为参考点的方式，降低电源电压的电压降对亮度的影响；此外通过将阈值电压采样和数据存储分开，实现高刷新率下的充分补偿，提高画质。

Description

像素驱动电路以及显示面板 技术领域
本发明涉及显示面板的电路领域，具体地说，涉及一种像素驱动电路以及显示面板。
背景技术
相比传统技术中的液晶显示面板，OLED(Organic Light Emitting Diode，有机发光二极管)显示面板具有反应速度更快、色纯度和亮度更优、对比度更高、视角更广等特点，因此，逐渐得到了显示技术开发商日益广泛的关注。OLED显示面板包括像素阵列以及控制像素阵列的像素驱动电路，像素阵列中的发光像素在像素驱动电路、扫描驱动电路和发光驱动电路的共同作用下发光。
在OLED显示面板的静态画面场景下，降低刷新率可显著降低功耗。低刷新率下，在像素驱动电路中，由于驱动晶体管(Driving TFT)阈值电压Vth在一帧内的漂移、OLED器件的充电延迟以及开关晶体管(Switch TFT)在由开转关后出现的缺陷电荷发射等原因，造成的显示面板的亮度波动，影响使用体验与画面质量。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本发明的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
有鉴于此，本发明提供一种像素驱动电路以及显示面板，以至少解决上述问题。
本发明的一个方面提供一种像素驱动电路，包括：
第一晶体管，所述第一晶体管的第一极连接于数据信号，第二极连接于第三节点，栅极连接于第二扫描信号；
第二晶体管，所述第二晶体管的第一极连接于第一节点，第二极连接于第四节点，栅极连接于第二节点；
第三晶体管，所述第三晶体管的第一极连接于所述第三节点，第二极连接于所述第二节点，栅极连接于第三扫描信号；
第四晶体管，所述第四晶体管的第一极连接于第一电源电压，第二极连接于所述第一节点，栅极连接于发光控制信号；
第五晶体管，所述第五晶体管的第一极连接于所述第四节点，第二极连接于发光二极管的第一极，栅极连接于所述发光控制信号；
第六晶体管，所述第六晶体管的第一极连接于所述第三节点，第二极连接于第一参考电压，栅极连接于第一扫描信号；
第七晶体管，所述第七晶体管的第二极连接于所述第四节点，栅极连接于第四扫描信号；
第一电容，所述第一电容的第一极连接于所述第二节点，第二极连接于所述第一节点；
第二电容，所述第二电容的第一极连接于所述第一节点，第二极连接于所述发光控制信号。
在一些实施例中，所述发光二极管的第二极连接于第二电源电压。
在一些实施例中，所述第七晶体管的第一极连接于第二电源电压。
在一些实施例中，所述第七晶体管的第一极连接于第二参考电压。
在一些实施例中，所述第一晶体管至所述第七晶体管均为P型MOS管。
在一些实施例中，所述第一晶体管至所述第二晶体管、所述第四晶体管至所述第七晶体管均为P型MOS管，所述第三晶体管为N型MOS管。
在一些实施例中，在一帧画面时间内，所述发光控制信号、所述第三扫描信号和所述第四扫描信号的频率相同，所述第一扫描信号和所述第二扫描信号的频率相同，所述发光控制信号的频率至少为所述第一扫描信号的两倍。
在一些实施例中，在一帧画面时间内，所述第三扫描信号的第一个下降沿与所述第一扫描信号的下降沿时刻相同，所述第三扫描信号的第一个上升沿与所述第二扫描信号的上升沿时刻相同。
在一些实施例中，在一帧画面时间内，所述第三扫描信号的第一个上升沿与所述第一扫描信号的下降沿时刻相同，所述第三扫描信号的第一个下降沿与所述第二扫描信号的上升沿时刻相同。
在一些实施例中，在一帧画面时间内，所述第四扫描信号的第一个下降沿和第一个上升沿，与所述第一扫描信号的下降沿和上升沿时刻相同。
本发明的另一个方面还提供一种显示面板，包括上述任一项所述的像素驱动电路。
本发明与现有技术相比的有益效果至少包括：
本发明的像素驱动电路以及显示面板，通过高频的第三扫描信号、第四扫描信号、第三晶体管以及第七晶体管共同形成发射电荷回收结构和高频阳极重置结构的主要组成部分，从而降低缺陷电荷发射造成的显示面板的亮度波动，提升画面质量；同时，通过电容存储栅源电位差和连接恒定电位作为参考点的方式，降低电源电压的电压降对亮度的影响；此外通过将阈值电压采样和数据存储分开，实现高刷新率下的充分补偿，提高画质。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本发明。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本发明的实施例，并与说明书一起用于解释本发明的原理。显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出本发明的一种显示面板的电路结构示意图；
图2示出本发明像素驱动电路的第一实施例的电路图；
图3示出图2所示的像素驱动电路工作时的波形图；
图4示出图3中t1阶段像素驱动电路的工作状态示意图；
图5示出图3中t2阶段像素驱动电路的工作状态示意图；
图6示出图3中t3阶段像素驱动电路的工作状态示意图；
图7示出图3中t4阶段像素驱动电路的工作状态示意图；
图8示出图3中t5阶段像素驱动电路的工作状态示意图；
图9示出图3中t6阶段像素驱动电路的工作状态示意图；
图10示出图3中t7阶段像素驱动电路的工作状态示意图；
图11示出图3中t8阶段像素驱动电路的工作状态示意图；
图12示出本发明像素驱动电路的第二实施例的电路图；
图13示出图12所示的像素驱动电路工作时的波形图；
图14示出本发明像素驱动电路的第三实施例的电路图。
附图标记：
10       显示面板
11       显示区
111      像素驱动电路
121      数据驱动器
DATA     数据信号
ELVDD    第一电源电压
ELVSS    第二电源电压
EM       发光控制信号
Scan1    第一扫描信号
Scan2    第二扫描信号
Scan3    第三扫描信号
Scan4    第四扫描信号
Ref1     第一参考电压
Ref2     第二参考电压
T1       第一晶体管
T2       第二晶体管
T3       第三晶体管
T4       第四晶体管
T5       第五晶体管
T6       第六晶体管
T7       第七晶体管
C1       第一电容
C2       第二电容
N1       第一节点
N2       第二节点
N3       第三节点
N4       第四节点
D        发光二极管
具体实施方式
为使本发明解决的技术问题、采用的技术方案和达到的技术效果更加清楚，下面将结合附图对本发明实施例的技术方案作进一步的详细描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
此外，所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有特定细节中的一个或更多，或者可以采用其它的方法、模块、装置、步骤等。在其它情况下，不详细示出或描述公知模块、方法、装置、实现、步骤、或者操作以避免模糊本公开的各方面。
本案发明人通过细致深入研究，对于现有技术中所存在的问题，提供了一种解决方案。图1示出本发明的一种显示面板的电路结构示意图。图2示出本发明像素驱动电路的第一实施例的电路图。图12示出本发明像素驱动电路的第二实施例的电路图。图14示出本发明像素驱动电路的第三实施例的电路图。如图1、2、12和14所示，本发明公开一些像素驱动电路111以及显示面板10，其中像素驱动电路111至少包括：第一晶体管至第七晶体管、第一电容至第二电容、1条数据信号线、1条发光控制信号线、4条扫描信号线。本发明的像素驱动电路111以及显示面板10，通过高频的第三扫描信号Scan3和第四扫描信号Scan4控制第三晶体管T3和第七晶体管T7，共同形成发射电荷回收结构和高频阳极重置结构的主要组成部分，从而降低缺陷电荷发射造成的显示面板的亮度波动，提升画面 质量；同时，通过第一电容C1存储栅源电位差和连接恒定电位作为参考点的方式，降低电源电压的电压降对亮度的影响；此外通过将阈值电压Vth采样和数据存储分开，实现高刷新率下的充分补偿，提高画质。
下面结合附图并通过具体实施方式来进一步说明本发明的技术方案。
如图1所示，本发明的一个方面提供一种显示面板10，该显示面板10包括显示区11和非显示区。其中，扫描驱动电路、发光驱动电路和数据驱动器121位于显示面板10的非显示区。多条数据信号线与数据驱动器121相连，数据驱动器121通过多条数据信号线为发光像素提供数据信号DATA。显示区11包括阵列排列的发光像素，每一发光像素均具有控制其发光的像素驱动电路111。发光像素至少在扫描驱动电路、发光驱动电路、像素驱动电路111和数据驱动器121的共同作用下发光。
基于同一发明构思，本发明的另一个方面提供一些像素驱动电路111。如图2所示，本发明第一实施例的像素驱动电路111包括：第一晶体管T1至第七晶体管T7，以及第一电容C1至第二电容C2。其中，第一晶体管T1的第一极连接于数据信号DATA，第二极连接于第三节点N3，栅极连接于第二扫描信号Scan2。第二晶体管T2的第一极连接于第一节点N1，第二极连接于第四节点N4，栅极连接于第二节点N2。第三晶体管T3的第一极连接于第三节点N3，第二极连接于第二节点N2，栅极连接于第三扫描信号Scan3。第四晶体管T4的第一极连接于第一电源电压ELVDD，第二极连接于第一节点N1，栅极连接于发光控制信号EM。第五晶体管T5的第一极连接于第四节点N4，第二极连接于发光二极管D的第一极，栅极连接于发光控制信号EM。第六晶体管T6的第一极连接于第三节点N3，第二极连接于第一参考电压Ref1，栅极连接于第一扫描信号Scan1。第七晶体管T7的第二极连接于第四节点N4，栅极连接于第四扫描信号Scan4。第一电容C1的第一极连接于第二节点N2，第二极连接于第一节点N1。第二电容C2的第一极连接于第一节点N1，第二极连接于发光控制信号EM。
在本实施例中，在上述连接关系的基础上，还具有：第七晶体管T7的第一极连接于第二电源电压ELVSS。发光二极管D的第二极连接于第二电源电压ELVSS。其中，发光二极管D可以为OLED或者AMOLED (Active-matrix organic light emitting diode，有源矩阵有机发光二极体或主动矩阵有机发光二极体)，发光二极管D的第一极为阳极，第二极为阴极。第一电源电压ELVDD为正电源电压，第二电源电压ELVSS为负电源电压，但并不以此为限。
在本实施例中，第一晶体管T1至第七晶体管T7均为P型MOS管。P型MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)简称P型MOS管或者PMOS管。其中，PMOS管的控制端为栅极，其第一极为源极，第二极为漏极，或者其第一极为漏极，第二极为源极。PMOS管的导通电平为低电平，其关闭电平为高电平。在另一些实施例中，本领域所属技术人员很容易得出本发明所提供的像素驱动电路111可以轻易改成全为N型MOS管或者混合型CMOS管。需要说明的是，下文中晶体管的导通和关断时的高低电平均是以PMOS管为例的，当根据设计需要选择其它相应的晶体管类型时，其导通和关断的高低电平也会相应的变化。
在本实施例中，第一参考电压Ref1恒定，且其电压低于数据信号DATA的最低电位。在其它实施例中，第一参考电压Ref1也可以进行微小调整以满足特定的显示需求。
图3示出图2所示的像素驱动电路工作时的波形图。图4示出图3中t1阶段像素驱动电路的工作状态示意图。图5示出图3中t2阶段像素驱动电路的工作状态示意图。图6示出图3中t3阶段像素驱动电路的工作状态示意图。图7示出图3中t4阶段像素驱动电路的工作状态示意图。图8示出图3中t5阶段像素驱动电路的工作状态示意图。图9示出图3中t6阶段像素驱动电路的工作状态示意图。图10示出图3中t7阶段像素驱动电路的工作状态示意图。图11示出图3中t8阶段像素驱动电路的工作状态示意图。
本实施例中的像素驱动电路111可以工作在低频下，其中低频是指操作频率小于60Hz，但最低操作频率为1Hz，但并不以此为限。具体地，图3可以为本发明的像素驱动电路111在操作频率为60Hz、每一帧内插黑和发光2次情况下的时序图。当然，本发明的像素驱动电路111在每一帧内也可以插黑和发光多次，只需要在t1至t4阶段之后重复t5至t8阶段 即可。以下仅以2次为例，进行说明：
如图3所示，在本实施例中，在一帧画面时间内，发光控制信号EM、第三扫描信号Scan3和第四扫描信号Scan4均包含两个下降沿和两个上升沿。第一扫描信号Scan1和第二扫描信号Scan2均仅包含一个下降沿和一个上升沿。也即，在一帧画面时间内，发光控制信号EM、第三扫描信号Scan3和第四扫描信号Scan4的频率相同，第一扫描信号Scan1和第二扫描信号Scan2的频率相同，发光控制信号EM的频率为第一扫描信号Scan1的两倍。具体地，第三扫描信号Scan3的第一个下降沿与第一扫描信号Scan1的下降沿时刻相同，第三扫描信号Scan3的第一个上升沿与第二扫描信号Scan2的上升沿时刻相同。第四扫描信号Scan4的第一个下降沿和第一个上升沿，与第一扫描信号Scan1的下降沿和上升沿时刻相同。
如图3所示，在本实施例中，在显示画面的一帧时间内，像素驱动电路111的工作过程被划分为8个阶段，分别为t1至t8。在这8个过程中，上述的像素驱动电路111中的发光二极管D完成两次从插黑到发光的过程。需要说明的是，为方便理解，图4至图11中“×”表示晶体管截止。下面结合图3的波形图和图2的电路图对上述8个过程中像素驱动电路111的输入和发光的关系进行分析：
如图3和4所示，在t1阶段，发光控制信号EM输入低电平，第一扫描信号Scan1输入低电平，第二扫描信号Scan2输入高电平，第三扫描信号Scan3输入低电平，第四扫描信号Scan4输入低电平。第一晶体管T1被关闭，第二晶体管T2至第七晶体管T7被打开。在本阶段中，由于第七晶体管T7晶体管被打开，将发光二极管D短路掉，此时不发光，本阶段为重置阶段。第一参考电压Ref1透过第六晶体管T6和第三晶体管T3向第二节点N2写入低电位，也即第二晶体管T2的栅极，以重置第二晶体管T2。同时，第三晶体管T3被打开，并透过第六晶体管T6捕获来自第一参考电压Ref1的电荷。
如图3和5所示，在t2阶段，发光控制信号EM输入高电平，第一扫描信号Scan1输入低电平，第二扫描信号Scan2输入高电平，第三扫描信号Scan3输入低电平，第四扫描信号Scan4输入低电平。第一晶体管 T1、第四晶体管T4和第五晶体管T5被关闭，第二晶体管T2、第三晶体管T3、第六晶体管T6和第七晶体管T7被打开。在本阶段中，发光控制信号EM输入高电平关闭第四晶体管T4和第五晶体管T5，发光二极管D不发光。第一参考电压Ref1透过第六晶体管T6和第三晶体管T3继续向第二节点N2写入低电位，也即第二晶体管T2的栅极，以记录第二晶体管T2的阈值电压Vth。发光控制信号EM的电位由低变高的瞬间，通过第二电容C2的耦合将第一节点N1的电位上抬。之后由于栅极电位为第一参考电压Ref1，第二晶体管T2为打开状态，第二晶体管T2将第一节点N1和第四节点N4相连接。因此第一节点N1的电位会下降至VRef1-Vth，此时第一电容C1存储的电位差为Vth。同时，第三晶体管T3被打开，并继续透过第六晶体管T6捕获来自第一参考电压Ref1的电荷。
如图3和6所示，在t3阶段，发光控制信号EM输入高电平，第一扫描信号Scan1输入高电平，第二扫描信号Scan2输入低电平，第三扫描信号Scan3输入低电平，第四扫描信号Scan4输入高电平。第四晶体管T4至第七晶体管T7被关闭，第一晶体管T1至第三晶体管T3被打开。在本阶段中，发光控制信号EM输入高电平关闭第四晶体管T4和第五晶体管T5，发光二极管D不发光。数据信号DATA透过第一晶体管T1和第三晶体管T3向第二节点N2写入数据电位，也即第二晶体管T2的栅极。第二节点N2的电位变化量为ΔVN2＝VDATA-VRef1，相应的第一节点N1由于电容耦合，电位变化量为：
此时第一电容C1中存储的电位差为Vth+ΔVN2-ΔVN1。通过第一电容C1存储栅源电位差而非栅极电位的方式，同时加上第一参考电压Ref1作为参考点，使发光电流与第一电源电压ELVDD的电位值无关，从而降低第一电源电压ELVDD的电压降(IR drop)对亮度的影响，对在大尺寸面板下电压降(IR drop)引起的亮度不均有改善作用。同时，第三晶体管T3被打开，并透过第一晶体管T1捕获来自数据信号DATA的电荷。在t2至t3阶段，将第二晶体管T2的阈值电压Vth的采样和数据存储分开，可使阈值电压Vth补偿在相近行间同时进行，从而大大放宽行数和高刷新率 对补偿时间的限制，实现高刷新率下的充分补偿，提高画质。
如图3和7所示，在t4阶段，发光控制信号EM输入低电平，第一扫描信号Scan1输入高电平，第二扫描信号Scan2输入高电平，第三扫描信号Scan3输入高电平，第四扫描信号Scan4输入高电平。第一晶体管T1、第三晶体管T3、第六晶体管T6和第七晶体管T7被关闭，第二晶体管T2、第四晶体管T4和第五晶体管T5被打开。在本阶段中，第一电源电压ELVDD和第二电源电压ELVSS作用在发光二极管D的两端，使其发光。同时，第三晶体管T3被关闭，并向第一电容C1中发射电荷，导致第二节点N2的电位上升，发光二极管D的亮度逐渐下降，进而显示面板的亮度下降。
如图3和8所示，在t5阶段，发光控制信号EM输入低电平，第一扫描信号Scan1输入高电平，第二扫描信号Scan2输入高电平，第三扫描信号Scan3输入低电平，第四扫描信号Scan4输入低电平。第一晶体管T1和第六晶体管T6被关闭，第二晶体管T2至第五晶体管T5以及第七晶体管T7被打开。在本阶段中，第一电源电压ELVDD和第二电源电压ELVSS作用在发光二极管D的两端，使其发光。同时，第三晶体管T3再次打开，并从第一电容C1中捕获电荷，回收束缚在第三晶体管T3的沟道缺陷中，使第二节点N2的电位下降。
如图3和9所示，在t6阶段，发光控制信号EM输入高电平，第一扫描信号Scan1输入高电平，第二扫描信号Scan2输入高电平，第三扫描信号Scan3输入低电平，第四扫描信号Scan4输入低电平。第一晶体管T1以及第四晶体管T4至第六晶体管T6被关闭，第二晶体管T2、第三晶体管T3至第七晶体管T7被打开。在本阶段中，发光控制信号EM输入高电平关闭第四晶体管T4和第五晶体管T5，发光二极管D不发光。同时，第三晶体管T3保持打开，并继续从第一电容C1中捕获电荷，回收束缚在第三晶体管T3的沟道缺陷中，使第二节点N2的电位继续下降。
如图3和10所示，在t7阶段，发光控制信号EM输入高电平，第一扫描信号Scan1输入高电平，第二扫描信号Scan2输入高电平，第三扫描信号Scan3输入低电平，第四扫描信号Scan4输入高电平。第一晶体管T1以及第四晶体管T4至第七晶体管T7被关闭，第二晶体管T2和第 三晶体管T3被打开。在本阶段中，发光控制信号EM输入高电平关闭第四晶体管T4和第五晶体管T5，发光二极管D不发光。同时，第三晶体管T3保持打开，并继续从第一电容C1中捕获电荷，回收束缚在第三晶体管T3的沟道缺陷中，使第二节点N2的电位继续下降。
如图3和11所示，在t8阶段，发光控制信号EM输入低电平，第一扫描信号Scan1输入高电平，第二扫描信号Scan2输入高电平，第三扫描信号Scan3输入高电平，第四扫描信号Scan4输入高电平。第一晶体管T1、第三晶体管T3、第六晶体管T6和第七晶体管T7被关闭，第二晶体管T2、第四晶体管T4和第五晶体管T5被打开。在本阶段中，第一电源电压ELVDD和第二电源电压ELVSS作用在发光二极管D的两端，使其发光，并且亮度达到第三晶体管T3发射电荷前的亮度。同时，第三晶体管T3再次被关闭，并向再次第一电容C1中发射电荷，导致第二节点N2的电位再次上升。
在本实施例中，像素驱动电路111使用高频的第三扫描信号Scan3和第四扫描信号Scan4控制第三晶体管T3和第七晶体管T7，实现发射电荷回收和高频阳极重置，其充电过程分为驱动晶体管重置、驱动晶体管阈值电压Vth记录以及驱动晶体管数据写入三步，通过合理设定第一电容C1、第二电容C2以及驱动晶体管阈值电压Vth的记录时间，可以实现对驱动晶体管阈值电压Vth的充分补偿。其中，驱动晶体管即第二晶体管T2。本实施例通过上述设计可以实现如下有益效果：第一，驱动晶体管阈值电压Vth的记录和驱动晶体管阈值电压的数据写入被分开，驱动晶体管阈值电压Vth的补偿过程可以在相邻行中交叠进行，因此不受行数和刷新率的限制，因此在大尺寸高刷新率情况下补偿效果有较大优势。第二，由于驱动晶体管的补偿时间可设置为很长，因此第一电容C1可设置为很大，此时驱动晶体管阈值电压Vth波动以外的误差，如漏电、电容耦合相关的误差将被稀释，进一步提高补偿效果。第三，本实施例的像素驱动电路111的发光亮度由第一参考电压Ref1与数据信号DATA的电压差决定，而与第一电源电压ELVDD无关，因此第一电源电压ELVDD上的压降不会影响发光二极管D的亮度，电压降(IR drop)将被显著降低。第四，一帧之内，本实施例的像素驱动电路111在充电完成后，第一电容C1就将第一节点 N1和第二节点N2的电位差保持住，后续无论何种因素(比如插黑)使得第一节点N1有所变化，第二节点N2的电位都将随第一节点N1同向变化，从而不再有帧内第二晶体管T2Vgs的长时间波动，所以第二晶体管T2阈值电压Vth在帧内不再发生明显波动导致亮度变化，消除了第二晶体管T2阈值电压Vth波动带来的画面闪烁。第五，第三扫描信号Scan3的高频信号可将第三晶体管T3关断后缓慢发射的缺陷电荷在t5和t7阶段重新回收至沟道缺陷中，此过程在一帧内可反复进行多次，将发射电荷带来的亮度波动变为高频从而降低闪烁程度。第六，本实施例对发光二极管D阳极的高频重置也可降低闪烁程度。
图12示出本发明像素驱动电路的第二实施例的电路图。图13示出图12所示的像素驱动电路工作时的波形图。如图12和13所示，本发明第二实施例的像素驱动电路111与第一实施例相比，其第三晶体管T3为N型MOS管，即采用宽禁带、低漏电材料以进一步降低电荷的释放，如铟镓锌氧化物(IGZO)或者非晶硅(a-Si)等等。同时，在一帧画面时间内，第三扫描信号Scan3的第一个上升沿与第一扫描信号Scan1的下降沿时刻相同，第三扫描信号Scan3的第一个下降沿与第二扫描信号Scan2的上升沿时刻相同。本实施例的其它电路组件以及连接方式均与第一实施例相同，波形图仅具有如上区别。由此，本实施例即可实现与第一实施例相同的工作过程以及有益效果。此外，本实施例在超低刷新率下，如1Hz或更低，将第三晶体管T3变为低漏电晶体管，可以在实现第一实施例有益效果的基础上，同时减少由于漏电带来的亮度变化从而实现超低刷新率。
图14示出本发明像素驱动电路的第三实施例的电路图。如图14所示，本发明第三实施例的像素驱动电路111与第一实施例相比，其第七晶体管T7的第一极连接于第二参考电压Ref2，其它电路组件、连接方式以及工作过程的波形图均与第一实施例相同。在本实施例中，第二参考电压Ref2恒定，且其电压低于数据信号DATA的最低电位。在其它实施例中，第一参考电压Ref1也可以进行微小调整以满足特定的显示需求。第七晶体管T7所连电位从第二电源电压ELVSS变为一个独立的第二参考电压Ref2，可以在实现第一实施例有益效果的基础上，同时利用第二参考电压Ref2的独立调节能力调整第二晶体管T2充电时的Vds跨压，用于精细优化短 时残影和补偿效果。
基于同一发明构思，本发明的实施例还提供了一种显示装置，包括本发明实施例提供的上述显示面板10。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置的实施可以参见上述显示面板10的实施例，技术方案以及技术效果重复之处不再赘述。
综上，本发明的像素驱动电路111以及显示面板10，通过高频的第三扫描信号Scan3和第四扫描信号Scan4控制第三晶体管T3和第七晶体管T7，共同形成发射电荷回收结构和高频阳极重置结构的主要组成部分，从而降低缺陷电荷发射造成的显示面板的亮度波动，提升画面质量；同时，通过第一电容C1存储栅源电位差和连接恒定电位作为参考点的方式，降低电源电压的电压降对亮度的影响；此外通过将阈值电压Vth采样和数据存储分开，实现高刷新率下的充分补偿，提高画质。
以上内容是结合具体的可选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (11)

  1. 一种像素驱动电路，其特征在于，包括：
    第一晶体管，所述第一晶体管的第一极连接于数据信号，第二极连接于第三节点，栅极连接于第二扫描信号；
    第二晶体管，所述第二晶体管的第一极连接于第一节点，第二极连接于第四节点，栅极连接于第二节点；
    第三晶体管，所述第三晶体管的第一极连接于所述第三节点，第二极连接于所述第二节点，栅极连接于第三扫描信号；
    第四晶体管，所述第四晶体管的第一极连接于第一电源电压，第二极连接于所述第一节点，栅极连接于发光控制信号；
    第五晶体管，所述第五晶体管的第一极连接于所述第四节点，第二极连接于发光二极管的第一极，栅极连接于所述发光控制信号；
    第六晶体管，所述第六晶体管的第一极连接于所述第三节点，第二极连接于第一参考电压，栅极连接于第一扫描信号；
    第七晶体管，所述第七晶体管的第二极连接于所述第四节点，栅极连接于第四扫描信号；
    第一电容，所述第一电容的第一极连接于所述第二节点，第二极连接于所述第一节点；
    第二电容，所述第二电容的第一极连接于所述第一节点，第二极连接于所述发光控制信号。
  2. 根据权利要求1所述的像素驱动电路，其特征在于，所述发光二极管的第二极连接于第二电源电压。
  3. 根据权利要求1所述的像素驱动电路，其特征在于，所述第七晶体管的第一极连接于第二电源电压。
  4. 根据权利要求1所述的像素驱动电路，其特征在于，所述第七晶体管的第一极连接于第二参考电压。
  5. 根据权利要求3或4所述的像素驱动电路，其特征在于，所述第一晶体管至所述第七晶体管均为P型MOS管。
  6. 根据权利要求3所述的像素驱动电路，其特征在于，所述第一晶 体管至所述第二晶体管、所述第四晶体管至所述第七晶体管均为P型MOS管，所述第三晶体管为N型MOS管。
  7. 根据权利要求1所述的像素驱动电路，其特征在于，在一帧画面时间内，所述发光控制信号、所述第三扫描信号和所述第四扫描信号的频率相同，所述第一扫描信号和所述第二扫描信号的频率相同，所述发光控制信号的频率至少为所述第一扫描信号的两倍。
  8. 根据权利要求5所述的像素驱动电路，其特征在于，在一帧画面时间内，所述第三扫描信号的第一个下降沿与所述第一扫描信号的下降沿时刻相同，所述第三扫描信号的第一个上升沿与所述第二扫描信号的上升沿时刻相同。
  9. 根据权利要求6所述的像素驱动电路，其特征在于，在一帧画面时间内，所述第三扫描信号的第一个上升沿与所述第一扫描信号的下降沿时刻相同，所述第三扫描信号的第一个下降沿与所述第二扫描信号的上升沿时刻相同。
  10. 根据权利要求1所述的像素驱动电路，其特征在于，在一帧画面时间内，所述第四扫描信号的第一个下降沿和第一个上升沿，与所述第一扫描信号的下降沿和上升沿时刻相同。
  11. 一种显示面板，其特征在于，包括根据权利要求1至10任一项所述的像素驱动电路。
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