RU238705U1 - On-board indicator calculator - Google Patents

Abstract

The utility model relates to on-board indicator computers. The technical result consists in increasing the reliability and fault tolerance of the on-board indicator computer. The on-board indicator computer includes: a physical LVDS port connected to two programmable logic integrated circuits (FPGAs), the first FPGA (main) intended for high-speed data processing to generate an indication in accordance with specified parameters, the second FPGA (backup, control) for redundancy and continuous data reliability monitoring, a processor connected to both FPGAs, ensuring the processing of data received from the on-board network and a database, to generate control commands in the FPGA, a database intended for storing information necessary for the correct generation of an indication, and a physical port (on-board network) ensuring the transfer of data to the on-board network. 1 Fig.

Description

The utility model relates to the field of computing and aviation equipment and is intended for use in civil aircraft to provide the crew with the necessary flight navigation and flight information through its display on a multifunctional indicator, which ensures more convenient and rapid perception of data, and simultaneously reduces the operational workload on pilots.

The onboard multifunctional display is designed to improve the safety and efficiency of civil aircraft operations by promptly providing the crew with accurate, complete, and visual information about the current aircraft status, its systems, and flight parameters. Contextual data display allows for flexible adaptation of information to the current flight situation. The multifunctional display also allows the crew to effectively interact with other onboard systems and optimize piloting and navigation procedures, which in turn helps reduce pilot workload. This significantly improves overall flight safety and reliability, while also enhancing crew situational awareness.

A key challenge in the development and operation of modern onboard multifunctional displays is the high complexity of their setup and configuration. This is due to the use of complex hardware and software solutions, including foreign-manufactured components, the need to integrate multiple information streams, and high-density data display to guarantee the error-free and timely presentation of critical information that directly impacts flight safety. As a result, the process of developing and implementing displays becomes lengthy, expensive, and labor-intensive, creating significant barriers to their effective use on aircraft.

In addition, standard on-board display computers do not provide sufficient performance and responsiveness, which causes delays, distortion, or loss of relevance of displayed data, increasing the workload of the crew and increasing the risk of errors in decision-making.

To solve this problem, it is necessary to develop a computer for an onboard multifunctional display based on a hardware architecture that includes a processor and two programmable logic integrated circuits (FPGAs), the first of which will be designed for high-speed processing and output of critical flight information, and the second for continuous monitoring and verification of the reliability of the displayed data, the processor for generating commands for both FPGAs based on the results of preliminary processing of data coming from the onboard network.

The following technical solutions are known from the current state of the art.

A computing device (patent RU 168565) with a reconfigurable architecture is known, using programmable logic integrated circuits (FPGA) for use in reconfigurable computing units of multiprocessor computing systems intended for solving labor-intensive problems and processing large data arrays and flows, using parallelization and pipelining of computing processes. The device comprises an external port for data exchange, a PCI-Express switch, an interface FPGA, a group of N computing FPGAs, high-speed PCI-Express interfaces, a unit for operational configuration of the interface FPGA, a power control and management unit, a monitoring unit, an external JTAG control and management port, configuration memory of the interface FPGA, a bidirectional common bus, a group of N computing ASICs, a group of N starting configurations of the computing FPGAs, a unit for operational reconfiguration of the memories of the starting configurations of the computing FPGAs, and a synchronization unit.

This technical solution is aimed at increasing productivity and reducing energy consumption in large data processing tasks, but does not provide integration with the aircraft's onboard digital network.

A utility model (patent RU 185051) is known, which pertains to the field of industrial real-time communication systems, specifically to a slave device of the Ethernet POWERLINK network based on a programmable logic integrated circuit (FPGA), including an interface module to a physical layer chip, the input/output of which is connected to a common data channel, to which are connected a cyclic data exchange module and an asynchronous data exchange module, which is connected to a base dictionary module, which is connected to object dictionary memory, which is also connected to the cyclic data exchange module. This utility model reduces the requirements for the logical capacity of the FPGA used and allows the device to be implemented without additional memory chips.

The disadvantage of this technical solution is the lack of hardware redundancy mechanisms and mutual control between several FPGAs, which significantly reduces fault tolerance and makes this architecture less suitable for aviation systems.

An autonomous computing module is known (patent RU 2720556), which contains an interface FPGA, a group of N computing FPGAs, an external high-speed serial port, K groups of N computing ASICs, an external FPGA monitoring and control port, a processor core, interface FPGA configuration memory, a unit for operational reconfiguration of memories of starting configurations of computing FPGAs, a group of N memories of starting configurations of computing FPGAs, a group of N units for individual monitoring and power management of computing ASICs, a group of N units for individual adjustment of operating frequencies of computing ASICs, a group of N Flash memories of computing ASICs, RAM of the processor core, an external console control port, a module status indication unit and an external ASIC monitoring and control port for increasing the performance of the computing module, as well as expanding the scope of application and classes of effectively solved computationally complex problems.

A significant drawback of this technical solution is the lack of specialized ports required for direct video signal transmission to the display matrix and interaction with the aircraft's secure onboard network. Furthermore, the solution is primarily designed for autonomous operation and high-performance data processing, but lacks the ability to integrate with the aircraft's onboard network, complicating its use in civil aviation.

A flight visualization system and cognitive flight indicator for a single-rotor helicopter (patent RU 2497175) are known. They comprise a computer unit for determining spatial attitude and motion dynamics parameters, which includes modules for algorithmic correction of instrumental errors of primary information sensors (PIS), digital filters for compensating for vibration accelerations of the helicopter's coupled axes, and an inertial-satellite filter, all implemented using software and algorithms. These systems are designed to improve the accuracy and reliability of determining ground speed, wind parameters, and helicopter attitude parameters—roll and pitch angles—required by the crew for safe landing in conditions where the ground surface is not clearly visible. The computer of the block for determining the parameters of spatial position and motion dynamics additionally contains a topographic database of the underlying surface, for example, digital cartographic information with the worldwide aeronautical database of the Garmin company - Garmin Flight Charts - superimposed on it, or a high-precision improved database of digital terrain - Earth landscape EGPWS from Honeywell.

This solution does not provide for mechanisms for generating initial data and monitoring its integrity, which prevents the possibility of formal confirmation of compliance with the safety and reliability requirements imposed on aviation equipment.

A computing unit (patent RU 2707701) is known, comprising a housing with a backplane. The backplane contains at least one computing module, an interface module, a switching module, and a power supply module, all connected via a service bus. The unit is designed to create a computer for onboard aviation equipment while increasing its reliability and simplifying its use. Furthermore, the computing unit is configured to utilize a high-speed serial interface for receiving and transmitting primary data from external sensors, and to exchange this information with other modules for transmitting video data via the ARJNC818 interface between the interface modules and the switching modules.

A drawback of this technical solution is the lack of specialized hardware redundancy mechanisms and mutual control of computing video streams. Furthermore, the described solution does not address in detail the mechanisms for generating video data, which complicates the system's use in multifunctional displays (MFIs), which require the rapid generation of graphic elements and streaming visual data in accordance with the requirements of onboard display systems.

The technical solution known from source RU 2707701 is, in its technical essence, the closest to the proposed utility model and can serve as a prototype.

The problem addressed by the claimed utility model is the development of a computer for an on-board display of an aircraft, in which the functions of high-speed processing and generation of indication with minimal delays are implemented in the first programmable logic integrated circuit (FPGA), and the functions of redundancy and continuous control of the reliability of the displayed information are implemented in the second FPGA by constantly comparing the results of the operation of both FPGAs, which significantly increases the reliability and fault tolerance of the computer, and the preliminary processing of information from the on-board network and the formation of control commands for both FPGAs are implemented in the processor, which significantly increases the autonomy of the computer.

The technical result of the proposed utility model consists of increasing the level of reliability and fault tolerance of the computer for the on-board indicator by increasing the speed of information processing and its reliability when displayed, as well as simplifying the configuration of the computer.

The claimed technical result is achieved by implementing a computer for an on-board indicator, which contains a physical port (on-board network) for transmitting information to the on-board network, a processor intended for preliminary processing of data coming from the on-board network and a database, as well as the formation of control commands for programmable logic integrated circuits (FPGAs), a database that ensures the storage of information necessary for the correct formation of an indication, two programmable logic integrated circuits (FPGAs), wherein the first FPGA (main) is configured with the possibility of high-speed data processing and the formation of an indication with minimal time delays and high visualization efficiency, the second FPGA (backup, monitoring), configured with the possibility of redundancy and continuous monitoring of the reliability of data by comparing the output data with the first FPGA to improve the reliability of the computer, a physical LVDS port for transmitting data from the FPGA to the on-board indicator.

At the same time, the first programmable logic integrated circuit (FPGA) (the main one) is responsible for generating the indication according to the main visualization algorithm, using optimized methods of processing and rendering graphic information, which ensures minimal delays and high accuracy of data display.

The second programmable logic integrated circuit (FPGA) (backup, control) performs parallel data processing using an alternative visualization algorithm, including a different synchronization and display layout technique from the main one.

It's important that the first and second FPGAs be based on different architectures and utilize different algorithms for generating images and video data. This approach ensures independent data processing and subsequent comparison of results, significantly increasing the reliability of the onboard display's computer.

This architecture will enable the efficient processing, integration, and display of large volumes of data received from various aircraft systems, including navigation, flight control, engine control, and external sensors, while minimizing time delays in high-speed flight conditions and dynamically changing operational environments, significantly improving flight safety and reliability.

Fig. 1 shows the structural diagram of the proposed computer for an on-board multifunctional indicator, where 1 is the physical LVDS port providing data transmission; 2 is the FPGA (main); 3 is the FPGA (backup, control); 4 is the processor; 5 is the database; 6 is the physical port (on-board network) for transmitting data to the on-board network.

The computer for the on-board indicator is made in the form of a single device, which contains elements in its composition that are assembly units connected to each other by assembly operations, and has a functional and structural unity, therefore it can be declared as a utility model.

The on-board equipment computer (Fig. 1) includes: a physical LVDS port (1) connected to two programmable logic integrated circuits (FPGAs), the first FPGA (main) (2) intended for high-speed data processing for generating an indication in accordance with specified parameters, the second FPGA (backup, monitoring) (3) - for generating an indication, backup and continuous monitoring of the reliability of data by comparing with the data of the first FPGA (main) (2), a processor (4) connected to both FPGAs, providing preliminary processing of data coming from the on-board network and the database (5), and generating control commands in the FPGA, the database (5), intended for storing information necessary for the correct generation of an indication and a physical port (on-board network) (6), providing data transmission to the on-board network and interconnection with the computers participating in flight support.

In a preferred embodiment of the utility model, a Xilinx AMD Kintex 7 family microcircuit can be used as the FPGA (main) (2), and an Intel Cyclone 10 can be used as the FPGA (backup, control) (3), which will allow for independent data processing and increase the fault tolerance of the utility model.

The processor (4) can be implemented on the basis of a PowerPC chip, which will allow compliance with strict safety and reliability requirements, as well as compatibility with certification standards for aviation electronics, since it is widely used in on-board control systems.

The proposed computer for the on-board indicator (Fig. 1) functions as follows.

Via the physical port (onboard network) (6), the processor (4) receives flight and navigation information from the onboard network, as well as additional data from other flight support computers. Incoming parameters include data on the current aircraft position (coordinates, altitude, speed, heading), flight mission parameters, the status of onboard systems and components, and external navigation information obtained from satellite, radio navigation, and inertial systems.

In parallel, the processor (4) accesses the database (5), which contains cartographic and auxiliary information necessary for the correct generation of indications. The database stores digital terrain maps, information on air routes, airports, high-altitude obstacles, meteorological data, and other parameters critical to the crew's situational awareness. Using the database information allows for consideration of not only current flight parameters but also predicted changes along the route, providing timely warning to the crew of potential threats and changes in the navigational situation.

Based on the received data, the processor (4) pre-processes the information, analyzes it, compares it with current flight conditions, and generates control commands for the FPGA. These commands determine the display parameters, including: the composition and arrangement of displayed elements (the set of graphic and text elements, as well as their placement on the screen), color coding (to highlight important information or warnings), data dynamics (the frequency or conditions of information update depending on current flight conditions), the presentation format of critical parameters, ensuring their quick and unambiguous perception, and the integration of information words into a single interface (without overloading the user's perception).

Next, the first FPGA (main) (2), using the primary visualization algorithm, receives control commands from the processor (4), after which it performs high-speed processing to generate the display in accordance with the specified parameters. The use of the FPGA (main) (2) allows for the integration of various information streams, graphic processing and filtering, adaptation of the visual representation to current flight conditions, and preparation of information for display on the display. This significantly minimizes delays in processing and preparation of information, ensuring high-speed operation of the computer.

The second FPGA (backup, control) (3) performs similar data processing independently of the first FPGA (main) (2). Upon receiving control commands from the processor (4), the second FPGA (backup, control) generates an indication using an alternative visualization algorithm, including redundancy and continuous verification of the received data against the results of the first FPGA (main) (2). This provides an additional level of verification of the generated indication, allowing for the identification of possible discrepancies and the prevention of incorrect or distorted information being output to the indicator.

If the processing results match, the video signal is transmitted via the physical LVDS port (1) to the on-board indicator display matrix, where it is visualized as a reliable and timely indication, providing the crew with access to critical data in real time.

If critical differences are detected between the data received by the FPGA, the FPGA (backup, control) (3) initiates additional checks or mechanisms to eliminate the possibility of displaying erroneous or incorrect data.

Thus, the proposed architecture of the on-board indicator computer increases the reliability and fault tolerance of the on-board indicator computer by increasing the speed of information processing and its reliability when displayed.

Claims (1)

A computer for an on-board indicator, including a physical port for receiving and transmitting information from/to the on-board network, a physical port for transmitting information to the on-board indicator, characterized in that it contains two programmable logic integrated circuits (FPGAs) interconnected and connected to a physical port for transmitting data to the on-board indicator, wherein the first FPGA is intended for high-speed data processing and generating an indication in accordance with specified parameters based on a visualization algorithm, the second FPGA is intended for generating an indication based on an alternative algorithm, redundancy and continuous reliability monitoring by comparing the obtained results with the data of the first FPGA, both FPGAs are connected by communication lines to a database and a processor that provides the ability to pre-process data for generating control commands in the FPGAs, with a physical port connected to them for receiving and transmitting information from/to the on-board network.