KR100275954B1 - Lcd panel driver - Google Patents

Abstract

The present invention relates to an LCD panel driver, wherein the gate driver is divided into two, and the odd and even lines of the LCD panel are divided and driven by using the divided gate drivers. There is a purpose.

The present invention for this purpose comprises a data selection section, a control section, a source driver, and first and second gate drivers. The data selector receives the image data signal, the horizontal synchronous signal, the vertical synchronous signal, and the first control signal to supply the first image data signal and the even-numbered line to be supplied to the odd-numbered line of the LCD panel according to the logic of the horizontal synchronous signal. The second image data signal is alternately latched, and one of the first image data signal and the second image data signal is output by the first control signal. The control unit receives the first image data or the second image data signal output from the data selection unit and outputs the first image data or the second image data signal according to a horizontal synchronization signal and the vertical synchronization signal. do. The source driver receives the first image data signal or the second image data signal output from the controller and outputs the first image data signal to the LCD panel. The first gate driver drives an odd number line of the LCD panel, and outputs the first control signal when driving of the odd number line is completed. The second gate driver drives an even numbered line of the LCD panel when the first control signal is output.

In the LCD panel driving circuit according to the present invention, the image data signal output from each channel of the source driver does not fully swing between the positive and negative voltage levels, thereby reducing power consumption. Significantly improve the operation speed.

Description

LCD panel drive circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LCD panel driver circuit, and more particularly, to an improvement in the structure of a gate driver of an LCD panel.

LCD panel is composed of a plurality of liquid crystal cells arranged in a matrix structure. One cell includes a MOS transistor, which is a switching element, and a liquid crystal part, and one cell can be driven by controlling a gate of the MOS transistor.

The image data signal is input to the source of the MOS transistor through a source driver, and the gate is sequentially controlled by a gate driver. When the gate of the MOS transistor is opened by the gate driver, the image data signal supplied to the source is transferred to the liquid crystal.

1 is a block diagram showing such a conventional LCD panel driving circuit.

The control unit 102 receives an image data signal RGB, a horizontal synchronizing signal H_SYNC, and a vertical synchronizing signal V_SYNC. The image data signal RGB input to the controller 102 is transmitted to the source driver 104 in accordance with the timing of the horizontal synchronous signal H_SYNC and the vertical synchronous signal V_SYNC. At this time, the control unit 102 also generates a polarity control signal POL and outputs it to the source driver 104. The polarity control signal POL is a signal for controlling the polarity (+ or-) of the image data signal.

The source driver 104 outputs the received image data signal RGB to each line of the LCD panel 106. The gate driver 108 operates by the driving signal D output from the controller 102 to activate each line of the LCD panel 106.

That is, when the image data signal RGB is supplied from the source driver 104 to one line of the LCD panel 106, the gate driver 108 opens the gate of the line to output one line of image signal.

The LCD panel driving method includes a line inversion method and a dot inversion method. The line inversion method inverts the polarity of the image data signal in line units of the LCD panel, and the dot inversion method inverts the polarity of the image data signal supplied to each pixel of the LCD panel in the diagonal direction.

The concept of the dot inversion method of the LCD panel is illustrated in FIG. 2A. As can be seen in Fig. 2A, a pixel that has a (+) polarity in the upper line has a (-) polarity in the next line, whereas a pixel that has a (-) polarity in the upper line has a (+) polarity in the next line. Inverting the polarity of the image data signal supplied to the neighboring pixels in this way is to slow down the aging of the pixel caused by supplying the image data signal of the same polarity to one pixel for a long time.

2B is a diagram showing a voltage range of an image data signal supplied to an LCD panel. As shown in Fig. 2B, the image data signal supplied to each pixel of the LCD panel swings between the voltage V1 in the negative (-) direction and the voltage V2 in the (+) direction with the center voltage VCOM as the center. do.

Therefore, in the case of using a conventional LCD panel driving circuit as shown in Fig. 1, image data signals of different polarities are generated in each channel (image data signal output terminal for driving one pixel) of the source driver 104 every line. Should output That is, full swing between V1 and V2 in FIG. 2B. Such a full swing of the image data signal makes it difficult to implement low power consumption and high speed operation.

Accordingly, an object of the present invention is to divide the gate driver into two, and to drive the odd-numbered and even-numbered lines of the LCD panel by using the divided gate drivers.

The present invention for this purpose comprises a data selection section, a control section, a source driver, and first and second gate drivers.

The data selector receives the image data signal, the horizontal synchronous signal, the vertical synchronous signal, and the first control signal to supply the first image data signal and the even-numbered line to be supplied to the odd-numbered line of the LCD panel according to the logic of the horizontal synchronous signal. The second image data signal is alternately latched, and one of the first image data signal and the second image data signal is output by the first control signal.

The control unit receives the first image data or the second image data signal output from the data selection unit and outputs the first image data or the second image data signal according to a horizontal synchronization signal and the vertical synchronization signal. do.

The source driver receives the first image data signal or the second image data signal output from the controller and outputs the first image data signal to the LCD panel.

The first gate driver drives an odd number line of the LCD panel, and outputs the first control signal when driving of the odd number line is completed. The second gate driver drives an even numbered line of the LCD panel when the first control signal is output.

1 is a block diagram showing a conventional LCD panel driving circuit.

Figure 2a is a view showing the concept of the dot inversion method of the LCD panel.

2B is a diagram showing a voltage range of an image data signal supplied to an LCD panel.

3 is a block diagram showing an LCD panel driving circuit according to the present invention.

4 is a block diagram showing a data selection unit of an LCD panel driving circuit according to the present invention;

Explanation of symbols on the main parts of the drawings

102, 304: control unit 104, 306: source driver

106, 308: LCD panel 108, 310, 312: gate driver

302: data selection unit 410, 414: tee flip-flop

POL: Polarity control signal V_SYNC: Vertical sync signal

H_SYNC: Horizontal Sync Signal

Referring to Figures 3 and 4 preferred embodiment of the present invention made as described above are as follows. 3 is a block diagram showing an LCD panel driving circuit according to the present invention.

The data selector 302 receives an image data signal RGB, a horizontal synchronous signal H_SYNC, a vertical synchronous signal V_SYNC, and a second gate driver driving signal S as a first control signal. The data selector 302 outputs the input image data signal RGB to the controller 304.

The data selector 302 alternately latches the odd-numbered image data signal RGB and the even-numbered image data signal RGB in accordance with the logical value of the horizontal synchronization signal H_SYNC. The odd-numbered image data signal RGB is supplied to the odd-numbered line of the LCD panel as the first image data signal RGB, and the even-numbered image data signal RGB is the even-numbered LCD data signal as the second image data signal RGB. Is supplied to line one.

The data selector 302 is configured to output one of the odd-numbered image data signal RGB and the even-numbered image data signal RGB in accordance with the second gate driver driving signal S described above.

The control unit 304 receives an odd-numbered image data signal RGB or an even-numbered image data signal RGB output from the data selector 302. The control unit 304 also receives the horizontal synchronizing signal H_SYNC and the vertical synchronizing signal V_SYNC together to control the output of the odd-numbered image data signal RGB and the even-numbered image data signal RGB.

The source driver 306 receives the odd-numbered image data signal RGB and the even-numbered image data signal RGB output from the controller 304 and supplies it to the LCD panel 308.

The first gate driver 310 drives the odd-numbered lines of the LCD panel 308, and generates a second gate driver driving signal S when driving of the odd-numbered lines is completed. The second gate driver driving signal S is outputted to the data selector 302 and the second gate driver 312 described above. The second gate driver 312 starts an operation by the second gate driver driving signal S to drive even-numbered lines of the LCD panel 308.

That is, the data selector 302 divides the image data signal RGB into an odd-numbered image data signal RGB and an even-numbered image data signal RGB, and supplies the same to the source driver 306. The gate driver also includes a first driver. The gate driver 310 is divided into a second gate driver 312 and drives odd-numbered lines of the LCD panel first and then even-numbered lines.

As described above, driving only odd-numbered lines of the LCD panel first and then even-numbered lines is performed by the operation of the data selector added according to the present invention. 4 is a block diagram illustrating a data selection unit of an LCD panel driving circuit according to the present invention.

The first tee flip-flop (T Flip-Flop) 410 receives a vertical synchronizing signal V_SYNC as a data signal IN and a horizontal synchronizing signal H_SYNC as a clock signal as a latch input as a second control signal. The control signal Q1 is generated.

The second tee flip-flop 414 also receives the vertical synchronization signal V_SYNC as the data signal IN, and the clock signal uses the second gate driver driving signal S described above. The output of the second tee flip-flop 414 is a latch output control signal Q2 which is a third control signal.

The vertical synchronization signal V_SYNC generates a single pulse at the time of notifying the start of one frame, and maintains a low level while a scan of one frame is in progress. The horizontal synchronization signal H_SYNC has as many single pulses as the number of lines the LCD panel has during one period of the vertical synchronization signal V_SYNC.

The tee flip-flop toggles the logic of the output signal every clock. Accordingly, the first tee flip-flop 410 using the horizontal sync signal H_SYNC as a clock outputs the latch input control signal Q1 of the inverted logic value every cycle of the horizontal sync signal H_SYNC. That is, the first tee flip-flop 410 outputs a logic value 1 in an odd period of the horizontal synchronization signal H_SYNC and a logic value 0 in an even period.

From this point of view, the second tee flip-flop 414 using the second gate driver driving signal S as a clock has a latch output control signal having a logic value inverted every 1/2 cycle of the vertical synchronization signal V_SYNC. (Q2) is generated. This is because the second gate driver driving signal S is generated immediately after scanning the odd-numbered lines (1/2 of one frame) of the LCD panel, and this point is 1 / time of the vertical synchronization signal V_SYNC. This is because it corresponds to 2 cycles. That is, the second tee flip-flop 414 outputs a logic value 1 during the first half vertical sync signal V_SYNC and a logic value 0 during the other half vertical sync signal V_SYNC.

The first odd-numbered data latch 402 receives and latches the image data signal RGB when the logic value of the latch input control signal Q1 is 1. The image data signal RGB is input to the first odd-numbered data latch 402 through three transmission gates 404 to 408 turned on by the latch input control signal Q1.

Since the latch input control signal Q1 has a logic value 1 for every odd period of the horizontal synchronization signal H_SYNC, as a result, all of the image data signals RGB input to the first odd-numbered data latch 402 are odd-numbered. It can be seen that it is for scanning the line.

When the new image data signal RGB is input to the first odd number data latch 402 and latched, the existing image data signal RGB that is latched is output to the second odd number data latch 412.

The first even-numbered data latch 416 receives and latches the image data signal RGB when the logic value of the latch input control signal Q1 is zero. The image data signal RGB is input to the first even-numbered data latch 416 through three other transmission gates 418 to 422 turned on by the latch input control signal Q1.

When the new image data signal RGB is input to the first even-numbered data latch 416 and latched, the existing image data signal RGB that is latched is output to the second even-numbered data latch 426.

The latch input control signal Q1 has a logic value of 0 every even period of the horizontal synchronization signal H_SYNC. When the signal is inverted by the inverter 424, the latch input control signal Q1 becomes a logic value 1. Accordingly, the three transmission gates 418 to 422 for switching the input terminals of the first even-numbered data latch 416 may be operated when the logic value of the latch input control signal Q1 becomes zero (that is, the horizontal synchronization signal H_SYNC). Every even period). As a result, it can be seen that the image data signal RGB input to the first even-numbered data latch 416 is for scanning even-numbered lines of the LCD panel.

The second odd-numbered data latch 412 and the second even-numbered data latch 426 have a storage capacity for storing image data signals required to scan a half frame of a full frame that an LCD panel can implement. To have.

As described above, when a half frame image data signal is stored in the second odd-numbered data latch 412 and the second even-numbered data latch 426 of sufficient storage capacity, the second tee flip-flop 414 is outputted. The image data signal RGB for scanning odd-numbered lines and the image data signal RGB for scanning even-numbered lines are alternately outputted by the latch output control signal Q2.

As described above, the latch output control signal Q2 that is the output of the second tee flip-flop 414 outputs a logic value 1 during the first half of the vertical synchronization signal V_SYNC and a logic value 0 during the other half. do. Therefore, the odd number line scanning image data signal RGB stored in the second odd number data latch 412 is output during the first half of the vertical synchronization signal V_SYNC, and the latch output control signal during the other half. When Q2 is inverted by the inverter 428, the even-numbered line scanning image data signal RGB stored in the second even-numbered data latch 426 is outputted.

Since the logic value of the latch output control signal Q2 is determined by the second gate driver driving signal S which is the clock of the second tee flip-flop 414, the image data signal output of the second odd-numbered data latch 412 is output. The time point and the time point at which the image data signal is output by the second even-numbered data latch 426 coincide with the operation time points of the first gate driver 310 and the second gate driver 312 of FIG. 3.

Therefore, the present invention divides the gate driver into two, and divides and drives the odd-numbered and even-numbered lines of the LCD panel by using the divided gate drivers, so that the image data signal output from each channel of the source driver is (+ The power consumption is reduced and operation speed is greatly improved by not swinging between the polarity voltage level and the negative voltage level.

Claims (7)

LCD panel driving circuit, The image data signal, the horizontal synchronous signal, the vertical synchronous signal, and the first control signal are input, and the first image data to be supplied to the odd-numbered line of the LCD panel and the even-numbered line according to the logic value of the horizontal synchronous signal. A data selector configured to alternately latch two image data signals, and output one of the first image data signal and the second image data signal by the first control signal; The first image data signal or the second image data signal output from the data selection unit is input, and outputs the first image data signal or the second image data signal according to the horizontal synchronization signal and the vertical synchronization signal. A control unit; A source driver for receiving the first image data signal or the second image data signal output from the controller and outputting the first image data signal to the LCD panel; A first gate driver driving an odd number line of the LCD panel and outputting the first control signal when driving of the odd number line is completed; And a second gate driver for driving even lines of the LCD panel when the first control signal is output. The method of claim 1, wherein the data selection unit, A first latch for latching the image data signal at every odd clock of the horizontal synchronization signal, and outputting the image data signal latched at every clock of the first control signal; And a second latch for latching the image data signal at every even clock of the horizontal synchronization signal and outputting the image data signal latched at every clock of the first control signal. The method of claim 1, wherein the data selection unit, A first tee flip-flop for inputting the vertical synchronous signal as a data signal and for inputting the horizontal synchronous signal as a clock signal to generate a second control signal; A second tee flip-flop for inputting the vertical synchronization signal as a data signal and for inputting the first control signal as a clock signal to generate a third control signal; A first odd number data latch for receiving and latching the image data signal when the logic value of the second control signal is 1; A second odd number data latch configured to receive and latch an image data signal latched to the first odd number data latch and output a latched image data signal every clock of the third control signal; A first even-numbered data latch configured to receive and latch the image data signal when the logic value of the second control signal is 0; And a second even number data latch configured to receive and latch an image data signal latched to the first even number data latch, and output a latched image data signal every clock of the third control signal. Panel driving circuit. The LCD panel driving circuit of claim 3, wherein the image data signal input to the first odd-numbered data latch is input through a first transmission gate switched by the second control signal. The method of claim 3, wherein the image data signal input to the first even-numbered data latch is input through a second transmission gate that is complementarily switched with the first transmission gate by the second control signal. LCD panel drive circuit. The LCD panel driving circuit of claim 3, wherein the second odd-numbered data latch and the second even-numbered data latch have a storage capacity for storing an image data signal capable of scanning 1/2 frame of the LCD panel. . The LCD panel driving circuit of claim 1, wherein the first control signal is a last line driving signal of the first gate driver.