KR100249540B1 - Mode selection circuit - Google Patents

Abstract

The mode selection circuit of the present invention which can reduce the area of a chip by providing a mode selection circuit for selecting an operation mode of a semiconductor chip without any additional input terminal includes a first inverter One); And a control signal for controlling the first inverter (1), which is controlled by the mode selection signal output of the first inverter (1) and rises to a time constant determined by the resistor (R1) and the capacitor (C1) And a second inverter (2) for outputting.

Description

Mode selection circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mode selection circuit provided on a semiconductor chip to select an operation mode of a semiconductor chip, and more particularly to a mode selection circuit for generating a control signal for selecting an operation mode in response to a rise time of a power supply voltage.

6 is a circuit diagram of a conventional semiconductor chip 110 that generates a control signal for selecting an operation mode of the internal circuit 15 through the interface circuit 12 in accordance with the state of a dedicated input terminal 14, Fig. 2 is a block diagram showing a mode selection circuit 111 of Fig.

For example, when the input terminal 14 is at the high level, the mode selection circuit 111 of FIG. 6 generates a high level control signal through the interface circuit 12 so that the internal circuit 15 operates in the test mode While when the input terminal 14 is grounded, a low level control signal is generated to control the internal circuit 15 to operate in a normal operation mode.

In the conventional technique of FIG. 6, a dedicated input terminal 14 for mode selection must be provided, so that a space must be secured on the semiconductor chip.

As a conventional technique for saving space, Japanese Patent Application Laid-Open No. 195719/1990 or Japanese Patent Laid-Open Publication No. 160416/1992 discloses a technique for providing a mode selection control signal , Only a mode selection signal) is generated.

7 shows a circuit diagram disclosed in Japanese Patent Laid-Open No. 195719/1990. In this example, a specific signal supplied to the input terminal 101 is divided into nine D-type flip-flops 105 to 113, five inverters Flop 124 and two NOR gates 119 and 120 and is coupled to the AND gate 13 in accordance with the output of the detector latched by the register having the RS type flip- Output terminal 129 is controlled by a switching circuit having three inverters 125 to 127. [

Thus, the input / output terminal 129 can supply a specific signal to the input terminals 101 and 102, without any additional input terminals; The output signal supplied from the wiring 128 or the input signal to be supplied to the wiring 131 can be switched.

Japanese Patent Application Laid-Open No. 160516/1992 discloses a mode selection circuit of Fig. 8 in which the logic of the input signal supplied to the input terminal 202 is latched and the same logic as the mode input signal 214 Two capacitors 207, and a resistor 209 when a power supply voltage is supplied from the power supply terminal 201 in order to enable the latch circuit 204 for outputting the power supply voltage to the internal circuit 211, , And the write signal generator 203 having the AND gate 210 generates a single write pulse.

Therefore, the input signal supplied to the input terminal 202 can be processed in the internal circuit 211 according to the mode selected by the mode selection signal determined by the initial logic of the input signal, even if there is no additional input terminal.

In the prior art disclosed in the above-mentioned Japanese publications, no additional input terminal is required for mode selection, but instead, a considerable amount of circuit elements are required to be installed, resulting in an increase in the chip size of the semiconductor do.

Therefore, the main object of the present invention is to provide a mode selection circuit capable of selecting the operation mode of the semiconductor chip while minimizing the size of the semiconductor chip without providing any additional input terminal.

1 is a circuit diagram showing an embodiment of the present invention;

FIG. 2A is a timing chart illustrating the operation of the embodiment of FIG. 1; FIG.

FIG. 2B is another timing chart illustrating the operation of the embodiment of FIG. 1; FIG.

3 is a block diagram showing an embodiment of a semiconductor chip 10 to which the circuit configuration shown in Fig. 1 is applied to the mode selection circuit 11. Fig.

4 is a block diagram showing another embodiment of the semiconductor chip 13 including a plurality of mode selection circuits 11-1 to 11-n each having the same configuration as the embodiment shown in Fig.

5 is a timing chart showing a power supply voltage rising with different time constants CR1 to CRn.

6 is a block diagram showing a semiconductor chip 110 in which a conventional mode selection circuit 111 is installed.

7 is a circuit diagram disclosed in Japanese Patent Application Laid-Open No. 195719/1990.

8 is a circuit diagram showing a conventional mode selection circuit disclosed in Japanese Patent Laid-Open No. 160416/1992.

DESCRIPTION OF THE REFERENCE NUMERALS

1: first inverter 2: second inverter

10: semiconductor chips 11, 11-1, 11-2, 11-3, ... , 11-n: Mode selection circuit

12, 16: Interface circuit 14: Input terminal

15, 17: Internal circuit

In order to achieve the above-mentioned object, there is provided a power supply apparatus for a vehicle, comprising at least one mode selection apparatus operated by a power source which is selectively raised to a first time constant or a second time constant, A second inverter connected between the power source and the ground for inputting a mode selection signal output from the first inverter and an output signal as an input signal to the first inverter; And a passive element connected between the output terminal to the two inverters and the ground so that the second inverter has a time constant greater than the first time constant and less than or equal to the second time constant, And the first inverter outputs a different mode selection signal when the number of the first inverters increases.

BRIEF DESCRIPTION OF THE DRAWINGS Further objects, features and advantages of the present invention will become more apparent from the detailed description set forth below, the appended claims, and the accompanying drawings, wherein like reference numerals are used to designate identical and corresponding components .

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 is a circuit diagram showing an embodiment of the present invention. The mode selection circuit of this embodiment includes a pMOS transistor P1 and a first nMOS transistor N1 which are connected in series between a power supply Vcc and a ground GND. And outputs a mode selection signal having the logic inverted logic of the node A connected to the gates thereof to the output connected to the drain of the pMOS transistor P1 and the drain of the first nMOS transistor N1 The reverse logic of the logic of the first inverter 1 outputting from the terminal OUT and the logic supplied from the output terminal OUT to the ground is connected to the power source Vcc through the resistor R1 A second inverter 2 having a second nMOS transistor to be outputted from a drain connected to the node A and a capacitor C1 provided between the node A and the ground GRD.

2A and 2B are timing charts showing the operation of the embodiment of FIG.

2A, when the power supply Vcc rises to a time constant shorter than the time constant determined by the resistor R1 and the capacitor C1, the potential Va of the node A is lower than the power supply Vcc The potential difference between the potential Va and the power source Vcc (i.e., V) gradually increases.

Potential difference ( The pMOS transistor P1 is turned on and the gate potential of the second nMOS transistor N2 is set to the high level, that is, the power supply voltage Vcc, when the gate voltage of the pMOS transistor P1 exceeds the threshold voltage Vth of the pMOS transistor P1. Or a potential level that is branched by the on-resistance of the first nMOS transistor N1 and the pMOS transistor P1 when the potential Va exceeds the threshold voltage of the first nMOS transistor, Level turns on the second nMOS transistor.

Therefore, the potential Va is converted to the low level to convert the mode selection signal to the high level, and the potential Va of the node A is stably maintained at the low level.

On the other hand, when the power source Vcc is controlled to rise to a time constant longer than the time constant determined by the resistor R1 and the capacitor C1, the potential Va of the node A Rises along the power supply Vcc to turn on the first nMOS transistor N1. Thus, the mode selection signal output of the output terminal OUT is maintained at the low level, and the gate of the second nMOS transistor N2 is turned off to maintain the voltage Va of the node A at the high level.

Therefore, in the mode selection circuit of the present invention, three MOS transistors P1, N1, and N2, a resistor R1, and a capacitor C1 (not shown) are provided without any input terminal for supplying an input signal to be detected, , The operation mode can be selected by the mode selection signal determined according to the rise time constant of the power source Vcc. Accordingly, in the above-described Japanese Patent Laid-Open Nos. 195719/1990 As compared with the prior art disclosed in the publications of Japanese Patent No. 160416/1992.

Although the positive power source Vcc of the present invention has been described so far based on the embodiment of FIG. 1, it goes without saying that various modifications are possible within the scope of the present invention. For example, when a negative power supply is used, a similar mode selection circuit is provided by replacing the second nMOS transistor N1 with a pMOS transistor and interchanging the pMOS transistor P1 and the first nMOS transistor N1 can do.

3 is a circuit diagram showing the configuration of the circuit shown in Fig. 1 applied to the mode selection circuit 11 and for controlling the internal circuit 15 through the interface circuit 12 in accordance with the rising time constant of the supplied power supply. Is a block diagram showing an embodiment of a semiconductor chip for generating a mode selection signal having a state (high level and low level).

4 shows another embodiment of the semiconductor chip 13 composed of a plurality of mode selection devices 11-1 to 11-n having the same configuration as in Fig. 1 but having a register and a capacitor which are provided with different time constants Fig.

By supplying power from the time constants CR1 to CRn exemplified in the timing chart of Fig. 5 that rise by one time constant to the logic of the mode selection signal output of the plurality of mode selection devices 11-1 to 11-n And then control by the control signal generated by the interface circuit 16 to select a corresponding operation mode from a plurality of operation modes of the internal circuit 17, for example, different test modes and normal operation modes It is possible.

According to the configuration of the present invention described above, the size of the semiconductor chip can be minimized by providing a mode selection circuit for selecting the operation mode of the semiconductor chip without any additional input terminal.

Claims (3)

Wherein the at least one mode selection device is connected between the power source and the ground, and the at least one mode selection device is connected between the power source and the ground, A first inverter for outputting an output signal; A second inverter connected between the power supply and the ground, for receiving the mode selection signal output from the first inverter and the output signal as an input signal to the first inverter; And a passive element connected between the output terminal of the second inverter and the ground to have the time constant of the second inverter greater than the first time constant and less than or equal to the second time constant, And the first inverter outputs a mode selection signal different from each other when rising to the first time constant and the second time constant. The method of claim 1, wherein the first inverter comprises a series connection of a pMOS and an nMOS connected between the power source and the ground, the mode selection signal is output from a contact between the pMOS and the nMOS, a gate of the nMOS is connected to a common terminal, and an output of the second inverter is input to the common terminal. Wherein said passive element is provided as a cacheter and said second inverter is operated by a power source which is diverted by the resistance of said second inverter and said capacitor, and wherein said mode < RTI ID = 0.0 > And an output of the second inverter rising at a time constant determined by the resistor and the capacitor is output from the drain of the MOS transistor connected to the contact of the resistor and the capacitor And a mode selection circuit.