JPWO2000014756A1 - Switch open/close state detection device and electronic device - Google Patents

Abstract

(57) [Abstract] The control circuit of a switch open/close state detection device controls the value of a resistor connected between one end of the switch whose open/close state is to be detected and the power supply or ground wire according to the voltage level of the power supply, thereby making it possible to widen the range of operating voltage, suppress the current that flows when the switch is turned on, thereby reducing the power consumption of electronic devices equipped with a switch open/close state detection device, and improving detection accuracy by ensuring the flow of detection current.

Description

Detailed Description of the Invention

TECHNICAL FIELD The present invention relates to a switch open/close state detection device and an electronic device, and more particularly to a switch open/close state detection device capable of detecting the open/close state of a switch with low power consumption and high accuracy, and an electronic device using the device. BACKGROUND ART In general electronic devices, various operations are performed using switches. However, in electronic devices that require low power consumption, the open/close state of the switch is not detected continuously but is detected intermittently, thereby minimizing the power consumed by the detection circuit. A configuration for detecting the open/close state of a switch used in such electronic devices will be described with reference to FIG. 17. As shown in this figure, one end of a switch SW whose open/close state is to be detected is grounded to a high-potential reference level Vdd, while the other end is connected to a detection circuit 900. Here, the detection circuit 900 is composed of an n-channel field-effect transistor 910 and a latch circuit 930. The drain of the transistor 910 is connected to the other end of the switch SW, and its source is connected to a negative power supply voltage Vss. A sampling pulse SP is supplied to the gate of the transistor 910. The latch circuit 930 latches the voltage level of the signal line A connected to the other end of the switch SW at the falling edge of the sampling pulse SP and outputs the signal Out indicating the open/closed state of the switch SW. In this detection circuit 900, the transistor 910 is turned on only during the "H" level period of the sampling pulse SP, and its on-resistance pulls down the signal line A to the power supply voltage Vss. Therefore, the voltage level of the signal line A remains at the power supply voltage Vss if the switch SW is open during the "H" level period of the sampling pulse SP, but transitions to the ground level if the switch SW is closed. Therefore, the latch circuit 930 latches the voltage level of the signal line A at the falling edge of the sampling pulse SP, thereby enabling the output of the signal Out corresponding to the open/closed state of the switch SW. Then, a subsequent circuit (not shown) executes processing corresponding to the instruction of the switch based on the signal Out. According to the detection circuit 900, a current does not always flow between the drain and source of the transistor 910, so it is possible to reduce the power consumption of the detection circuit 900. However, the power supply voltage Vss is not constant depending on the electronic device to which it is applied, and
For example, in an electronic device that includes a power generation mechanism and a power storage mechanism, and that uses the power stored in the power storage mechanism as a power source, the power supply voltage Vs may fluctuate depending on the state of charge.
This assumes that s fluctuates. Here, with a typical transistor, the lower the source-drain voltage, the higher its on-resistance; in other words, the resistance versus voltage characteristic is nonlinear. On the other hand, if signal line A is pulled down with a high resistance, its voltage level is likely to become unstable. Therefore, to stabilize the voltage level of signal line A even when the source-drain voltage is low, i.e., even when the difference between power supply voltage Vss and ground level is small, a transistor 910 with low on-resistance must be used. However, a configuration in which signal line A is pulled down with a transistor with low on-resistance inevitably increases the power consumption of detection circuit 900. This not only contradicts the original goal of achieving low power consumption, but also limits the range of power supply voltages over which the switch's open/closed state can be detected, due to the transistor's characteristics. This problem becomes more pronounced when the sampling rate is increased to accurately detect the open/closed state of switch SW. The reasons for this are as follows. That is, the signal line A has parasitic capacitance due to the transistor 910, the pads for mounting, wiring, etc. Here, when the switch SW is in the open state and charge is accumulated in this parasitic capacitance for some reason, if the sampling pulse SP goes to "H" level, the level of the signal line A will change over time according to the time constant of the parasitic capacitance and the pull-down resistor. For this reason, the signal line A will not be fixed at "L" level, where the switch SW is in the open state, until after it has been pulled down for a predetermined period of time. Therefore, in order to increase the sampling rate, the pulse width of the sampling pulse SP must be secured to a certain extent so that there is sufficient time until the level of the signal line A is fixed. This is because it means that the on-time of the transistor 910 is extended. The present invention has been made in view of the above problem, and its object is to
The present invention provides a switch open/close state detection device that can achieve both an expanded power supply voltage range over which the open/close state of a switch can be detected and improved detection accuracy for the open/close state of the switch, and an electronic device using the device. Disclosure of the Invention [0003] A first aspect of the present invention comprises a switch having one end connected to a ground line or a power supply, a resistor connected between the other end of the switch and the power supply or ground line, and a control unit that controls the value of the resistor based on the power supply voltage, which is the difference between the voltage level of the power supply and the ground level of the ground line, and outputs a signal corresponding to the open/close state of the switch corresponding to the voltage level at the other end of the switch. The first aspect of the present invention further comprises a discrimination unit that discriminates the voltage level at the other end of the switch and outputs a signal corresponding to the open/close state of the switch. The discrimination unit of the first aspect of the present invention further discriminates the voltage level at predetermined intervals. The control unit of the first aspect of the present invention also controls the value of the resistor so that the value of the resistor does not exceed a predetermined upper resistance value. The control unit of the first aspect of the present invention is characterized in that it controls the resistance value so that the resistance value is within a resistance range defined by a predetermined upper limit resistance value and a predetermined lower limit resistance value. The resistor of the first aspect of the present invention is a variable resistor whose resistance value changes based on a power supply voltage, and when comparing voltages in terms of their absolute values, the resistance value set by the control unit when the power supply voltage is higher than a predetermined reference voltage is a virtual resistance value obtained by assuming that the measurement is performed under power supply voltage conditions where the power supply voltage is lower than the predetermined reference voltage. When comparing voltages in terms of their absolute values, the control unit determines the resistance value to be set when the power supply voltage is lower than the predetermined reference voltage as follows:
The present invention is characterized in that the resistance value is controlled to be smaller than the virtual resistance value under power supply voltage conditions. Furthermore, the resistor of the first aspect of the present invention is characterized in that it is composed of multiple sub-resistors, and the control unit controls the number of resistors to be connected between the other end of the switch and the power supply or ground line based on the power supply voltage. Furthermore, the resistor of the first aspect of the present invention is characterized in that it is composed of multiple sub-resistors having approximately the same resistance value, and the control unit connects more sub-resistors in parallel when the power supply voltage is lower than the reference voltage than the number of sub-resistors to be connected when the power supply voltage is higher than the reference voltage. Furthermore, the resistor of the first aspect of the present invention is characterized in that it is composed of multiple sub-resistors having different resistance values, and the control unit selects one or more sub-resistors to be connected between the other end of the switch and the power supply or ground line based on the power supply voltage. Furthermore, the control unit of the first aspect of the present invention is characterized in that multiple mutually different reference voltages are predetermined. Furthermore, the resistor of the first aspect of the present invention is characterized in that it is a transistor and is turned on at intervals at which the voltage level at the other end of the switch is determined. A first aspect of the present invention provides a resistor switching circuit that includes a switch having one end connected to a ground line or a power supply, a resistor connected between the other end of the switch and the power supply or the ground line, and a resistance value switching circuit that switches the value of the resistor based on a power supply voltage that is a difference between the voltage level of the power supply and the ground level of the ground line, and that determines the voltage level at the other end of the switch and:
The resistor of the first aspect of the present invention is characterized in that it outputs a signal corresponding to the open/closed state of the switch. Furthermore, the first aspect of the present invention is characterized in that it includes a latch circuit that determines the voltage level at the other end of the switch and outputs a signal corresponding to the open/closed state of the switch. Furthermore, the latch circuit of the first aspect of the present invention is characterized in that it determines the voltage level at predetermined intervals. Furthermore, the resistor of the first aspect of the present invention is a variable resistor whose resistance value changes based on the power supply voltage, and when comparing voltages in terms of their absolute values, the resistance value set by the resistance value switching circuit when the power supply voltage is higher than a predetermined reference voltage is a virtual resistance value that is a resistance value obtained when measured under power supply voltage conditions where the power supply voltage is lower than the predetermined reference voltage, and the resistance value switching circuit controls the resistance value to be set when the power supply voltage is lower than the predetermined reference voltage so that it is smaller than the virtual resistance value under the power supply voltage conditions. A second aspect of the present invention is characterized by comprising a power supply for supplying electric power, a voltage detection unit for detecting the voltage of the power supply, a switch having one end connected to a ground line or the power supply, a resistor connected between the other end of the switch and the power supply or the ground line, a control unit for controlling the value of the resistor based on the power supply voltage which is the difference between the voltage level of the power supply detected by the voltage detection unit and the ground level of the ground line, a discrimination unit for discriminating the voltage level at the other end of the switch and outputting a signal corresponding to the open/closed state of the switch, and a processing unit for executing processing content instructed by the switch in accordance with the signal output by the discrimination unit.Furthermore, the discrimination unit of the present invention is characterized by discriminating the voltage level at predetermined intervals. In a second aspect of the present invention, the resistor is a variable resistor whose resistance value changes based on the power supply voltage, and when comparing the absolute values of the voltages, the control unit sets a resistance value when the power supply voltage is higher than a predetermined reference voltage, assuming that the resistance value is measured under power supply voltage conditions where the power supply voltage is lower than the predetermined reference voltage. The control unit controls the resistance value to be set when the power supply voltage is lower than the predetermined reference voltage, so that the resistance value under the power supply voltage conditions is smaller than the virtual resistance value. In addition, the processing unit in the second aspect of the present invention is characterized by including a timing unit that performs various timing processes instructed by a switch. In addition, the power supply in the second aspect of the present invention is characterized by including a power storage unit that stores power generated by the power generation mechanism and supplies the power stored in the power storage unit. Furthermore, in the second aspect of the present invention, the power supply includes a voltage control unit that controls the output voltage from the power storage unit in accordance with the voltage detected by the voltage detection unit. Best Mode for Carrying Out the Invention Next, a best mode for carrying out the present invention will be described with reference to the drawings.
[1] First embodiment [1.1] Circuit configuration of detection circuit Fig. 1 is a circuit diagram showing the configuration of a detection circuit 100 according to a first embodiment of the present invention. As shown in Fig. 1, one end of a switch SW whose open/closed state is to be detected is grounded to a reference level Vdd on the high potential side, and the other end of the switch SW is connected to the detection circuit 100. Here, the detection circuit 100 includes n-channel field effect transistors 110a, 110b, 110c, 110d, 110e, 110f ...
The circuit is composed of a transistor 110a and a transistor 110b, an AND circuit 120, and a latch circuit 130. Of these, the transistors 110a and 110b are both of the same type,
The performance of the transistors 110a and 110b is almost the same, with each drain connected to the other end of the switch SW and each source connected to the negative power supply voltage Vss. A sampling pulse SP is supplied to the gate of the transistor 110a, and the gate of the transistor 110b is connected to the output terminal of the AND circuit 120. The AND circuit 120 outputs the logical product of the sampling pulse SP and a signal CMP supplied from a voltage detection circuit 400 (see FIG. 4) described later, which goes to "H" level when the difference between the power supply voltage Vss and a reference level Vdd serving as the ground level is equal to or greater than a threshold value Vth. The latch circuit 130, like the latch circuit 930 in FIG. 17, detects the voltage level of the signal line A connected to the other end of the switch SW by the sampling pulse SP.
and outputs it as a signal Out indicating the open/closed state of the switch SW. [1.2] Operation of the Detection Circuit Next, the operation of the detection circuit 100 will be described with reference to FIGS.
FIG. 2 shows the relationship between the power supply voltage Vss and the resistance value for pulling down the signal line A. Although the horizontal axis in FIG. 2 represents the power supply voltage Vss, since the power supply voltage Vss is actually a negative power supply, strictly speaking, the horizontal axis represents the difference between the power supply voltage Vss and the reference level Vdd (=|Vdd-Vss|), or the right direction is the negative axis. When this voltage difference is greater than the threshold value Vth, the signal CMP goes low. Therefore, while the sampling pulse SP is high, only the transistor 110a turns on, pulling down the signal line A. Therefore, in this case alone, there is no difference from the conventional detection circuit 900. Furthermore, as the power supply discharge progresses and the difference between the power supply voltage Vss and the reference level Vdd becomes equal to or less than the threshold value Vth, the signal CMP goes high. This opens the AND circuit 120, causing the output of the AND circuit 120 to go high. Here, the threshold voltage Vth is set to a voltage level corresponding to a value just before the upper limit M of the range in which the voltage level of the signal line A is reliably determined by the on-resistance of the transistor 110a. When the AND circuit 120 is open and the sampling pulse SP is at the "H" level, both the transistors 110a and 110b are on, and the parallel connection of the on-resistances pulls down the signal line A.
2, the resistance value that pulls down the signal line A is about half that when only the transistor 110a is turned on, so the voltage level of the signal line A is pulled down reliably. More generally, when a transistor (= a variable resistor whose resistance value changes based on the power supply voltage) is used and the voltage is compared in terms of its absolute value, the resistance value of the power supply voltage (|Vdd-
When the voltage Vss|) is higher than a predetermined reference voltage (=Vth), the resistance value set by the detection circuit 100 (corresponding to the control unit) is assumed to be measured under power supply voltage conditions where the power supply voltage is lower than the predetermined reference voltage, and the resistance value obtained is taken as a virtual resistance value (corresponding to the dashed line portion extending the curve (a) in FIG. 2 to the low voltage side). When the voltages are compared in absolute value, the detection circuit 100 controls the resistance value to be set so that it is smaller than the virtual resistance value under power supply voltage conditions where the power supply voltage is lower than the predetermined reference voltage. In other words, by controlling the resistance value to a value as shown by the curve (a) in FIG. 2, the voltage level of the signal line A is reliably pulled down. In this regard,
In terms of units of the power supply voltage Vs, the same applies to a case where there are multiple reference voltages, as in the case of the third modified example described later. [1.3] Effects of the First Embodiment As described above, according to the detection circuit 100 of the first embodiment, the power supply voltage Vs
When the difference between Vss and the reference level Vdd is greater than the threshold value Vth, only the transistor 110a is turned on during the "H" level period of the sampling pulse SP, thereby suppressing power consumption, whereas when the difference is equal to or less than the threshold value Vth, both the transistors 110a and 110b are turned on, thereby stabilizing the voltage level of the signal line A. Therefore, even when the power supply voltage Vss fluctuates within a certain range, it is possible to achieve both low power consumption and improved detection accuracy. In other words, the range of the power supply voltage Vss within which the voltage level of the signal line A is stable is 1
In the conventional configuration in which the signal line A is pulled down by only one transistor, the range is limited to a region above the threshold Vth.
0, it is possible to expand the range to above the threshold Vth. [1.4] Modifications of the First Embodiment Note that the present invention is not limited to the detection circuit 100 according to the above-described embodiment, and various applications and modifications are possible. [1.4.1] First Modification For example, the detection circuit 100 according to the embodiment has been described as a type in which the power supply voltage is a negative power supply, but as shown in FIG. 3, the transistors 110a, 110b, 110c, 110d, 110e, 110f, 110g, 110h, 110i, 110j, 110i ...
The present invention can also be applied to a type in which the transistors 110a and 110b are p-channel and the power supply voltage is a positive power supply. [1.4.2] Second Modification Alternatively, instead of using the same type of transistors 110a and 110b as in the embodiment, it is possible to use a transistor 110a with a relatively high on-resistance and a transistor 110b with a relatively low on-resistance, and to selectively turn on the transistors depending on the power supply voltage by turning on only the transistor 110a when the power supply voltage is high and turning on only the transistor 110b when the power supply voltage is low. [1.4.3] Third Modification Furthermore, it is also possible to use a configuration in which three or more transistors are arranged in parallel instead of just two, and the number of transistors turned on increases stepwise as the power supply voltage decreases. [1.4.3.1] Specific Configuration of the Third Modification More specifically, the detection circuit 10 in FIG. 4 shows a configuration in which three transistors are arranged in parallel.
4 shows a circuit diagram of the detection circuit 100A. As shown in FIG. 4, one end of the switch SW, the open/close state of which is to be detected, is grounded to a reference level Vdd on the high potential side, and the other end of the switch SW is connected to a detection circuit 100. The detection circuit 100A includes an n-channel field effect transistor 110a,
The transistors 110a, 110b, and 110c are all of the same type and have almost the same performance, with their drains connected to the other end of the switch SW and their sources connected to the negative power supply voltage Vss. A sampling pulse SP is supplied to the gate of the transistor 110a, and the gate of the transistor 110b is connected to the output terminal of the AND circuit 120.
The gate of the transistor 110c is connected to the output terminal of the AND circuit 120A. Here, the AND circuit 120A outputs the logical product of a signal CMP1, which is supplied from a voltage detection circuit or the like (not shown) and goes to "H" level when the difference between the power supply voltage Vss and the reference level Vdd (the ground level) is equal to or less than a threshold value Vth1, and a sampling pulse SP. The AND circuit 120A also outputs the logical product of a signal CMP2, which is supplied from a voltage detection circuit or the like (not shown) and goes to "H" level when the difference between the power supply voltage Vss and the reference level Vdd (the ground level) is equal to or less than a threshold value Vth2 (<Vth1), and a sampling pulse SP. Furthermore, the latch circuit 130, like the latch circuit 930 in FIG. 17, detects the voltage level of the signal line A connected to the other end of the switch SW by a sampling pulse S.
The signal CMP1 is latched at the falling edge of P and output as a signal Out indicating the open/closed state of the switch SW. [1.4.3.2] Operation of the detection circuit of the third modification Next, the operation of the detection circuit 100A will be described with reference to FIGS. 4 and 5. Here, FIG. 5 is a diagram showing the relationship between the power supply voltage Vss and the resistance value that pulls down the signal line A, similar to FIG. 2. Now, when this voltage difference is larger than the threshold value Vth1, the signal CMP1 is set to "L
Since the signal CMP2 goes to the "H" level and the signal CMP2 goes to the "L" level, only the transistor 110a is turned on and pulls down the signal line A while the sampling pulse SP is at the "H" level. Therefore, in this case only, there is no difference from the conventional detection circuit 900. Furthermore, as the power supply discharge progresses and the difference between the power supply voltage Vss and the reference level Vdd becomes equal to or less than the threshold value Vth1, the signal CMP1 goes to the "H" level, the AND circuit 120 opens, and the output of the AND circuit 120 goes to the "H" level. Furthermore, since the signal CMP2 remains at the "L" level, the AND circuit 120A remains closed, and the output of the AND circuit 120A remains at the "L" level. Here, the threshold voltage Vth1 is set to a voltage level corresponding to a value just before the upper limit M of the range in which the voltage level of the signal line A is reliably determined by the on-resistance of the transistor 110a. When the AND circuit 120 is open, both the transistors 110a and 110b are turned on during the period when the sampling pulse SP is at the "H" level, and the signal line A is pulled down by the parallel connection of the on-resistors.
5, the resistance value for pulling down the signal line A is about half that when only the transistor 110a is turned on, so the voltage level of the signal line A is pulled down reliably. Furthermore, when the power supply discharge progresses and the difference between the power supply voltage Vss and the reference level Vdd becomes equal to or less than the threshold value Vth2, the signals CMP1 and CMP2 become "H" level, so that the AND circuits 120 and 120A open and the outputs of the AND circuits 120 and 120A become "H" level. Here, the threshold voltage Vth2 is determined by the resistance value of the transistor 110a and the transistor 110b.
00b, the voltage level of the signal line A is set to a value just before the upper limit value M of the range in which the voltage level of the signal line A is reliably determined. When the AND circuit 120 and the AND circuit 120A are in an open state, the transistors 110a, 110b, and 110C are in an open state while the sampling pulse SP is at the "H" level.
5, the resistance value for pulling down the signal line A is approximately 1/2 of that when only the transistor 110a is turned on.
3, the voltage level of signal line A is reliably pulled down. [1.4.4] Fourth Modification In addition, the connection topology from one end of switch SW to the power supply voltage may be controlled in accordance with the power supply voltage. For example, if the power supply voltage is high, the resistors may be connected in series, whereas if the power supply voltage is low, the resistors may be connected in parallel. [1.4.5] Fifth Modification In the above explanation, the threshold voltage is set to a voltage level just below the upper limit M of the range in which the voltage level of signal line A is reliably determined by the on-resistance of a transistor or the parallel on-resistance of multiple transistors. However, in order to prevent the current flowing through each transistor from becoming unnecessarily large in order to reduce power consumption when switch SW is on, as shown in FIG. 6, the threshold voltage may be set to a lower limit M' of the range in which the voltage level of signal line A is reliably determined and in which the amount of current when switch SW is on is a predetermined amount.
[1.4.6] Sixth Modification In the first embodiment and each modification, the state of the switch SW is detected at predetermined intervals corresponding to the sampling pulse SP, but it is also possible to configure the switch SW to be constantly detected. More specifically, the AND circuit 120 and the latch circuit 130 in FIG. 1 are omitted, and a predetermined voltage is applied to the gate of the transistor 110a to keep it always on,
The signal CMP may be input directly to the gate of the transistor 100b, and the voltage level of the signal line A may be directly output as a signal Out indicating the open/closed state of the switch SW. [1.5] Electronic Device Next, an example in which the detection circuit 100 according to the first embodiment is applied to an actual electronic device will be described. FIG. 7 is a block diagram showing the configuration of an electronic watch as an example of an electronic device. Briefly, this electronic watch has a 1/10-second chronograph function in addition to a normal time display function, and the opening and closing of the switch SW starts and stops the timekeeping operation of the chronograph function. [1.5.1] Configuration of the Electronic Watch Each component of the electronic watch will now be described. [1.5.1.1] Power Generation Mechanism First, the power generation mechanism 410 will be described in detail with reference to FIG. 8. As shown in FIG. 8, the power generation mechanism 410 includes a two-pole magnetized disk-shaped rotor 411 and a stator 413 around which an output coil 412 is wound. In this configuration, when a person wearing the electronic timepiece swings their wrist, the oscillating weight 414 rotates, and this rotation rotates the rotor 411 via the gear train mechanism 415. This rotation generates an electromotive force in the output coil 412, and AC output is extracted. As shown in Figure 7, the AC output generated by the power generation mechanism 410 is converted to DC by the rectifier diode D and charged into the capacitor C1 of the power supply circuit 430, which will be described later. Therefore, the voltage of the capacitor C1 is, to be precise, the output voltage of the power generation mechanism 410 minus the forward voltage of the rectifier diode D. [1.5.1.2] Limiter Circuit The limiter circuit 420 prevents overcharging of the capacitor C1.
In detail, when the voltage of the capacitor C1, which has risen due to charging, reaches or exceeds the rated value, the power supply circuit 430 is energized to bypass the charging current. [1.5.1.3] Power Supply Circuit The power supply circuit 430, which will be described in detail later, includes a plurality of capacitors including the capacitor C1 and a plurality of switches, and charges the capacitor C1 with the power generated by the power generation mechanism 410, and also boosts the output voltage of the capacitor C1 in stages to supply it to each part as the power supply voltage Vss. [1.5.1.4] Voltage Detection Circuit The voltage detection circuit 440 detects the power supply voltage Vss (the difference between the power supply voltage Vss and the reference level Vdd)
First, if the detected power supply voltage Vss is equal to or less than the threshold value Vth, a signal CMP is outputted which goes to "H" level. Second, the detected power supply voltage Vss is outputted to the boost control circuit 45.
0. Here, a specific configuration of the voltage detection circuit 440 will be described. FIG. 9 shows a block diagram of the main part of the voltage detection circuit 440. The voltage detection circuit 440 includes an inverter 44
0 A, the reference level Vdd is applied to the source terminal, and the inverter 4
a p-channel MOS transistor 440B to which the output terminal of 40A is connected; a first voltage dividing resistor RR1 having one end connected to the drain terminal of the p-channel MOS transistor 440B; a second voltage dividing resistor RR2 having one end connected to the first voltage dividing resistor RR1 and the other end to which the power supply voltage Vss is applied; and a reference voltage generating circuit 440
9, the reference voltage Vd is a reference voltage Vd, and the comparator 440D has an inverting input terminal connected to the connection point between the first voltage dividing resistor RR1 and the second voltage dividing resistor RR2, a non-inverting input terminal connected to the reference voltage generating circuit 440C, an enable signal ENABLE input to a control terminal, and outputs a comparison result as comparison result data RESULT, and a latch circuit 440E has a clock terminal C to which a voltage detection timing signal DETECT that goes to "H" level prior to the voltage detection timing is input, a data terminal D to which the comparison result data RESULT is input, and which outputs a signal CMP from an inverting output terminal XQ.
When d=00 [V] and the power supply voltage Vss=-1.2 [V], the first voltage dividing resistor RR1=100 [kΩ], the second voltage dividing resistor RR2=20 [kΩ], and the reference voltage of the reference voltage generating circuit 440C=-1.0 [V]. Next, the voltage detection operation of the voltage detection circuit 440 will be described with reference to FIGS. 10 and 11. The enable signal ENABLE goes to "H" level for a predetermined period every 2 [sec]. Then, while the enable signal ENABLE is at "H" level, the inverter 440A outputs an output signal at "L" level, and the p-channel MOS transistor 4
40B is turned on. Similarly, the comparator 440D is turned on. In parallel with this, the power supply voltage Vss is applied to the first voltage dividing resistor RR1 and the second voltage dividing resistor RR2.
2 and input to the inverting input terminal of the comparator 440D as a comparison voltage. As a result, the comparator 440D compares the reference voltage generated by the reference voltage generating circuit 440C with the comparison voltage, and outputs the comparison result data RESU
10, when the comparison target voltage is lower than the reference voltage generated by the reference voltage generating circuit 440C, the comparison result data RESULT becomes "H" level, and when the voltage detection timing signal DETECT falls at time t2, the comparison result data RESULT is output to the data terminal D of the latch circuit 440E.
However, in this case, since the inverting output terminal XQ is already at the "L" level, the signal CMP output from the inverting output terminal XQ does not change at all. Conversely, if the comparison voltage is higher than the reference voltage generated by the reference voltage generating circuit 440C, the enable signal ENABLE
is at the "H" level, the comparison result data RESULT becomes "L" level,
At time t4, when the voltage detection timing signal DETECT falls, the comparison result data RESULT is captured by the latch circuit 440E. In this case, the signal CMP output from the inverted output terminal XQ transitions from the "L" level to the "H" level. When making these determinations, the input timing of the sampling signal SP input to the latch circuit 130 of the detection circuit 110 and the voltage detection timing signal DETECT
The input timings of the sampling pulse SP and the voltage detection timing signal DETECT must be set to be different from each other, as shown at time t1 and time t2 in FIG.
11, the signal φ128 is a reference signal with a 1/128 second period used to realize a 1/10 second chronograph, and the sampling pulse SP and the enable signal ENABLE are synchronized with the signal φ128. [1.5.1.5] Boost Control Circuit The boost control circuit 450 controls the voltage detection circuit 440 to control each switch of the power supply circuit 430.
The boost control circuit 450 controls the boost of the power supply circuit 430 by supplying a control signal for controlling opening and closing in accordance with the power supply voltage Vss detected by the detection circuit 100. [1.5.1.6] Switch The switch SW starts and stops the chronograph function by opening and closing it. One end is grounded, while the other end is connected to the detection circuit 100. The detection circuit 100 is the same as in the embodiment described above, and detects the open/closed state of the switch SW and outputs a signal Out indicating that state. The clock circuit 460 performs a chronograph function in response to the signal Out in addition to the normal time display function. In addition, an oscillator circuit (not shown) supplies a boost/charge switching signal to the boost control circuit 450, a sampling pulse SP to the detection circuit 100, and a reference signal for time display and chronograph to the clock circuit 460. [1.5.2] Details of the Power Supply Circuit The detailed configuration of the power supply circuit 430 will now be described with reference to FIG. 12.
2, the power supply circuit 430 is composed of capacitors C1 to C4 and switches S1 to S7, and charges the capacitor C1 with the power generated by the power generation mechanism 410, and controls the output voltage Vs of the capacitor C1 by the switches S1 to S7.
s' is stepped up in stages and supplied to each part as power supply voltage Vss. Here, switches S1 to S7 are actually composed of transmission gates, transistors, etc. [1.5.2.1] Specific Operation of Power Supply Circuit The operation of the power supply circuit 430 configured as above will be explained assuming that the voltage range in which each part can operate is 0.9 to 1.8 V, and that after capacitor C1 is fully charged, power generation by the power generation mechanism 410 ceases. In this case, the power supply circuit 430 initially operates so that capacitors C1 and C2 are at the same potential. In detail, the boost control circuit 450 controls switches S3,
Only switch S1, S3, and S4 are turned on, while the other switches are controlled to be off. As a result, the power supply circuit 430 becomes equivalent to the circuit shown in FIG. 13(a), so that the output voltage Vss' of capacitor C1 is output as the power supply voltage Vss. Next, as the discharge of capacitor C1 progresses and the power supply voltage Vss reaches 1.2 V at time t1 shown in FIG. 14, the power supply circuit 430 operates to boost the output voltage Vss' of capacitor C1 by 1.5 times. More specifically, when the voltage detection circuit 440 detects that the power supply voltage Vss has reached 1.2 V, the boost control circuit 450, upon receiving notification of this detection result, first turns on switches S1, S3, and S6, while controlling the other switches to be off. As a result, the power supply circuit 430 becomes equivalent to the circuit shown in the left column of FIG. 13(b), so that capacitors C3 and C4 are each charged with a voltage 0.5 times the output voltage Vss' of capacitor C1. After this, the boost control circuit 450 turns on the switches S2, S4, S5, and S7, while turning off the other switches. As a result, the power supply circuit 430 becomes equivalent to the circuit shown in the right column of FIG. 13(b), and the capacitor C2 is connected to the capacitor C1 and the capacitor C3, which is charged with a voltage 0.5 times that of the capacitor C1.
(C4) is connected in series with the capacitor C1, and as a result, the output voltage V
A voltage 1.5 times the output voltage Vss' of capacitor C1 will be output as power supply voltage Vss. Furthermore, as the discharge of capacitor C1 progresses and power supply voltage Vss reaches 1.2 V at time t2 shown in FIG. 14, power supply circuit 430 operates to double the output voltage Vss' of capacitor C1. More specifically, when voltage detection circuit 440 detects that power supply voltage Vss has again reached 1.2 V, boost control circuit 450, which has received notification of this detection result, first turns on switches S1, S3, S5, and S7, while controlling the other switches to be off. As a result, power supply circuit 430 operates as shown in FIG. 13(c).
Since the circuit is equivalent to the circuit shown in the left column of
13C, and the capacitor C2 is charged with a voltage equal to the voltage of the capacitor C1 and the capacitor C3 (C
4) is charged by the series connection with the capacitor C1, resulting in an output voltage Vss
Then, when the discharge of the capacitor C1 further progresses and the power supply voltage Vss reaches 1.2 V at time t3 shown in FIG. 14, the power supply circuit 430 discharges the capacitor C1.
13(d), the power supply circuit 430 operates to boost the output voltage Vss' of 1.1 by three times. In detail, when the voltage detection circuit 440 detects that the power supply voltage Vss has again reached 1.2V, the boost control circuit 450, which is notified of this detection result, first turns on the switches S1, S3, S5, and S7, while controlling the other switches to be off. As a result, the power supply circuit 430 operates as shown in FIG.
13(d), the capacitors C3 and C4 are each charged with a voltage equal to one time the output voltage Vss' from the capacitor C1. After this, the boost control circuit 450 turns on the switches S2, S4, and S6, and controls the other switches to be off. As a result, the power supply circuit 430 becomes equivalent to the circuit shown in the right column of FIG. 13(d), and the capacitor C2 is charged with a voltage equal to one time the output voltage Vss' from the capacitor C1.
As a result of the series connection of capacitor C1, capacitor C3 charged with the same voltage, and capacitor C4, a voltage three times the output voltage Vss' of capacitor C1 is output as the power supply voltage Vss. Note that the operation has been described assuming that power generation by the power generation mechanism 410 is no longer performed. However, conversely, if power generation by the power generation mechanism 410 is performed and the power generated exceeds the power consumed by each circuit component, capacitor C1 is charged, and the output voltage Vss' rises. Here, when the output voltage Vss' of capacitor C1 rises due to power generation and the power supply voltage Vss reaches 1.8 V, an operation is performed to gradually reduce the boost factor. For example, if the current boost factors are 3, 2, and 1.5, respectively, and the power supply voltage Vss reaches 1.8 V, the boost factors will be reduced to 2, 1.5, and 1.
In this way, in the power supply circuit 430, when the power supply voltage Vss drops to 1.2 V, the boosting factor is increased by one step, while when the power supply voltage Vss drops to 1.8 V, the boosting factor is increased by one step.
, the boost factor is reduced by one step, and as a result, the output voltage Vss' of the capacitor C1 that charges the generated power drops to 0.
Even if the power supply voltage Vss is within the range of 0.9 V, the
Since the voltage is maintained at 1.8V or less, the charged power can be effectively utilized and the operable time can be extended to, for example, time t4 in Figure 14. [1.5.3] Effects of the Electronic Watch Furthermore, with this electronic watch, the start/stop of the chronograph function is instructed by opening and closing the switch SW, and the open/closed state of this switch is detected by the detection circuit 1.
00, it is possible to achieve both low power consumption and improved detection accuracy.
The common voltage detection circuit 440 detects the power supply voltage Vss, which is required for switching the transistors in the MOSFETs, thereby simplifying the circuit configuration. In particular, if the transistors 110a and 110b (and also the transistor 110c) within the detection circuit 100 are selected and designed so that the threshold voltage Vth is 1.2V, this will be the same as the 1.2V voltage level that serves as the boost judgment criterion, eliminating the need to increase the voltage level to be judged, further simplifying the circuit configuration. [1.5.4] Modified Examples of Electronic Timepieces: While the above electronic timepiece uses a capacitor C1 as the main component for charging the power generated by the power generation mechanism, any secondary battery capable of storing power will suffice. Furthermore, in addition to the power generation mechanism shown in FIG. 5, any type of power generation mechanism can be used, including solar cells, thermoelectric generators, and piezoelectric generators. Electronic devices to which the detection circuit 100 according to the above embodiment can be applied include:
In addition to the electronic clocks mentioned above, LCD TVs, video tape recorders, notebook personal computers, mobile phones, PDAs (Personal Digital Assistants), etc.
Examples include a personal digital assistant (PDAs), a calculator, etc. [2] Second embodiment Next, a detection circuit according to a second embodiment will be described. [2.1] Circuit configuration of detection circuit Fig. 15 is a circuit diagram showing the configuration of a detection circuit 100B according to a second embodiment of the present invention. As shown in Fig. 15, one end of a switch SW whose open/closed state is to be detected is grounded to a reference level Vdd on the high potential side, and the other end of the switch SW is connected to the detection circuit 100B. Here, the detection circuit 100B includes an n-channel field effect transistor 140a,
140b, two-input AND circuits 150A and 150C, and a three-input AND circuit 1
The transistor 140a is composed of OR circuits 160A and 160B, OR circuits 160A and 160B, and a latch circuit 170. Of these, transistor 140a has a larger impedance (resistance value) than transistor 140b, and each drain is connected to the other end of switch SW, while each source is connected to the negative power supply voltage Vss. Furthermore, AND circuit 150A outputs the logical product of an inverted signal of signal CMP1 and a sampling pulse SP. Here, signal CMP1 is supplied from a voltage detection circuit or the like, and becomes "H" level when the difference between the power supply voltage Vss and a reference level Vdd (ground level) is less than threshold value Vth1. Furthermore, AND circuit 150B outputs the logical product of three signals: signal CMP1, the inverted signal of signal CMP2, and the sampling pulse SP. Here, the signal CMP2 is supplied from a voltage detection circuit or the like, and is a signal that goes to "H" level when the difference between the power supply voltage Vss and the reference level Vdd, which is the ground level, is less than a threshold value Vth2 (<Vth1).
The OR circuit 160A outputs the logical product of the output signal of the AND circuit 150A and the output signal of the AND circuit 150B.
Furthermore, the OR circuit 160B outputs the logical sum of the output signals of the AND circuit 150B and the AND circuit 150C.
17, the latch circuit 170 outputs the logical sum of the output signals of the sampling pulse SP.
, and outputs a signal Out indicating the open/closed state of the switch SW. [2.2] Operation of the Detection Circuit Next, the operation of the detection circuit 100B will be described with reference to Fig. 16. When the difference (= |Vdd-Vss|) between the power supply voltage Vss and the reference level Vdd is equal to or greater than the threshold value Vth1, the signals CMP1 and CMP2 are at the "L" level. Therefore, while the sampling pulse SP is at the "H" level, the AND circuit 150A
The output of the AND circuit 150B is "H", the output of the AND circuit 150C is "L", and the output of the AND circuit 150D is "L". As a result, the output of the OR circuit 160A is "H", the output of the OR circuit 160B is "L".
", and during the period when the sampling pulse SP is at "H" level, the transistor 1
Transistor 140 has a large impedance (resistance value) compared to 40b
Only signal line a is turned on, pulling down signal line A. Furthermore, when the power supply discharge progresses and the difference between the power supply voltage Vss and the reference level Vdd becomes less than threshold value Vth1 and equal to or greater than threshold value Vth2, signal CMP2 becomes "L" level and signal CMP1 becomes "H" level, so that sampling pulse S
During the period when P is at the "H" level, the output of the AND circuit 150A is "L", the output of the AND circuit 150B is "H", and the output of the AND circuit 150C is "L". As a result, the output of the OR circuit 160A is "L", and the output of the OR circuit 160B is "H".
", and during the period when the sampling pulse SP is at "H" level, the transistor 1
Only 40b is turned on, pulling down the signal line A. Furthermore, when the power supply discharge progresses and the difference between the power supply voltage Vss and the reference level Vdd becomes less than the threshold value Vth2, the signals CMP1 and CMP2 become "H" level. Therefore, while the sampling pulse SP is at "H" level, the AND circuit 150A
The output of the AND circuit 150B is "L", the output of the AND circuit 150C is "H". As a result, the output of the OR circuit 160A is "H", the output of the OR circuit 160B is "H".
", and during the period when the sampling pulse SP is at "H" level, the transistor 1
40a and transistor 140b are turned on, pulling down the signal line A. In this way, the resistance value that pulls down the signal line A is gradually reduced as the power supply voltage drops, so the voltage level of the signal line A is pulled down reliably. [2.3] Effects of the Second Embodiment As described above, according to the detection circuit 100B of the second embodiment, the power supply voltage V
When the difference between ss and the reference level Vdd is greater than the threshold value Vth1, only the transistor 140a with a larger resistance value is turned on during the "H" level period of the sampling pulse SP, and power consumption is suppressed. When the difference is equal to or less than the threshold value Vth1 and is greater than the threshold value Vth2, only the transistor 140B with a smaller resistance value is turned on, and power consumption is suppressed while the voltage is pulled down reliably. When the difference is further less than the threshold value Vth2, the transistor 140a
, 140b are turned on, and the voltage level of the signal line A is stabilized.
The present invention provides a method for detecting the open/closed state of a switch by controlling a resistance connected between the power supply or the ground line and one end of the switch, the open/closed state of which is to be detected, by a control circuit in accordance with the power supply voltage level.
It is possible to achieve both low power consumption and improved detection accuracy. In this case, the improvement in detection accuracy can be achieved by: (1) making it less likely that the on/off state of the switch will be erroneously detected; (2) making it possible to more accurately recognize the on or off time of the switch; and (3) making it possible to grasp the transition state of the switch, such as the transition from the on state to the off state and the transition from the off state to the on state, in a short time from the time the switch is operated.

[Brief explanation of the drawings]

FIG. 1 is a circuit diagram showing the configuration of a detection circuit for detecting the open/closed state of a switch according to a first embodiment of the present invention. FIG. 2 is a diagram for explaining the operation of the detection circuit according to the first embodiment. FIG. 3 is a circuit diagram showing the configuration of a first modified example of the detection circuit according to the first embodiment. FIG. 4 is a circuit diagram showing the configuration of a third modified example of the detection circuit according to the first embodiment. FIG. 5 is a diagram for explaining the operation of the third modified example of the detection circuit according to the first embodiment. FIG. 6 is an explanatory diagram of a fifth modified example of the detection circuit according to the first embodiment. FIG. 7 is a block diagram showing the configuration of an electronic timepiece as an example of an electronic device to which the detection circuit according to the first embodiment is applied. FIG. 8 is a perspective view showing the configuration of a power generation mechanism in the electronic timepiece of FIG. 7. FIG. 9 is a block diagram showing the configuration of the main parts of the voltage detection circuit in the electronic timepiece of FIG. 7. FIG. 10 is a diagram for explaining the operation of the voltage detection circuit. FIG. 11 is a diagram for explaining the relationship between sampling pulses and voltage detection timing. FIG. 12 is a circuit diagram showing the configuration of a power supply circuit in the electronic timepiece of FIG. 7. FIG. 13 is a simplified diagram showing an equivalent circuit during charging and boosting in the power supply circuit of FIG. 12. FIG. 14 is a diagram for explaining the charging and boosting operation in the power supply circuit of FIG. 12. Fig. 15 is a circuit diagram showing the configuration of a detection circuit for detecting switch open/close states according to a second embodiment of the present invention, Fig. 16 is a diagram for explaining the operation of the detection circuit of the second embodiment, and Fig. 17 is a circuit diagram showing the configuration of a conventional switch open/close state detection circuit.

─────────────────────────────────────────────────────── (Note) This publication is based on the publication published internationally by the International Bureau of Patents (WIPO). The effect of the international publication of the Japanese patent application (Japanese utility model registration application) related to this publication arises pursuant to Article 184-10, Paragraph 1 of the Patent Act (Article 48-13, Paragraph 2 of the Utility Model Act) and is unrelated to this publication.

Claims (21)

[Claims] [Claim 1] A switch open/closed state detection device comprising: a switch having one end connected to a ground line or a power supply; a resistor connected between the other end of the switch and the power supply or ground line; and control means for controlling the value of the resistor based on a power supply voltage that is the difference between the voltage level of the power supply and the ground level of the ground line, wherein the device outputs a signal corresponding to the open/closed state of the switch, which corresponds to the voltage level at the other end of the switch. 2. The switch open/closed state detection device according to claim 1, further comprising a discrimination means for discriminating the voltage level at the other end of the switch and outputting a signal corresponding to the open/closed state of the switch. 3. The switch open/closed state detection device according to claim 2, wherein said determining means determines said voltage level at predetermined intervals. [Claim 4] The switch open/close state detection device according to claim 2, wherein the control means controls the value of the resistor so that the value of the resistor does not exceed a predetermined upper limit resistance value. [Claim 5] In the switch open/closed state detection device described in claim 2, the control means controls the value of the resistor so that the value of the resistor falls within a resistance range defined by a predetermined upper limit resistance value and a predetermined lower limit resistance value. [Claim 6] A switch open/closed state detection device according to claim 2, wherein the resistor is a variable resistor whose resistance value changes based on the power supply voltage, and a virtual resistance value is a value of the resistor obtained when the value of the resistor set by the control means when the power supply voltage is higher than a predetermined reference voltage is measured under power supply voltage conditions in which the power supply voltage is lower than the predetermined reference voltage when the voltages are compared in absolute value, and the control means controls the value of the resistor to be set when the power supply voltage is lower than the predetermined reference voltage so that it is smaller than the virtual resistance value under the power supply voltage conditions when the voltages are compared in absolute value. [Claim 7] A switch open/closed state detection device according to claim 6, wherein the resistor is composed of a plurality of sub-resistors, and the control means controls the number of resistors to be connected between the other end of the switch and the power supply or ground line based on the power supply voltage. [Claim 8] A switch open/closed state detection device according to claim 6, wherein the resistor is composed of a plurality of secondary resistors having approximately the same resistance value, and the control means connects a greater number of secondary resistors in parallel when the power supply voltage is lower than the reference voltage than the number of secondary resistors that should be connected when the power supply voltage is higher than the reference voltage. [Claim 9] A switch open/closed state detection device according to claim 6, wherein the resistor is composed of a plurality of secondary resistors having different resistance values, and the control means selects one or more of the secondary resistors from the plurality of secondary resistors to be connected between the other end of the switch and the power supply or ground line based on the power supply voltage. 10. The switch open/closed state detection device according to claim 6, wherein said control means predetermines a plurality of said reference voltages which are different from one another. [Claim 11] The switch open/closed state detection device according to claim 2, wherein the resistor is a transistor, and is turned on at intervals at which the voltage level at the other end of the switch is determined. [Claim 12] A switch open/closed state detection device comprising: a switch having one end connected to a ground line or a power supply; a resistor connected between the other end of the switch and the power supply or ground line; and a resistance value switching circuit that switches the value of the resistor based on a power supply voltage that is the difference between the voltage level of the power supply and the ground level of the ground line, and that outputs a signal corresponding to the open/closed state of the switch that corresponds to the voltage level at the other end of the switch. 13. The switch open/closed state detection device according to claim 12, further comprising a latch circuit that determines the voltage level at the other end of the switch and outputs a signal corresponding to the open/closed state of the switch. 14. The switch open/closed state detection device according to claim 13, wherein said latch circuit determines said voltage level at predetermined intervals. [Claim 15] A switch open/closed state detection device according to claim 13, wherein the resistor is a variable resistor whose resistance value changes based on the power supply voltage, and when comparing voltages in terms of their absolute values, the resistance value set by the resistance value switching circuit when the power supply voltage is higher than a predetermined reference voltage is a virtual resistance value obtained when the resistance value is measured under power supply voltage conditions in which the power supply voltage is lower than the predetermined reference voltage, and the resistance value switching circuit controls the resistance value to be set when the power supply voltage is lower than the predetermined reference voltage so that it is smaller than the virtual resistance value under the power supply voltage conditions when comparing voltages in terms of their absolute values. [Claim 16] An electronic device comprising: a power supply that supplies electric power; voltage detection means that detects the voltage of said power supply; a switch having one end connected to a ground line or a power supply; a resistor connected between the other end of said switch and the power supply or the ground line; control means that controls the value of said resistor based on the power supply voltage that is the difference between the voltage level of said power supply detected by said voltage detection means and the ground level of said ground line; discrimination means that discriminates the voltage level at the other end of said switch and outputs a signal corresponding to the open/closed state of said switch; and processing means that executes processing content instructed by said switch in accordance with the signal output by said discrimination means. 17. The electronic device according to claim 16, wherein said determining means determines said voltage level at predetermined intervals. [Claim 18] An electronic device according to claim 16, wherein the resistor is a variable resistor whose resistance value changes based on the power supply voltage, and when comparing voltages in terms of their absolute values, the value of the resistor set by the control means when the power supply voltage is higher than a predetermined reference voltage is a virtual resistance value obtained when the value is measured under power supply voltage conditions in which the power supply voltage is lower than the predetermined reference voltage, and the control means controls the value of the resistor to be set when the power supply voltage is lower than the predetermined reference voltage so that it is smaller than the virtual resistance value under the power supply voltage conditions when comparing voltages in terms of their absolute values. 19. The electronic device according to claim 16, wherein said processing means comprises a timing means for executing various timing processes instructed by said switch. 20. The electronic device according to claim 16, wherein the power supply includes a storage means for storing electric power generated by a power generation mechanism, and supplies the electric power stored by the storage means. 21. The electronic device according to claim 20, further comprising: voltage control means for controlling an output voltage from said power storage means in accordance with the voltage detected by said voltage detection means.