JPS6342594Y2 - - Google Patents

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Publication number
JPS6342594Y2
JPS6342594Y2 JP1981094533U JP9453381U JPS6342594Y2 JP S6342594 Y2 JPS6342594 Y2 JP S6342594Y2 JP 1981094533 U JP1981094533 U JP 1981094533U JP 9453381 U JP9453381 U JP 9453381U JP S6342594 Y2 JPS6342594 Y2 JP S6342594Y2
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Japan
Prior art keywords
terminal
amplifier
variable resistors
variable
fixed
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1981094533U
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Japanese (ja)
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JPS58516U (en
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Priority to JP9453381U priority Critical patent/JPS58516U/en
Publication of JPS58516U publication Critical patent/JPS58516U/en
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Description

【考案の詳細な説明】 本考案はグラフイツク・イコライザ回路に係
り、回路の利得のばらつきを利得調整回路等を使
用することなく略無くし得て、入力信号に対し任
意の周波数特性を付与して出力するグラフイツ
ク・イコライザ回路を提供することを目的とす
る。
[Detailed description of the invention] The present invention relates to a graphic equalizer circuit, which can substantially eliminate variations in circuit gain without using a gain adjustment circuit, etc., and outputs an input signal with arbitrary frequency characteristics. The purpose of the present invention is to provide a graphic equalizer circuit that performs the following functions.

第1図A,Bは従来のグラフイツク・イコライ
ザ回路の各例の回路図を示す。第1図A中、入力
端子1に入来した例えば音声信号は演算増幅器2
の非反転入力端子に供給され、ここで後述する如
く、n個(nは複数)の分割周波数帯域について
夫々独立に所望の利得で非反転増幅された後、抵
抗R1、増幅器3を夫々経て出力端子5より出力
される。ここで、演算増幅器2の出力端子は抵抗
R2を介してその反転入力端子に接続されており、
また抵抗R1と増幅器3の入力端子との接続点は
n個の可変抵抗器VR1〜VRoを夫々並列に介して
演算増幅器2の反転入力端子に接続されている。
可変抵抗器VR1〜VRoは夫々固定端子a,b(以
下、端子a,bと略す)間の中点位置に中点タツ
プcを有しており、また端子a,b間を摺動する
摺動子dを有している。
FIGS. 1A and 1B show circuit diagrams of examples of conventional graphic equalizer circuits. In FIG. 1A, for example, an audio signal entering input terminal 1 is input to operational amplifier 2.
The signal is supplied to the non-inverting input terminal of , and is non-invertingly amplified with a desired gain for each of the n (n is plural) divided frequency bands, as described later, and then passed through the resistor R 1 and the amplifier 3, respectively. It is output from the output terminal 5. Here, the output terminal of operational amplifier 2 is a resistor
connected to its inverting input terminal via R 2 ,
Further, the connection point between the resistor R 1 and the input terminal of the amplifier 3 is connected to the inverting input terminal of the operational amplifier 2 through n variable resistors VR 1 to VR o , respectively, in parallel.
The variable resistors VR 1 to VR o each have a midpoint tap c at the midpoint position between fixed terminals a and b (hereinafter abbreviated as terminals a and b), and a sliding resistor between fixed terminals a and b. It has a slider d.

可変抵抗器VR1〜VRoの各摺動子dは互いに異
なる共振周波数で共振するよう構成された共振回
路41〜4oを介して接地されており、一方、各中
点タツプcは夫々共通に接地されている。可変抵
抗器VR1〜VRoの摺動子dは夫々互いに独立して
摺動され得るよう構成されており、入力音声信号
は摺動子dの接触位置に応じてその摺動子dが接
続されている共振回路の共振周波数及びその近傍
周波数の帯域がレベル増強、レベル減衰又は平坦
な周波数特性が付与されることは周知の通りであ
る。例えば、摺動子dが中点タツプcに接触して
いるときは平坦周波数特性を示し、また端子a方
向に摺動されるときはそれにつれて負帰還量が減
少するので徐々にレベル増強される特性を示し、
更に中点タツプcより端子b方向に摺動されると
きはそれにつれて徐々にレベル減衰される特性を
示す。
Each slider d of the variable resistors VR 1 to VR o is grounded via a resonant circuit 4 1 to 4 o configured to resonate at mutually different resonance frequencies, while each center tap c is connected to the ground, respectively. Commonly grounded. The sliders d of the variable resistors VR 1 to VR o are configured so that they can be slid independently of each other, and the input audio signal is transmitted depending on the contact position of the slider d. It is well known that level enhancement, level attenuation, or flat frequency characteristics are imparted to the resonance frequency of the resonant circuit and its neighboring frequency band. For example, when the slider d is in contact with the center tap c, it exhibits a flat frequency characteristic, and when it is slid in the direction of the terminal a, the amount of negative feedback decreases accordingly, so the level is gradually increased. showing the characteristics,
Furthermore, when it is slid from the center tap c toward the terminal b, it exhibits a characteristic in which the level is gradually attenuated.

また第1図Bに示す従来のグラフイツク・イコ
ライザ回路は、同図Aの従来回路に比し演算増幅
器2と増幅器3の接続順序と、可変抵抗器VR1
VRoの端子aが演算増幅器2の反転入力端子に接
続されると共に端子bが非反転入力端子に接続さ
れた点が異なるだけであり、その周波数特性の付
与は同図Aに示す従来回路と同一の方法により行
ない得る。
Furthermore, the conventional graphic equalizer circuit shown in FIG. 1B differs from the conventional circuit shown in FIG .
The only difference is that terminal a of VR o is connected to the inverting input terminal of operational amplifier 2, and terminal b is connected to the non-inverting input terminal, and the frequency characteristics given are different from the conventional circuit shown in FIG. It can be done by the same method.

上記の第1図A又はBに示す従来のグラフイツ
ク・イコライザ回路において、可変抵抗器VR1
VRoの各端子a,c間の抵抗値(以下これをRac
と記す)と、端子b,c間の抵抗値(以下これを
Rbcと記す)とは、本来等しい値となるように製
造されているはずであるが、実際には製造上の精
度の問題で、一度に多数の可変抵抗器を製造する
と、抵抗値Rac,Rbcのいずれか一方が他方よりも
大になる傾向がある。このように抵抗値RacとRbc
とが不等であると、上記の従来回路では利得がば
らつくことになる。
In the conventional graphic equalizer circuit shown in FIG. 1A or B above, the variable resistors VR 1 to
The resistance value between each terminal a and c of VR o (hereinafter referred to as R ac
) and the resistance value between terminals b and c (hereinafter referred to as
R bc ) are supposed to be manufactured to have the same value, but in reality, due to manufacturing accuracy issues, if many variable resistors are manufactured at once, the resistance value R ac , R bc tends to be larger than the other. In this way, the resistance values R ac and R bc
If these are unequal, the gain will vary in the above conventional circuit.

すなわち、第1図Aに示す従来回路において、
摺動子dが中点タツプcの位置に在るときの利得
Gは G=R2+Rac/n/Rac/n×Rbc/n/R1+Rbc/n(1
) となり、Rac=Rbc、R1=R2であればG=1とな
るから平坦な周波数特性が得られることになる。
しかるに、Rac>Rbcの場合、Rac=K・Rbc(ただ
しKは定数でK>1)とすると、上記利得Gは次
式で示す如くになる。
That is, in the conventional circuit shown in FIG. 1A,
The gain G when the slider d is at the center tap c is as follows: G=R 2 +R ac /n/R ac /n×R bc /n/R 1 +R bc /n(1
), and if R ac = R bc and R 1 = R 2 , then G = 1, so a flat frequency characteristic can be obtained.
However, in the case of R ac >R bc , if R ac =K·R bc (K is a constant and K>1), the gain G becomes as shown in the following equation.

G=R2+K・Rbc/n/K・Rbc/n×Rbc/n/R1+R
bc/n ここで、R1=R2とおくと上式は G=R1+K・Rbc/n/K・(R1+Rbc/n) =1+R1(1−K)/K(R1+Rbc/n)(2) となる。ここで、K>1だから、(2)式の右辺第2
項は負となるので利得Gは1より小となり、減衰
傾向を示すことになる。
G=R 2 +K・R bc /n/K・R bc /n×R bc /n/R 1 +R
bc /n Here, if R 1 = R 2 , the above formula becomes G = R 1 +K・R bc /n/K・(R 1 +R bc /n) = 1+R 1 (1-K)/K(R 1 + R bc /n) (2). Here, since K>1, the second right-hand side of equation (2)
Since the term is negative, the gain G is less than 1, indicating a tendency to attenuate.

他方、Rac<Rbcの場合は前記Kは0<K<1で
あるから(2)式の右辺第2項は正となり、利得Gは
1より大となるので増大傾向を示すことになる。
On the other hand, in the case of R ac < R bc , the above K is 0 < K < 1, so the second term on the right side of equation (2) is positive, and the gain G is larger than 1, so it shows an increasing tendency. .

そこで、従来は上記の抵抗値Rac,Rbcの不等に
よつて生ずる利得のばらつきを補正するために、
第1図A中との個所に第2図に示す如き抵抗
R3及び可変抵抗器VRaよりなる利得調整回路を
挿入接続して、見掛け上Rac/n=Rbc/nとして利得G を一定(R1=R2の場合はG=1)としていた。
Therefore, conventionally, in order to correct the variation in gain caused by the above-mentioned inequality in the resistance values R ac and R bc ,
A resistor as shown in Fig. 2 is placed at the point A in Fig. 1.
By inserting and connecting a gain adjustment circuit consisting of R 3 and a variable resistor VR a , the gain G was apparently kept constant as R ac /n = R bc /n (G = 1 in the case of R 1 = R 2 ). .

しかるに、上記の従来回路は、利得調整のため
の回路が必要であつたため、部品点数が増加し、
コストが高くなり、また調整が煩雑である等の欠
点があつた。
However, the above conventional circuit requires a circuit for gain adjustment, which increases the number of components.
There were disadvantages such as high cost and complicated adjustment.

本考案は上記欠点を除去したものであり、以下
その一実施例につき第3図と共に説明する。
The present invention eliminates the above-mentioned drawbacks, and one embodiment thereof will be described below with reference to FIG. 3.

第3図は本考案になるグラフイツク・イコライ
ザ回路の一実施例の要部の回路図を示す。同図
中、第1図A,Bと同一構成部分には同一符号を
付してある。第3図において、同種の可変抵抗器
VR1〜VRoのうちi−1個(ただしiはnより小
なる自然数で、ここでは4以上である)の可変抵
抗器VR1〜VRi-1の各端子aは、残りの可変抵抗
器VRi〜VRoの各端子bに夫々接続され、かつ、
可変抵抗器VR1〜VRi-1の各端子bはVRi〜VRo
の各端子aに夫々接続されている。すなわち、第
3図中、1点鎖線より上ので示す範囲内の可変
抵抗器VR1〜VRi-1とで示す範囲内のVRi
VRoとは夫々互いに逆向きに接続されている。た
だし、各可変抵抗器VR1〜VRoの中点タツプcは
夫々共通に接地され、摺動子dは共振回路41
oに各別に接続される点については従来回路と
同様である。なお、端子a,bの区別は、可変抵
抗器VR1〜VRoに付されている端子番号や例えば
向きを示すマークなどに基づいて行なえる。
FIG. 3 shows a circuit diagram of a main part of an embodiment of the graphic equalizer circuit according to the present invention. In the figure, the same components as in FIGS. 1A and 1B are designated by the same reference numerals. In Figure 3, the same type of variable resistor
Each terminal a of VR 1 to VR i-1 of i-1 variable resistors VR 1 to VR i-1 (where i is a natural number smaller than n, and is 4 or more here) among VR 1 to VR o is connected to the remaining variable resistor. connected to each terminal b of the devices VR i to VR o , and
Each terminal b of the variable resistor VR 1 ~ VR i-1 is VR i ~ VR o
are connected to each terminal a of the terminal a. That is, in FIG. 3, the variable resistors VR 1 to VR i-1 within the range shown above the dashed-dotted line and VR i to VR i-1 within the range shown above.
VR o and each other are connected in opposite directions. However, the center tap c of each variable resistor VR 1 to VR o is commonly grounded, and the slider d is connected to the resonant circuit 4 1 to VR o.
4 o is connected to each other separately as in the conventional circuit. Note that the terminals a and b can be distinguished based on the terminal numbers attached to the variable resistors VR 1 to VR o or, for example, marks indicating directions.

これにより、可変抵抗器VR1〜VRoが抵抗値
Rac>Rbcなる場合であつても、Rac<Rbcなる場合
であつても、Rac,Rbcの不等による利得Gへのば
らつきの影響を軽減又は除去することができる。
すなわち、いま可変抵抗器VR1〜VRoの半数を
夫々互いに逆向きに接続したものとすると(この
とき上記i−1はn/2となる)、と接地間の抵
抗値RAは、と接地間の抵抗値RBと等しくなる。
This makes the variable resistor VR 1 ~ VR o the resistance value
Even if R ac >R bc or R ac <R bc , the influence of variations in gain G due to the inequality of R ac and R bc can be reduced or eliminated.
That is, if half of the variable resistors VR 1 to VR o are connected in opposite directions (in this case, the above i-1 becomes n/2), the resistance value R A between and ground is as follows. It is equal to the resistance value R B between ground.

RA=Rac/n/2Rbc/n/2 RB=Rbc/n/2Rac/n/2 抵抗値RA,RBは(1)式のRac/n,Rbc/nに相当する から Rac/n=RA=RB=Rbc/n となり、見掛け上Rac=Rbcとなる。従つて、利得
Gが一定しばらつきをなくすことができる。しか
も、この場合、利得調整の操作は全く不要であ
る。
R A = R ac /n/2R bc /n/2 R B = R bc /n/2R ac /n/2 The resistance values R A and R B are R ac /n and R bc /n in equation (1) Since it corresponds to R ac /n=R A = R B = R bc /n, it appears that R ac = R bc . Therefore, the gain G is constant and variations can be eliminated. Moreover, in this case, no gain adjustment operation is required at all.

なお、本実施例において、可変抵抗器VR1
VRi-1の摺動子dを端子a又はb方向へ摺動した
ときにレベル増強特性(又はレベル減衰特性)が
得られるものとすると、可変抵抗器VRi〜VRo
摺動子dを端子b又はa方向へ摺動したときにレ
ベル増強特性(又はレベル減衰特性)が得られる
ことは明らかである。
In addition, in this embodiment, the variable resistors VR 1 to
Assuming that a level enhancement characteristic (or level attenuation characteristic) is obtained when the slider d of VR i-1 is slid in the direction of terminal a or b, the slider d of variable resistors VR i to VR o It is clear that a level enhancement characteristic (or a level attenuation characteristic) is obtained when the terminal is slid in the direction of terminal b or a.

なお、VR1〜VRoのうち互いに逆方向に接続す
る可変抵抗器の数は全体の数の半数n/2どおしと
したときが最も良い結果が得られるが、実用上利
得のばらつきが問題とならないようにできれば良
いから、これに限定されるものではない。
Incidentally, the best results are obtained when the number of variable resistors VR1 to VR0 connected in opposite directions is half the total number, n/2, but this is not limited to this as long as it is possible to prevent gain variation from becoming a problem in practice.

上述の如く、本考案になるグラフイツク・イコ
ライザ回路は、入力信号を増幅する増幅器と、増
幅器の入力端子に第1の固定端子が接続され増幅
器の出力端子に第2の固定端子が接続されると共
に中点タツプ端子が接地され、かつ、その中点タ
ツプ端子と上記第1、第2の固定端子との間の両
抵抗値が不等である可変抵抗器の複数個からなる
第1の可変抵抗器群と、上記増幅器の入力端子に
第2の固定端子が接続され増幅器の出力端子に第
1の固定端子が接続されると共に中点タツプ端子
が接地され、かつ、その中点タツプ端子と上記第
1、第2の固定端子との間の両抵抗値が不等であ
る可変抵抗器の複数個からなる第2の可変抵抗器
群と、互いに独立に摺動せしめられる第1及び第
2の可変抵抗器群の夫々の摺動子に各別に接続さ
れており、前記入力信号に対し複数の分割周波数
帯域毎にレベル制御を行なうために互いに共振周
波数が異ならしめられた複数個の共振回路とから
なるため、従来、上記可変抵抗器の中点タツプ端
子と第1、第2の固定端子との間の両抵抗値が不
等であつたために生じていたグラフイツク・イコ
ライザ回路の利得のばらつきを、利得調整のため
の新たな部品を全く使用することなく従来回路と
同一の部品数で略なくすことができ、従来と同一
の製造コストで済み、しかも従来必要であつた利
得調整操作も全く不要にでき利得調整の煩雑さを
完全に解消することができる等の特長を有するも
のである。
As described above, the graphic equalizer circuit according to the present invention includes an amplifier for amplifying an input signal, a first fixed terminal connected to the input terminal of the amplifier, a second fixed terminal connected to the output terminal of the amplifier, and a second fixed terminal connected to the output terminal of the amplifier. a first variable resistor consisting of a plurality of variable resistors whose midpoint tap terminal is grounded and whose resistance values between the midpoint tap terminal and the first and second fixed terminals are unequal; a second fixed terminal is connected to the input terminal of the amplifier, a first fixed terminal is connected to the output terminal of the amplifier, and a center tap terminal is grounded; A second variable resistor group consisting of a plurality of variable resistors having unequal resistance values between the first and second fixed terminals, and a first and second variable resistor group that are slidable independently of each other. a plurality of resonant circuits each connected to each slider of the variable resistor group and having mutually different resonant frequencies in order to control the level of the input signal for each of the plurality of divided frequency bands; This eliminates the variation in gain of the graphic equalizer circuit that conventionally occurred due to the unequal resistance values between the midpoint tap terminal of the variable resistor and the first and second fixed terminals. , it is possible to eliminate the need for any new parts for gain adjustment, with almost the same number of parts as the conventional circuit, and the manufacturing cost is the same as before, and the gain adjustment operation that was required in the past is completely unnecessary. This has the advantage of being able to completely eliminate the complexity of gain adjustment.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図A,Bは夫々従来の各例を示す回路図、
第2図は利得調整回路を有する従来のグラフイツ
ク・イコライザ回路の一例の要部を示す回路図、
第3図は本考案の一実施例の要部を示す回路図で
ある。 1……入力端子、2……演算増幅器、3……増
幅器、41〜4o……共振回路、5……出力端子、
VR1〜VRo……可変抵抗器。
FIGS. 1A and 1B are circuit diagrams showing conventional examples, respectively;
FIG. 2 is a circuit diagram showing a main part of an example of a conventional graphic equalizer circuit having a gain adjustment circuit;
FIG. 3 is a circuit diagram showing a main part of an embodiment of the present invention. 1... Input terminal, 2... Operational amplifier, 3... Amplifier, 4 1 to 4 o ... Resonant circuit, 5... Output terminal,
VR 1 ~ VR o ...Variable resistor.

Claims (1)

【実用新案登録請求の範囲】 1 入力信号を増幅する増幅器と、該増幅器の入
力端子に第1の固定端子が接続され該増幅器の
出力端子に第2の固定端子が接続されると共に
中点タツプ端子が接地され、かつ、その中点タ
ツプ端子と上記第1、第2の固定端子との間の
両抵抗値が不等である可変抵抗器の複数個から
なる第1の可変抵抗器群と、該増幅器の入力端
子に第2の固定端子が接続され該増幅器の出力
端子に第1の固定端子が接続されると共に中点
タツプ端子が接地され、かつ、その中点タツプ
端子と上記第1、第2の固定端子との間の両抵
抗値が不等である可変抵抗器の複数個からなる
第2の可変抵抗器群と、互いに独立に摺動せし
められる該第1及び第2の可変抵抗器群の夫々
の摺動子に各別に接続されており、上記入力信
号に対し複数の分割周波数帯域毎にレベル制御
を行なうために互いに共振周波数が異ならしめ
られた複数個の共振回路とから構成したグラフ
イツク・イコライザ回路。 2 該第1及び第2の可変抵抗器群は、夫々略同
数の可変抵抗器から構成されてなる実用新案登
録請求の範囲第1項記載のグラフイツク・イコ
ライザ回路。
[Claims for Utility Model Registration] 1. An amplifier for amplifying an input signal, a first fixed terminal connected to the input terminal of the amplifier, a second fixed terminal connected to the output terminal of the amplifier, and a center point tap. a first variable resistor group consisting of a plurality of variable resistors whose terminals are grounded and whose resistance values between the center tap terminal and the first and second fixed terminals are unequal; , a second fixed terminal is connected to the input terminal of the amplifier, a first fixed terminal is connected to the output terminal of the amplifier, and the center tap terminal is grounded, and the center tap terminal and the first fixed terminal are connected to each other. , a second variable resistor group consisting of a plurality of variable resistors having unequal resistance values between them and the second fixed terminal, and the first and second variable resistors that are slidable independently of each other. A plurality of resonant circuits each connected to each slider of the resistor group and having mutually different resonant frequencies in order to control the level of the input signal for each of the plurality of divided frequency bands. The constructed graphic equalizer circuit. 2. The graphic equalizer circuit according to claim 1, wherein the first and second variable resistor groups each include substantially the same number of variable resistors.
JP9453381U 1981-06-25 1981-06-25 Graphic equalizer circuit Granted JPS58516U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9453381U JPS58516U (en) 1981-06-25 1981-06-25 Graphic equalizer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9453381U JPS58516U (en) 1981-06-25 1981-06-25 Graphic equalizer circuit

Publications (2)

Publication Number Publication Date
JPS58516U JPS58516U (en) 1983-01-05
JPS6342594Y2 true JPS6342594Y2 (en) 1988-11-08

Family

ID=29889456

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9453381U Granted JPS58516U (en) 1981-06-25 1981-06-25 Graphic equalizer circuit

Country Status (1)

Country Link
JP (1) JPS58516U (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6091706A (en) * 1983-10-25 1985-05-23 Rohm Co Ltd Amplifier circuit
JPS6340409U (en) * 1986-09-01 1988-03-16
JPH0727690Y2 (en) * 1992-04-22 1995-06-21 日本コロムビア株式会社 Frequency characteristic adjustment circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5721689A (en) * 1980-07-15 1982-02-04 Matsushita Electric Works Ltd Heat insulated window frame material

Also Published As

Publication number Publication date
JPS58516U (en) 1983-01-05

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