JPS5914371A - Controller for inverter - Google Patents

Abstract

PURPOSE:To improve the economy and accuracy of an inverter by composing to logically pattern a unit waveform of 15 deg. period with 6 bits to form a unit waveform of 15 deg. in 180 deg. period of AC. CONSTITUTION:A bindary up-down counter 14 counts up or down at an every 15 deg. of electric angle. On the other hand, data of unit waveform of 6 bits in one word is stored with 15 deg. of electric angle as a unit in an ROM 15. A sexanary up-down counter 16 decodes data for 180 deg. of electric angle together with a data selector 17. A binary counter 18 is inverted and non-inverted at every 180 deg. together with exclusive OR gate 19 and decodes data of 360 deg. of electric angle. A data latch 20 having inverting function latches data whenever the data of the ROM 15 is altered, and outputs a control signal of unit waveform of 360 deg. of electric angle.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an inverter control device that provides variable voltage and variable frequency outputs.

[Technical background of the invention]

For example, by controlling the rotation speed of an AC motor, especially at a constant tonnage V.
Variable voltage is used when operating the vehicle.

Using a variable frequency power supply, the ratio t of motor terminal voltage to frequency
=7 The motor speed is fully controlled while keeping it constant. In this case, an inverter is the most common variable voltage, variable frequency power source.

FIG. 1 shows the main circuit configuration of a typical conventional open-loop three-phase glitch inverter. In this case, a transistor /' is used as the switching element, and each arm of the three-phase bridge is connected to a transistor y, p Try.
, Trz, Trs, Tr4. Trs, Tr6
A flywheel diode D1 to transistors Tr1 and Tr4 . Tr2 and Trs, Trs
and Tr6 are connected to output terminals TU, Tv,
Tw, and this output terminal TU, TV, TV
A three-phase AC motor as a load is connected to. Power is supplied from the DC power source 2 to the inverter main circuit 1 configured in this manner, and the transistors Tr+ to Tr6t are switched using the pulse width modulation method (hereinafter simply referred to as PWM method), thereby receiving power from the output terminals TU, Tv, and Tw. A three-phase AC output is obtained, and the output frequency can be adjusted by changing the switching period of each transistor Tr1 to Tr4.

FIG. 2 shows the configuration of a conventional inverter control circuit. In FIG. 2, reference numeral 3 denotes a frequency setting circuit that outputs a frequency setting signal 81 for setting the output frequency f of the main circuit 1, and the frequency setting signal 81 is applied to the pattern selector 4 and rate multiplier 5. 6 is an oscillator for generating a clock signal 82 which determines the output frequency f. The rate multiplier 5 is for controlling the output voltage V of the main circuit 1 to have a predetermined ratio relationship with the set frequency f, and changes the entire frequency of the clock signal 82 at a division ratio according to the frequency setting signal 81. Then, a new lock signal Szaf is output. 7 is an n-bit binary counter consisting of a readout circuit that counts the clock signal 52ay output from the rate multiplier 5;
is a ROM (read only memory) which is a storage element that receives the output from the pinary counter 7 and the address designation signal Ssf from the pattern selector 4; All predetermined logical patterns are stored.

In this way, the contents stored in the ROM 8 are stored as the frequency setting signal 8.
1, and the designated storage contents are read out one after another. 9 is the data selector, R
This is to selectively enable one of the 5 bits each from DO to D2 and D4 to D6 of the OMB, and these signals can be input directly or by inverting circuits 10, 11, and 12i.
It is obtained as a control signal via.

On the other hand, the ROM 8 stores a pulse train control signal t obtained by comparing the sine wave 8a and the triangular wave 8b as shown in FIG.
Mo is written.

[Problems with background technology]

The conventional method of storing the control signal Mo is generally to store the signal for 30 degrees of electrical angle (using 6 bits) or for U120' (using 3 bits) in order to simplify the circuit for successively reproducing the memory dice. Met. - For example, FIG. 4 shows a memory element readout circuit for 30° (using 6 bits). This figure 4 shows U, V.

It shows that the W phase is composed of a combination of 30° unit waveforms A, B, and C and their phase-inverted waveforms. Therefore, a control signal gM is applied to the storage element.

In the case where a three-phase control signal is obtained by a readout circuit, the minimum unit is 15° (using 6 bits).

This means that the configurations of 500 minutes (using 6 bits) and 120 degrees (using 3 bits) store extra information, and cannot be said to utilize all of the memory elements effectively.

[Purpose of the invention]

The present invention was developed in view of the above circumstances, and its object is to provide a low-cost inverter control device that can minimize the capacity of storage elements.

[Summary of the invention]

The inverter control device according to the present invention controls the switching elements of the inverter main circuit on and off using a logically patterned control signal to obtain an AC output approximating a sine wave, and has a unit waveform of 15° on a 180° interval By forming the unit waveform of the 15° interval into a logical pattern using 6 bits, as shown in FIG.

EXAMPLE An example of the present invention will be described below with reference to FIGS. 5 to 8.

In FIG. 5, 15 is a rate multiplier for controlling the output voltage V to have a predetermined ratio relationship with the set frequency f. For the sake of simplicity, a process of decoding a control signal of only one phase to obtain a control signal of 560 degrees of electrical angle will be described. 14 is a binary up/down counter, which performs up/down every 15 electrical degrees.

On the other hand, in the ROM 15, unit waveforms A (D° to 15°) and B (30
°~15°), c(so°~45°), o(6o°~4
5°).

Each data of E (60° to 75°) and F (90° to 75°) is stored as shown in FIG. 16 is a hexadecimal up-down counter, which together with a data selector 17 decodes all data for 180 degrees of electrical angle. Next 18 is 2
It is a decimal counter and inverts every 180 degrees along with the exclusive or gate 19. Perform non-inversion and electrical angle 36
Decode all 0° data. 20'Id It is a data latch that also has an inversion function, and latches all the data every time the data in the ROM 15 is changed. In this way, the unit waveforms A (Q° ~ 15°) and -B (15
° ~ 30 °) 9C (50 ° ~ 45 °), -D (45 ° ~
60°), E (60° ~ 75°), -F (75° ~ 90°)
°), F (90° to 75°), -E (75° to 60°)
, o(6, o=~45°), -c(ss°~50°)
, B (30 degrees) is obtained.The symbol "-" on the left side of the alphabetic code indicates down count reading, and the symbol "-" on the upper side of the anosophic alphabetic code indicates inversion.

FIG. 7 shows the process of decoding data for 180 degrees of electrical angle.

Next, the case of obtaining three-phase control signals will be explained. 8th
In the figure, 16 is a rate multiplier, and 14 is a binary up/down counter. Each numeral 21 is a readout control section indicated by a dashed line in FIG. 5, which synthesizes control signals for the -phase.

Since the phase difference between the three-phase control signals is 120°, the initial values of the hexadecimal up-down counter 16 and the binary counter 18 in the readout control unit 21 in FIG.
), the V phase is the hexadecimal up-down counter 16 (down mode 2) and the binary counter 18 (up mode O).
(i.e., leading by 120 degrees in electrical angle), and the W phase presets the hexadecimal up-down counter (up mode 2) and the binary counter 18 (up mode 1) (i.e., delaying by 120 degrees in electrical angle) as the respective values. By doing so, three-phase control signals can be easily obtained. The delay and advance of the phase as described above can be realized by making each of the U-phase, ■-phase, and W-phase counters presettable counters that are automatically loaded when the power is turned on. In this way, ■
Phase (E, -F.

F) control signals are obtained (see FIG. 7). All of the control signals output in this way are shown in Figure 1.
ry, Trz, Trs, Tr4. Trs, T
The output terminals TU and Tv of the inverter main circuit 1 are connected to the input terminal r6.

From Tw, a three-phase sine wave output as shown in FIG. 7 is obtained.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be modified in various ways without departing from the scope of the invention, such as being applicable not only to three-phase inverters but also to single-phase inverters (phase difference changed to 90°). It can be implemented by

〔Effect of the invention〕

The present invention has a configuration in which data corresponding to 15 electrical angles is stored in 6 bits of a memory element, and in the method of decoding data from the memory element to obtain a control signal, the stored information i' can be kept to the minimum necessary, e.g. Compared to the conventional method at 30°, the ROM capacity is half, and the same capacity ROM
Is it an improvement in terms of economy and accuracy, such as doubling the electrical angle resolution when fully used? It is possible to provide an inverter control device that can achieve

[Brief explanation of the drawing]

Fig. 1 is a diagram showing a conventional inverter main circuit, Fig. 2 is a block diagram of a conventional control circuit, Fig. 6 is a diagram showing a method of digitizing an analog signal (sine wave) 'If-,
8) is a diagram showing a conventional decoding method of sine wave quantized data, FIG. 5 is a block diagram for decoding data for one phase according to the present invention, FIG. 6 is a diagram showing a data allocation map of 1dROM, and FIG. 8 is a diagram showing a method for decoding sine wave quantized data according to the present invention, and FIG. 8 is a block diagram for decoding three-phase data according to the present invention. In the figure, 1 is the inverter main circuit, 13 is the rate multiplier, 14 is the binary up/down counter, and 15 is the R
OM (memory element), 16 is a hexadecimal up-down counter,
17 is a data selector, 18 is a binary counter, and 19 is an exclusive OR gate. Figure 1

Claims (1)

[Claims] In an inverter that obtains a sine wave approximation AC output by turning on and off all the switching elements in the main circuit of the inverter using a control signal of a predetermined pattern, the control signal is formed entirely by a logical pattern, and this control signal is A memory element that stores data in bits, a read control unit that controls reading of the memory contents of this memory element, and
This readout control section includes an up-down counter that alternately reads out the stored contents of the storage element in the forward and reverse directions, and three independent six-way counters that convert the read contents into three-phase outputs with a phase difference of 120 degrees. Binary reset tab μ up-down counter and data selector and three independent binary reset tabs for converting 180° data to 360° data
Jig or gate and pushing device.