JPH04372934A - Manufacture of array substrate for liquid crystal display device - Google Patents
Manufacture of array substrate for liquid crystal display deviceInfo
- Publication number
- JPH04372934A JPH04372934A JP3150798A JP15079891A JPH04372934A JP H04372934 A JPH04372934 A JP H04372934A JP 3150798 A JP3150798 A JP 3150798A JP 15079891 A JP15079891 A JP 15079891A JP H04372934 A JPH04372934 A JP H04372934A
- Authority
- JP
- Japan
- Prior art keywords
- film
- molybdenum
- acid
- scanning line
- liquid crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Liquid Crystal (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】この発明は、液晶表示装置用アレ
イ基板の製造方法に関し、特に走査線の形成方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an array substrate for a liquid crystal display device, and more particularly to a method for forming scanning lines.
【0002】0002
【従来の技術】薄膜トランジスタ(TFT)アレイは、
アクティブマトリックス型液晶表示素子に適用され、コ
ントラスト比の高さ、応答速度の点で他の液晶表示素子
に比べ格段に優れ、平面型表示装置の本命と目され脚光
を浴びている。また、TFTアレイの半導体材料として
、アモルファスシリコン(a−Si)が多く用いられて
いるが、構造的にゲート電極上にゲート絶縁層を設け、
その上に半導体層、ソース・ドレイン電極を設けたいわ
ゆる逆スタガード型が採用されることが多い。[Prior Art] A thin film transistor (TFT) array is
Applied to active matrix type liquid crystal display elements, it is much superior to other liquid crystal display elements in terms of high contrast ratio and response speed, and is attracting attention as it is seen as the favorite for flat panel display devices. In addition, amorphous silicon (a-Si) is often used as a semiconductor material for TFT arrays, but structurally, a gate insulating layer is provided on the gate electrode.
A so-called reverse staggered type is often adopted in which a semiconductor layer and source/drain electrodes are provided on top of the semiconductor layer.
【0003】図3は逆スタガード型のTFTアレイの要
部を示す断面図である。図3において、ガラス基板1上
には、例えばモリブデン・タンタル(MoTa)合金か
らなるゲート電極2及びこれと一体の走査線がパターン
形成されている。次に、ゲート絶縁膜3,4、a−Si
膜5、保護膜6が積層されてパターニングされた後、低
抵抗アモルファスシリコン(n+ a−Si)膜7が形
成されている。続いて、ITO(インジウム錫酸化膜)
からなる表示電極8が形成されている。その後、信号線
と一体のドレイン電極9、及びソース電極10がパター
ン形成され、TFTアレイが完成する。FIG. 3 is a sectional view showing the main parts of an inverted staggered TFT array. In FIG. 3, a gate electrode 2 made of, for example, a molybdenum tantalum (MoTa) alloy and a scanning line integrated therewith are patterned on a glass substrate 1. Next, gate insulating films 3, 4, a-Si
After the film 5 and the protective film 6 are laminated and patterned, a low resistance amorphous silicon (n+ a-Si) film 7 is formed. Next, ITO (indium tin oxide film)
A display electrode 8 is formed. Thereafter, a drain electrode 9 and a source electrode 10 integrated with the signal line are patterned to complete the TFT array.
【0004】0004
【発明が解決しようとする課題】液晶表示装置の表示部
分が大画面化或いは高精細化されるに伴い、走査線が長
くなることや、画素の開口率をほぼ一定にするため走査
線の幅が細くなることに起因して、走査線抵抗の高抵抗
化が起こる。この結果、走査信号の波形が歪み、信号の
伝搬遅延が起こる。このことが画像の不均一化となって
現れ、画質低下を招くことになる。そこで、走査線抵抗
を低抵抗化する必要がある。走査線抵抗値は、対角14
インチ画面サイズで画素数800×1000(走査線数
800本)のときに、シミュレーションによると約0.
3Ω/□以下としなければならない。低抵抗金属である
アルミニウム(Al)を走査線材料に使用すればよいが
、単独で用いると製造工程中の熱処理工程にてヒロック
を生じ、走査線と信号線の層間絶縁性を大きく悪くする
問題がある。また、逆スタガード型TFTでは、ゲート
上に各種の膜が形成され、それらの膜からなる配線等の
段差部での段切れ防止用にテーパー形状とすることが望
ましい。従来のゲート電極はMoTaを成膜後、ドライ
エッチングでパターンを形成しているが、テーパーを形
成するためにガス条件、ガス圧等に工夫を要する。[Problems to be Solved by the Invention] As the display portion of a liquid crystal display device becomes larger or has higher definition, the scanning line becomes longer, and the width of the scanning line increases in order to keep the aperture ratio of the pixel almost constant. Due to the thinning of the scanning line, the resistance of the scanning line increases. As a result, the waveform of the scanning signal is distorted, causing a signal propagation delay. This appears as non-uniformity of the image, leading to a reduction in image quality. Therefore, it is necessary to reduce the resistance of the scanning line. The scanning line resistance value is diagonal 14
According to simulations, when the screen size is 800 x 1000 pixels (800 scanning lines), approximately 0.
Must be 3Ω/□ or less. Aluminum (Al), which is a low-resistance metal, can be used as the scanning line material, but if it is used alone, hillocks will occur during the heat treatment process during the manufacturing process, which will greatly deteriorate the interlayer insulation between the scanning line and the signal line. There is. In addition, in an inverted staggered TFT, various films are formed on the gate, and it is desirable that the film is tapered to prevent breakage at a step portion such as a wiring made of these films. In the conventional gate electrode, a pattern is formed by dry etching after forming a MoTa film, but in order to form a taper, it is necessary to devise gas conditions, gas pressure, etc.
【0005】[0005]
【課題を解決するための手段】この発明は、絶縁性基板
上に走査線と信号線をマトリクス状に形成し、この交点
にTFT及び表示電極を配置してなる液晶表示装置用ア
レイ基板の製造方法についてのものであり、走査線を形
成する際に、Al金属とモリブデン(Mo)金属を順次
積層し、燐酸、酢酸及び硝酸の混酸でエッチング加工し
た後に、上層のMo金属を除去する工程を備えている。
更に、この工程において、上層のMo金属を除去した後
、Al金属上を他の金属例えばMoTa合金、タンタル
(Ta)金属、チタン(Ti)金属及びクロム(Cr)
金属等で被覆してもよい。[Means for Solving the Problems] The present invention manufactures an array substrate for a liquid crystal display device in which scanning lines and signal lines are formed in a matrix on an insulating substrate, and TFTs and display electrodes are arranged at the intersections of the scanning lines and signal lines. This is about a method in which, when forming a scanning line, Al metal and molybdenum (Mo) metal are sequentially laminated, etched with a mixed acid of phosphoric acid, acetic acid, and nitric acid, and then the upper layer of Mo metal is removed. We are prepared. Further, in this step, after removing the upper layer Mo metal, other metals such as MoTa alloy, tantalum (Ta) metal, titanium (Ti) metal, and chromium (Cr) are applied on the Al metal.
It may be coated with metal or the like.
【0006】[0006]
【作用】この発明において、テーパー加工については、
例えば燐酸、酢酸及び硝酸の混酸で、AlよりもMoの
エッチングレートが大きくなる混合比率の液を用いれば
可能である。その後、Mo酸化膜による膜はがれ防止の
ために、Moのみエッチングを行い、Alのみの走査線
にして、低抵抗の配線を形成することができる。更に、
このAl上に他の金属(MoTa、Ta等)を積層する
と、ヒロック防止や耐薬品処理を図ることができる。こ
のように形成したアレイ基板は、層間絶縁性について全
く問題なく且つ他の金属がAl上に存在するためにAl
のヒロックが起こらないことから、走査線と信号線等の
層間の短絡は起こらない。また、Alの膜厚を200n
m、他の金属例えばMoTaの膜厚を100nmとした
とき、配線抵抗はMoTa膜厚300nmのときの約9
分の1となり、低抵抗化を図ることができる。[Operation] In this invention, regarding taper processing,
For example, this is possible by using a mixed acid solution of phosphoric acid, acetic acid, and nitric acid with a mixing ratio such that the etching rate of Mo is higher than that of Al. Thereafter, in order to prevent the Mo oxide film from peeling off, only Mo is etched, and the scan line is made only of Al, thereby making it possible to form a low-resistance wiring. Furthermore,
By layering other metals (MoTa, Ta, etc.) on this Al, hillock prevention and chemical resistance treatment can be achieved. The array substrate formed in this way has no problem with interlayer insulation, and since other metals are present on Al, Al
Because hillocks do not occur, short circuits between layers such as scanning lines and signal lines do not occur. In addition, the Al film thickness was set to 200n.
m, when the film thickness of other metals such as MoTa is 100 nm, the wiring resistance is about 9 when the MoTa film thickness is 300 nm.
The resistance is reduced to 1/1, and the resistance can be lowered.
【0007】[0007]
【実施例】以下、この発明の詳細を図面を参照して説明
する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be explained below with reference to the drawings.
【0008】図1はこの発明の一実施例を用いたアクテ
ィブマトリクス型液晶表示装置の等価回路図である。図
1において、絶縁性基板21上に、走査線22と信号線
23がマトリクス状に配設されている。そして、走査線
22と信号線23の交差部に、a−Si膜を有するTF
T24が形成されている。更に、TFT24のドレイン
は信号線23に接続され、ゲートは走査線22に接続さ
れている。また、TFT24のソースには、各画素の表
示電極25と液晶容量26及び補助容量27が接続され
ている。FIG. 1 is an equivalent circuit diagram of an active matrix liquid crystal display device using an embodiment of the present invention. In FIG. 1, scanning lines 22 and signal lines 23 are arranged in a matrix on an insulating substrate 21. As shown in FIG. A TF having an a-Si film is provided at the intersection of the scanning line 22 and the signal line 23.
T24 is formed. Further, the drain of the TFT 24 is connected to the signal line 23, and the gate is connected to the scanning line 22. Furthermore, a display electrode 25 of each pixel, a liquid crystal capacitor 26, and an auxiliary capacitor 27 are connected to the source of the TFT 24.
【0009】図2はこの実施例におけるTFT部の製造
工程を示す断面図であり、図1と対応する部分には同一
の符号を付してある。図2において、製造工程に従って
説明する。まず、図2(a)に示すように、例えばプラ
ズマCVD法によるSiOx 膜付きガラスからなる絶
縁性基板21上に、スパッタ法により、Al膜31を2
00nm堆積させる。このとき、Al膜31はAl合金
例えばCu1原子%、Si0.5原子%含むAl膜でも
可能である。次に、このAl膜31上に、Mo膜32を
スパッタ法により50nm堆積させる。続いて、この積
層膜上に、フォトリソグラフィを用いてゲート電極を含
む走査線パターンを形成し、燐酸+硝酸+酢酸の混酸を
用いてAl/Mo積層膜のエッチングを行い、走査線パ
ターンを作製する。このとき、エッチング時にエッチン
グレートの差からMoにサイドエッチが入り、なだらか
なテーパーを形成する。次に、燐酸+硝酸+酢酸のMo
のみエッチングする比率の混酸を用いて、図2(b)に
示すように、Mo膜32のみ除去する。続いて、Al膜
31上にMoTa膜33をスパッタ法により50nm堆
積させる。次に、MoTa膜33のエッチングを行い、
Al膜31とMoTa膜33からなる走査線パターンを
作製する。FIG. 2 is a sectional view showing the manufacturing process of the TFT section in this embodiment, and parts corresponding to those in FIG. 1 are given the same reference numerals. Referring to FIG. 2, the manufacturing process will be explained. First, as shown in FIG. 2A, two Al films 31 are deposited by sputtering on an insulating substrate 21 made of glass with a SiOx film formed by plasma CVD, for example.
Deposit 00 nm. At this time, the Al film 31 may be an Al alloy, for example, an Al film containing 1 atomic % of Cu and 0.5 atomic % of Si. Next, on this Al film 31, a Mo film 32 is deposited to a thickness of 50 nm by sputtering. Next, a scanning line pattern including a gate electrode was formed on this laminated film using photolithography, and the Al/Mo laminated film was etched using a mixed acid of phosphoric acid + nitric acid + acetic acid to create a scanning line pattern. do. At this time, side etching occurs in Mo due to the difference in etching rate during etching, forming a gentle taper. Next, Mo of phosphoric acid + nitric acid + acetic acid
As shown in FIG. 2B, only the Mo film 32 is removed using a mixed acid at a ratio that etches only the Mo film 32. Subsequently, a MoTa film 33 is deposited to a thickness of 50 nm on the Al film 31 by sputtering. Next, the MoTa film 33 is etched,
A scanning line pattern consisting of an Al film 31 and a MoTa film 33 is produced.
【0010】続いて、図2(c)に示すように、プラズ
マCVD法によりSiOx 膜34、SiNx 膜35
、a−Si膜36及びSiNx 膜37を連続堆積させ
る。次に、上層のSiNx 膜37をパターニングし、
前処理後に、ソ―ス・ドレイン電極のコンタクトとして
n+ a−Si膜38をプラズマCVD法により堆積さ
せる。次に、a−Si膜36をパターニングし、例えば
ITO膜からなる表示電極25を形成する。続いて、走
査線22のパッド部(図示せず)の開口を、HF系エッ
チング液で行う。次に、スパッタ法によりAlを堆積さ
せ、これを図1に示す信号線23、及びソ―ス電極39
とドレイン電極40として形成する。この後、RIE(
Reactive Ion Etching)により、
a−Si膜36のチャネル部と対向するn+ a−Si
膜38を除去し、液晶表示装置用アレイ基板が完成する
。Subsequently, as shown in FIG. 2(c), an SiOx film 34 and a SiNx film 35 are formed by plasma CVD.
, an a-Si film 36 and a SiNx film 37 are successively deposited. Next, the upper layer SiNx film 37 is patterned,
After the pretreatment, an n+ a-Si film 38 is deposited as a source/drain electrode contact by plasma CVD. Next, the a-Si film 36 is patterned to form a display electrode 25 made of, for example, an ITO film. Subsequently, openings in the pad portions (not shown) of the scanning lines 22 are made using an HF-based etching solution. Next, Al is deposited by sputtering, and this is applied to the signal line 23 and source electrode 39 shown in FIG.
and is formed as the drain electrode 40. After this, RIE (
Reactive Ion Etching)
n+ a-Si facing the channel part of the a-Si film 36
The film 38 is removed, and an array substrate for a liquid crystal display device is completed.
【0011】この実施例において、走査線抵抗は、平均
走査線幅を30μm、走査線長を20cmとしたときに
、約1kΩとなり、これと同じ配線幅・配線長で膜厚3
000オングストロームのMoTa膜からなる走査線抵
抗は約9kΩとなるので、走査線抵抗を従来に比べ1/
9に低減することができた。また、Al膜31とMo膜
32のエッチング選択比の高い燐酸+硝酸+酢酸の混酸
からなるエッチング液を用いることにより、走査線とし
てのAl膜31のなだらかなテーパー加工が可能である
。更に、Al膜31上をMoTa膜33で保護すること
により、熱処理により発生するAlのヒロックを防ぐこ
とができた。また、Al膜31上にMoTa膜33を形
成することにより、走査線形成以降の工程において、従
来より用いられていたMoTaプロセスを採用すること
ができた。In this example, the scanning line resistance is approximately 1 kΩ when the average scanning line width is 30 μm and the scanning line length is 20 cm, and with the same wiring width and length, the film thickness is 3.
The resistance of the scanning line made of 000 angstrom MoTa film is approximately 9kΩ, so the resistance of the scanning line is 1/1 compared to the conventional one.
We were able to reduce this to 9. Further, by using an etching solution made of a mixed acid of phosphoric acid, nitric acid, and acetic acid that has a high etching selectivity between the Al film 31 and the Mo film 32, it is possible to gently taper the Al film 31 as a scanning line. Furthermore, by protecting the Al film 31 with the MoTa film 33, it was possible to prevent Al hillocks caused by heat treatment. Furthermore, by forming the MoTa film 33 on the Al film 31, the conventionally used MoTa process could be employed in the steps after forming the scanning lines.
【0012】0012
【発明の効果】この発明は、Al金属とMo金属を順次
積層し、燐酸、酢酸及び硝酸の混酸でエッチング加工し
た後に、上層のMo金属を除去する工程を備えることに
より、走査線抵抗は低抵抗化され、層間絶縁性が優れ、
容易にテーパーの形成を可能にするので、液晶表示装置
の大画面化・高精細化を図ることが可能となる。Effects of the Invention The present invention has a step of sequentially laminating Al metal and Mo metal, etching with a mixed acid of phosphoric acid, acetic acid, and nitric acid, and then removing the upper layer of Mo metal, thereby achieving low scanning line resistance. It is resistive and has excellent interlayer insulation.
Since a taper can be easily formed, it is possible to increase the screen size and high definition of a liquid crystal display device.
【図1】この発明の一実施例を用いたアクティブマトリ
クス型液晶表示装置の等価回路図である。FIG. 1 is an equivalent circuit diagram of an active matrix liquid crystal display device using an embodiment of the present invention.
【図2】この発明の一実施例におけるTFT部の製造工
程を示す断面図である。FIG. 2 is a cross-sectional view showing the manufacturing process of a TFT section in an embodiment of the present invention.
【図3】従来のTFTアレイの要部を示す断面図である
。FIG. 3 is a cross-sectional view showing essential parts of a conventional TFT array.
21……絶縁性基板 22……走査線 23……信号線 24……TFT 25……表示電極 31……Al膜 32……Mo膜 21...Insulating substrate 22...scanning line 23...Signal line 24...TFT 25...Display electrode 31...Al film 32...Mo film
Claims (1)
リクス状に形成し、この交点に薄膜トランジスタ及び表
示電極を配置してなる液晶表示装置用アレイ基板の製造
方法において、アルミニウム金属とモリブデン金属を順
次積層し、燐酸、酢酸及び硝酸の混酸でエッチング加工
した後に、上層の前記モリブデン金属を除去する工程を
備えることを特徴とする液晶表示装置用アレイ基板の製
造方法。1. A method for manufacturing an array substrate for a liquid crystal display device, in which scanning lines and signal lines are formed in a matrix on an insulating substrate, and thin film transistors and display electrodes are arranged at the intersections of the scanning lines and signal lines. 1. A method for manufacturing an array substrate for a liquid crystal display device, comprising a step of successively stacking the molybdenum metal on the upper layer after etching with a mixed acid of phosphoric acid, acetic acid, and nitric acid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3150798A JPH04372934A (en) | 1991-06-24 | 1991-06-24 | Manufacture of array substrate for liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3150798A JPH04372934A (en) | 1991-06-24 | 1991-06-24 | Manufacture of array substrate for liquid crystal display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04372934A true JPH04372934A (en) | 1992-12-25 |
Family
ID=15504665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3150798A Pending JPH04372934A (en) | 1991-06-24 | 1991-06-24 | Manufacture of array substrate for liquid crystal display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04372934A (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5811835A (en) * | 1995-08-23 | 1998-09-22 | Kabushiki Kaisha Toshiba | Thin-film transistor with edge inclined gates and liquid crystal display device furnished with the same |
| KR20010003446A (en) * | 1999-06-23 | 2001-01-15 | 김영환 | Method for forming data line of liquid crystal display device |
| KR100315648B1 (en) * | 2000-01-21 | 2001-11-29 | 정지완 | Gate electrode etching liquid in LCD display system |
| US6541389B1 (en) * | 1998-12-22 | 2003-04-01 | Kabushiki Kaisha Toshiba | Method of patterning a thin layer by chemical etching |
| KR100426746B1 (en) * | 1994-11-18 | 2004-07-05 | 가부시끼가이샤 히다치 세이사꾸쇼 | Active Matrix Liquid Crystal Display |
| KR100455640B1 (en) * | 1996-06-07 | 2005-01-17 | 루센트 테크놀러지스 인크 | Method for producing tapered lines |
| JP2005165300A (en) * | 2003-11-14 | 2005-06-23 | Semiconductor Energy Lab Co Ltd | Method for manufacturing liquid crystal display device |
| US7173683B2 (en) * | 1997-11-20 | 2007-02-06 | Samsung Electronics Co., Ltd. | Wire for liquid crystal displays, liquid crystal displays having the same, and manufacturing methods thereof |
| KR101030056B1 (en) * | 2003-11-14 | 2011-04-21 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Liquid Crystal Display Manufacturing Method |
| US7995167B2 (en) | 2006-10-18 | 2011-08-09 | Sharp Kabushiki Kaisha | Liquid crystal display device and method for manufacturing liquid crystal display device |
| US8289461B2 (en) | 2007-01-24 | 2012-10-16 | Sharp Kabushiki Kaisha | Liquid crystal display device |
| US8384860B2 (en) | 2007-06-26 | 2013-02-26 | Sharp Kabushiki Kaisha | Liquid crystal display device and method of manufacturing liquid crystal display device |
| US8421967B2 (en) | 2006-12-14 | 2013-04-16 | Sharp Kabushiki Kaisha | Liquid crystal display device and process for producing liquid crystal display device |
| US8659726B2 (en) | 2007-04-13 | 2014-02-25 | Sharp Kabushiki Kaisha | Liquid crystal display and method of manufacturing liquid crystal display |
-
1991
- 1991-06-24 JP JP3150798A patent/JPH04372934A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100426746B1 (en) * | 1994-11-18 | 2004-07-05 | 가부시끼가이샤 히다치 세이사꾸쇼 | Active Matrix Liquid Crystal Display |
| US6235561B1 (en) | 1995-08-23 | 2001-05-22 | Kabushiki Kaisha Toshiba | Method of manufacturing thin-film transistors |
| US5811835A (en) * | 1995-08-23 | 1998-09-22 | Kabushiki Kaisha Toshiba | Thin-film transistor with edge inclined gates and liquid crystal display device furnished with the same |
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| US8421967B2 (en) | 2006-12-14 | 2013-04-16 | Sharp Kabushiki Kaisha | Liquid crystal display device and process for producing liquid crystal display device |
| US8289461B2 (en) | 2007-01-24 | 2012-10-16 | Sharp Kabushiki Kaisha | Liquid crystal display device |
| US8659726B2 (en) | 2007-04-13 | 2014-02-25 | Sharp Kabushiki Kaisha | Liquid crystal display and method of manufacturing liquid crystal display |
| US8384860B2 (en) | 2007-06-26 | 2013-02-26 | Sharp Kabushiki Kaisha | Liquid crystal display device and method of manufacturing liquid crystal display device |
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