JP7821313B2 - Protection circuit and protection method - Google Patents

Description

The present invention relates to a protection circuit and a protection method.

Since the IGBT (Insulated Gate Bipolar Transistor) was introduced as a power semiconductor element for power conversion devices to replace the GTO (Gate Turn Off Thyristor), development has progressed, with higher voltage resistance and lower loss.

In recent years, multi-gate IGBTs have been devised and are being developed as a technology for reducing IGBT losses. Multi-gate IGBTs have auxiliary gate electrodes that control the carrier concentration inside the IGBT, and by switching the auxiliary gate electrodes on and off, they reduce losses when the current is interrupted (when the IGBT is turned off). Specifically, when the IGBT is on, i.e., when there is conduction between the collector and emitter, all gate electrodes are turned on to supply sufficient carriers (charge) within the IGBT, lowering the conduction resistance and reducing conduction losses. When the current is turned off, the auxiliary gate electrodes are turned off a certain amount of time before turn-off, reducing the carriers accumulated in the IGBT and reducing turn-off losses.

As mentioned above, driving a multi-gate IGBT requires providing the IGBT with a gate command signal having multiple on/off pulse patterns. The gate command signal is typically generated by a host controller, and the command signal from this controller is input to a buffer amplifier (hereinafter referred to as a "gate driver") connected to the gate of the IGBT, controlling the gate electrode of the IGBT and driving the IGBT. Because multi-gate IGBTs require multiple gate command signals as described above, the host controller must also be reconfigured to have multiple outputs to accommodate this, making it difficult to maintain compatibility with conventional systems. To address this issue, Patent Document 1 (Patent Document 1) discloses a gate driver for multi-gate IGBTs that is compatible with conventional controllers. According to Patent Document 1, the gate driver generates multiple gate command signals without changing the controller, making it possible to connect multi-gate IGBTs to conventional controllers.

JP 2019-103286 A

According to the technique described in Patent Document 1, the multi-gate IGBT operates with a fixed delay in response to the gate drive signal input from a host controller. If an abnormality occurs in the power conversion device configured with the multi-gate IGBT, the host controller detects this and turns off the gate drive signal to shut down the power conversion device. However, with the gate driver described in Patent Document 1, even if the gate drive command signal is stopped in an emergency, the gate driver operates with a fixed delay in response to the gate drive command, which delays protective shutdown, potentially damaging the multi-gate IGBT during this time.

The present invention solves the above problems and provides technology that can maintain the safety of systems that use multi-gate IGBTs.

In order to solve the above problem, a representative protection circuit of the present invention is a protection circuit used in a power conversion device that includes a drive circuit including a delay unit that receives at least one pulse-width modulated command signal and outputs a delayed signal obtained by delaying the command signal by a predetermined delay time, and a semiconductor circuit having at least one circuit element to which the signal output from the drive circuit is input, and is characterized in that it outputs a cut-off determination signal for cutting off the output of the semiconductor circuit, and is connected to the drive circuit so that the cut-off determination signal is input without passing through the delay unit.

According to the present invention, the safety of a system using a multi-gate IGBT can be maintained.
Problems, configurations, and effects other than those described above will become apparent from the following description of the preferred embodiments.

FIG. 1 is a diagram showing a power conversion device in which a protection circuit according to a first embodiment is used. FIG. 2 is a timing chart showing the power conversion device in normal operation. FIG. 3 is a timing chart showing a normal operation when the period T during which the command signal is on is shorter than the delay time d. FIG. 4 is a timing chart showing a case where an abnormality is detected in the power conversion device. FIG. 5 is a diagram showing a power conversion device in which a protection circuit according to the second embodiment is used. FIG. 6 is a timing chart of the power conversion device according to the second embodiment. FIG. 7 is a timing chart of a power conversion device as a comparative example.

Below, an embodiment of the present invention is described with reference to the drawings.

In the present disclosure, a state in which there is a signal on a signal line or a state in which a signal is input to a terminal is referred to as ON (hereinafter referred to as "ON"), and a state in which there is no signal on a signal line or a state in which no signal is input to a terminal is referred to as OFF (hereinafter referred to as "OFF"). An ON state is also represented as "Hi" or "H", and an OFF state is also represented as "Lo" or "L". For example, the OFF state can be represented as 0 V, and the ON state can be represented as a state in which a voltage is applied. However, it is not limited to 0 V, and a reference potential can also be used. Also, a current can be applied instead of a voltage.
Furthermore, when A and B are "connected," this means that a signal output from A (or B) is input to B (or A). A or B is a component of a circuit or a terminal of a circuit element.

[First embodiment]
(composition)
1 is a diagram illustrating a power conversion device using a protection circuit according to a first embodiment. The power conversion device 600 using the protection circuit 002 includes a drive circuit (hereinafter also referred to as a "gate driver") 400 including a delay unit 103 that receives at least one pulse-width-modulated command signal A, B, or C and outputs a delayed signal obtained by delaying the command signal by a predetermined delay time, and a semiconductor circuit 500 having at least one circuit element 112 that receives the signal output from the drive circuit 400. The protection circuit 002 outputs a shutdown determination signal D that shuts down the output of the semiconductor circuit 500, and is connected to the drive circuit 400 so that the shutdown determination signal D is input without passing through the delay unit 103. The configuration of the power conversion device 600 will be described below.

The host controller 001 outputs at least one pulse-width modulated (PWM) command signal. The figure shows the generation of three command signals: A, B, and C. Command signal A is input to photocoupler 101 and protection circuit 002 via signal line 003 and fed back to the host controller 001 via signal line 004. Photocoupler 101 provides insulation between the host controller 001 and gate driver 400 and transmits command signal A output from the host controller 001 to the gate driver 400. Similarly, command signal B is input to photocoupler 201 and protection circuit 002 via signal line 005 and fed back to the host controller 001 via signal line 006. Command signal C is input to photocoupler 301 and protection circuit 002 via signal line 007 and fed back to the host controller 001 via signal line 008.

Here, photocoupler 101 receives command signal A output from host controller 001, which is then input to input terminal 104b of logical product unit 104 and delay unit 103. While a configuration is shown in which command signal A is input to gate driver 400 via photocoupler 101, photocoupler 101 may be omitted, and host controller 001 may input command signal A to input terminal 104b of logical product unit 104 and delay unit 103. Similarly, photocouplers 201 and 301 may also be omitted, just like photocoupler 101.

The protection circuit 002 includes a first receiving unit 002a that receives command signals A, B, and C output from the host controller 001, a signal output unit 002b that outputs a shutdown determination signal D to the photocoupler 102, and a second receiving unit 002c that receives the shutdown determination signal D. The protection circuit 002 receives the command signals A, B, and C output from the host controller 001. If all of the command signals A, B, and C remain off for a predetermined period of time, the protection circuit 002 determines that an abnormality has occurred and switches the state of the shutdown determination signal D to stop the output of the semiconductor circuit 500. The protection circuit 002 is connected to the gate driver 400 so that the shutdown determination signal D is input without passing through the delay unit 103, and the shutdown determination signal D is used to shut off the output of the delayed signal output from the gate driver 400. The cutoff determination signal D is input to the photocouplers 102 , 202 , and 302 connected in a daisy chain via a signal line 009 , and is fed back to the protection circuit 002 via a signal line 010 .

Here, photocoupler 102 receives the shutdown determination signal D output from protection circuit 002, which is input to input terminal 105b of logical product unit 105 and input terminal 106b of logical product unit 106. While a configuration is shown in which shutdown determination signal D is input to gate driver 400 via photocoupler 102, photocoupler 102 may be omitted, and protection circuit 002 may input shutdown determination signal D to input terminal 105b of logical product unit 105 and input terminal 106b of logical product unit 106. Similarly, photocouplers 202 and 302 may also be omitted, just like photocoupler 102.

The gate driver 400 includes a set of circuits including logical product units 104, 105, and 106 and a delay unit 103, and the number of such sets of circuits is the same as the number of circuit elements included in the semiconductor circuit 500. The gate driver 400 receives a command signal via photocouplers 101, 201, and 301, and outputs a delayed signal delayed by a predetermined delay time to drive the downstream semiconductor circuit 500.

Next, the circuits included in the gate driver 400 will be described in detail, with their names and reference symbols assigned. The set of circuits included in the gate driver 400 includes a delay unit 103 that outputs a delayed signal obtained by delaying command signal A by a predetermined delay time; a first AND unit 105 that calculates the logical product of inputs between the first input terminal 105a and the second input terminal 105b and outputs the result from the first output terminal 105c; a second AND unit 106 that calculates the logical product of inputs between the third input terminal 106a and the fourth input terminal 106b and outputs the result from the second output terminal 106c; and a third AND unit 104 that calculates the logical product of inputs between the fifth input terminal 104a and the sixth input terminal 104b and outputs the result from the third output terminal 104c. Similarly, the delay unit 203 and the logical product units 205, 206, and 209 constitute a set of circuits, and the delay unit 303 and the logical product units 305, 306, and 304 constitute a set of circuits.

In terms of the connection relationship, the third output terminal 104c of the third AND unit 104 is connected to the third input terminal 106a of the second AND unit 106. The delay unit 103 is connected to the first input terminal 105a of the first AND unit 105 and the fifth input terminal 104a of the third AND unit 104. The second input terminal 105b of the first AND unit 105 and the fourth input terminal 106b of the second AND unit 106 are connected to the protection circuit 002. The command signal A is input to the sixth input terminal 104b of the third AND unit 104.

The gate driver 400 is controlled by two input signals. The first input signal is a command signal. Command signal A passes through signal line 003 and is input to gate driver 400 via photocoupler 101. Similarly, command signal B passes through signal line 005 and is input to gate driver 400 via photocoupler 201. Command signal C is input to gate driver 400 via photocoupler 301. These command signals are delayed by a predetermined delay time through gate driver 400 and control the gate electrode voltage of the dual-gate IGBT included in semiconductor circuit 500. The second input signal is a shutdown determination signal D. When the power conversion system including host controller 001, gate driver 400, and semiconductor circuit 500 is operating normally, shutdown determination signal D is on, and when the system is operating abnormally, shutdown determination signal D is off. Shutdown determination signal D is input to gate driver 400 via photocouplers 102, 202, and 302. Buffer unit 115 is a circuit element that produces an output when photocoupler 101 emits light and produces no output when it is off. The relationship between buffer unit 115 and photocoupler 101 also holds true between buffer unit 116 and photocoupler 102, buffer unit 215 and photocoupler 201, buffer unit 216 and photocoupler 202, buffer unit 315 and photocoupler 301, and buffer unit 316 and photocoupler 302.

Next, we will explain the circuit elements 112, 212, and 312 included in the semiconductor circuit 500. Circuit element 112 is a multi-gate semiconductor element having a first gate electrode (hereinafter also referred to as a "control terminal") 110 and a second gate electrode 111. A similar structure is also provided in circuit elements 212 and 312. The multi-gate semiconductor element is, for example, a dual IGBT. Multi-gate semiconductor elements 112 and 212 are connected in series between a positive power supply line 011 and a negative power supply line 013 to form an inverter circuit. The input/output line 012 of the inverter circuit is connected to the connection point of the two series-connected multi-gate semiconductor elements. A typical three-phase AC inverter is constructed by connecting three of these two series-connected inverter circuits in parallel to a power supply line. The inverter circuit composed of the above-mentioned multi-gate semiconductor elements 112 and 212 is shown as an example constituting, for example, the U phase of the three phases, and the multi-gate semiconductor element 312 can constitute a dual-gate IGBT on the positive power supply line side of two inverter circuits connected in series for the other phases, for example, the V phase.

Next, we will explain dead time. If command signals A and B for multi-gate semiconductor elements 112 and 212 that make up the inverter circuit are turned on simultaneously, both multi-gate semiconductor elements 112 and 212 will be turned on at the same time, causing a short circuit between positive power line 011 and negative power line 013. Therefore, when one is on, the other must be turned off. If the outputs of command signals A and B are switched simultaneously when switching from on to off, there is a concern that if one is turned off late due to control variations or other reasons, the other may be turned on, resulting in both being turned on simultaneously. For this reason, when switching outputs, a period during which both command signals A and B are turned off, known as dead time, is set. The dead time is set in advance in host controller 001. As described above, command signals A and B are repeatedly turned on and off, with dead time in between.

Command signals A, B, and C are also input to protection circuit 002, and when all of these are turned off, the output of protection circuit 002 is also turned off. Normally, as mentioned above, one of the multi-gate semiconductor elements in the inverter circuit is always outputting except during dead time, and the shutdown determination signal D, which is the output of protection circuit 002, is turned on.

(Timing chart for normal operation)
FIG. 2 is a timing chart showing the power conversion device in normal operation. The charts for command signals A, B, and C show the cases where they are detected on signal lines 003, 005, and 007 in FIG. 1, respectively. The chart for shutdown determination signal D shows the case where it is detected on signal line 009. The chart for delayed signal E shows the case where it is detected on signal line 107. The chart for signal F shows the case where it is detected between the third AND unit 104 and the second AND unit 106. The chart for signal G shows the signal input to the first gate electrode 110 of the multi-gate semiconductor element 112. The chart for signal H shows the signal input to the second gate electrode 111 of the multi-gate semiconductor element 112. Collector current Z is a current flowing from the collector 113 to the emitter 114 of the multi-gate semiconductor element 112. Here, the second gate electrode 111 is a terminal that controls an increase or decrease in the density of carriers accumulated inside the IGBT, and the on/off of the multi-gate semiconductor element, i.e., the flow or cut-off of the collector current Z, is controlled by the first gate electrode 110. For example, when the voltage applied to the first gate electrode 110 of the multi-gate semiconductor element 112 exceeds the dual gate on threshold, the multi-gate semiconductor element 112 is driven, and the collector current Z becomes Hi and a current flows.

At time t1, command signal A turns on, and at time t2, delayed by delay time d, delay signal E flips to on. At this time, due to normal operation, protection circuit 002's shutdown determination signal D is on. Since the output of buffer unit 116 on signal line 108 also turns on, signal E flips to on, and simultaneously signal G output from first AND unit 105 flips to on, turning first gate electrode 110 on. Furthermore, simultaneously with signal E flipping to on, signal F output from third AND unit 104 also turns on, turning signal H output from second AND unit 106 flips to on, turning second gate electrode 111 on. With first gate electrode 110 on, and a carrier density controlled state by second gate electrode 111 is established. As a result, collector current Z becomes Hi in multi-gate semiconductor element 112, and current flows.

The dead time corresponds to the period Td between t3 and t3d. This period Td is set based on the rated voltage and rated current of the multi-gate semiconductor element 112, and is generally in the range of approximately 5 μs to 10 μs.

Next, at time t3, when command signal A turns off, the signal output from buffer unit 115 turns off, and signal F output from third AND unit 104 turns off. As a result, signal H output from second AND unit 106 also turns off, turning second gate electrode 111 off. At time t4, after delay time d has elapsed, signal E output from delay unit 103 turns off, and signal G output from first AND unit 105 turns off. As a result, first gate electrode 110 is also turned off, collector current Z becomes low, and multi-gate semiconductor element 112 is shut off. By turning off second gate electrode 111 before first gate electrode 110 in this way, carriers accumulated in dual-gate IGBT 112 are reduced, reducing losses during current shutoff. This delay time d is set based on the rated voltage and rated current of the applicable multi-gate semiconductor element, and ranges from 5 μs to 100 μs.

In addition, in PWM control, we will explain the case where the period T during which the command signal is on is shorter than the delay time d. Figure 3 shows a timing chart during normal operation when the period T during which the command signal is on is shorter than the delay time d.

In this case, the signal G input to the first gate electrode 110 corresponds to the behavior of the delayed signal E. As in the case shown in Figure 2, the signal G turns on or off with a delay of the delay time d from the command signal output from the upper controller 001 during normal operation.

On the other hand, signal H input to second gate electrode 111 behaves differently from the case shown in Figure 2. During the time period before timing t1a when command signal A falls, the time elapsed since command signal A rose is less than delay time d, so no signal is output from delay unit 103. Furthermore, since command signal A is off after t1a, input terminal 104b of third AND unit 104, which does not pass through delay unit 103, is off. Therefore, signal F output from third AND unit 104 and signal H output from second AND unit 106 remain off, and signal H at second gate electrode 111 is also off. In this way, the present invention can be applied even when period T is shorter than delay time d.

(Timing chart when an abnormality is detected)
Next, a case where the operation of the power conversion device 600 is stopped by the delay determination signal D when an abnormality is detected will be described.

Figure 4 shows a timing chart when an abnormality is detected in the power conversion device. First, when command signal A turns on at time t1, the collector current Z of dual-gate IGBT 112 turns on at time t2, delayed by delay time d, as in the case shown in Figure 2.

Here, the power conversion device 600 has an abnormality detection unit that turns off the output of the host controller 001 when detecting an abnormality in the system. At time t7, when the abnormality detection unit detects some kind of abnormality (e.g., overcurrent, overvoltage, overtemperature, etc.), command signals A, B, and C output from the host controller 001 are all turned off. However, even if command signals A, B, and C are turned off, signal E on signal line 107 of delay unit 103 remains on even after time t7 due to the operation of delay unit 103. Similarly, delay units 203 and 303 also remain on.

In the first embodiment, therefore, the protection circuit 002 determines that an abnormality has occurred in the power conversion device 600 when all command signals output from the host controller 001 are turned off. The protection circuit 002 switches the state of the shutdown determination signal D from on to off. When the shutdown determination signal D is turned off, the photocouplers 102, 202, and 302 are turned off, and the outputs of the buffer units 116, 216, and 316 are turned off. The outputs of the logical product units 105, 106, 205, 206, 305, and 306 are turned off, and the gate voltages of all multi-gate semiconductors are turned off and shut off.

(Actions and Effects)
As described above, in the protection circuit for a power conversion device according to the embodiment, when an abnormality is detected, the collector current of the multi-gate semiconductor device can be cut off without delay, thereby maintaining the safety of the power conversion device as a system using the multi-gate semiconductor device.

In Figure 1, the signal lines from the higher-level controller that are input to protection circuit 002 are paired together, for example, 003 and 004, but this is not limited to this. If signal lines 004, 006, and 008, to which command signals A, B, and C respectively return, are electrically connected, and signal lines 004, 006, and 008 have a common potential, protection circuit 002 only needs to be connected to signal lines 003, 005, and 007 and the ground potential lines for these signals, thereby making it possible to reduce the number of wires in power conversion device 600.

In addition, while the first embodiment uses photocouplers 101, 201, 301, 102, 202, and 302 to ensure insulation between the host controller 001 and the gate driver 400 to which high voltage is applied, this is not limited to this. Similar effects can be achieved with any means that ensures electrical insulation and allows signal transmission, such as optical fiber or a pulse transformer. Furthermore, while the shutdown determination signal D from the protection circuit 002 in Figure 1 is input to a daisy-chain of diodes, it is also possible to provide separate wiring for each photocoupler and transmit signals in parallel.

In the above example, the logic is configured so that the ON state of the shutdown determination signal D represents a normal operating state. This is to create a fail-safe configuration in which, if an optical component with a short lifespan, such as a photocoupler, fails, the shutdown determination signal D automatically turns OFF, shutting down the system. It is also possible to invert the logic configuration so that the OFF state of the shutdown determination signal D represents a normal operating state, and the ON state represents an abnormality detection state.

Furthermore, in the first embodiment, the shutdown determination signal D is input to photocouplers connected in a daisy chain. This is because if an abnormality occurs anywhere in the daisy chain, current will no longer flow through the photocouplers, allowing the system to automatically shut down.

Second Embodiment
The second embodiment differs from the first embodiment in that it determines that an abnormality has occurred in the protection circuit 002 when all of the command signals remain off for a predetermined period of time. Here, the predetermined period is dead time. In the following description, components that are the same as or equivalent to those in the first embodiment are designated by the same reference numerals, and their description will be simplified or omitted.

(composition)
FIG. 5 is a diagram illustrating a power conversion device using a protection circuit according to a second embodiment. As illustrated in FIG. 5, the protection circuit 0021 includes A/D converters 401, 402, and 403, a logical OR unit 404, a timer/counter 405, and a D/A converter 406. The A/D converters 401, 402, and 403 function as a first receiver 0021a that receives a command signal output from the host controller 001. The D/A converter 406 generates a shutdown determination signal D for stopping the output of the multi-gate semiconductor element included in the semiconductor circuit 500. The shutdown determination signal D is output from an output unit 012b to photocouplers 102, 202, and 302 and then fed back to a receiver 0021c.

A/D conversion unit 401 operates to output Hi or Lo depending on the voltage between signal lines 003 and 004, which indicates the on or off state of command signal A. Similarly, A/D conversion unit 402 outputs Hi or Lo based on the voltage between signal lines 005 and 006, and A/D conversion unit 403 outputs Hi or Lo based on the voltage between signal lines 007 and 008.

The digital signals generated in the A/D conversion units 401, 402, and 403 are input to the logical OR unit 404. The logical OR unit 404 outputs a Hi signal if at least one of the signals output from the A/D conversion units contains a Hi signal, and outputs a Lo signal if all of the signals are Lo.

The timer counter 405 is connected to the logical OR unit 404. The timer counter 405 outputs a Lo signal if the period during which the input signal remains Lo is longer than the dead time Td, and outputs a Hi signal otherwise. The D/A conversion unit 406 converts the signal output from the timer counter 405 into an analog signal and outputs it as a shutoff determination signal D.

With this configuration, when any of the command signals A to C is on, or when the command signals A to C include a signal that turns off but the off period is equal to or shorter than the dead time Td, the protection circuit 0021 outputs a Hi signal as the shutoff determination signal D. On the other hand, when the state in which all of the command signals A to C are off continues for longer than the dead time Td, the protection circuit 0021 outputs a Lo signal as the shutoff determination signal D. In this way, the protection circuit 0021 detects abnormalities based on the state of the command signals.

(Timing chart)
Fig. 6 is a timing chart of the power conversion device according to the second embodiment, and Fig. 7 is a timing chart of a power conversion device as a comparative example.

In systems with inverter circuits, as mentioned above, a period known as dead time is provided during which both series-connected elements are off to prevent the series-connected elements from simultaneously turning on and causing a power supply short circuit. Depending on the design of the control commands, this dead time may overlap between the U, V, and W phases, temporarily turning off all command signals. An example is shown in Figure 7. In Figure 7, from time t3 to t3d, command signals A and B are both off due to the dead time, and command signal C is also off. Therefore, at time t3, all multi-gate semiconductor elements are turned off. In the first embodiment, protection circuit 002 operates at this point and shuts off the multi-gate semiconductor elements.

In order to prevent the above-described malfunction from occurring, in the second embodiment, as shown in Figure 6, if the state in which all of the command signals A, B, and C are off continues for longer than the dead time Td, the protection circuit 002 determines that an abnormality has occurred. In Figure 6, between t7 and t7d, the command signals A to C are all off, and this off state continues for longer than the dead time Td. After the state in which all of the command signals are off continues for longer than the dead time Td, the protection circuit 002 switches the state of the shutdown determination signal D from on to off and outputs it, thereby shutting down the power conversion device 600.

(Actions and Effects)
As described above, it is necessary to provide a dead time in a system having an inverter circuit. In the second embodiment, even if there is a dead time, it is possible to determine whether an abnormality has occurred, and the safety of the power conversion device as a system using multi-gate IGBTs can be maintained.

Furthermore, with this configuration, even when applied to an inverter system with a pulse pattern that requires various on/off controls, it is possible to detect abnormalities without false detection and reliably shut down the system, thereby maintaining the safety of the power conversion device as a system using multi-gate IGBTs.

In the above, the protection technology for power conversion devices has been described in the first and second embodiments in which a dual-gate IGBT is applied, but the present invention is not limited to this. It can also be applied to multi-gate IGBTs with three or more gates.

The above describes an embodiment of the present invention, but the present invention is not limited to the above-described embodiment, and various modifications are possible within the scope of the gist of the present invention.

001: Upper controller 002, 0021: Protection circuit 003, 005, 007: Signal line for command signal 004, 006, 008: Signal line for returning command signal 009: Signal line for shut-off determination signal 010: Signal line for returning shut-off determination signal 011: Positive power supply line 012: Input/output line 013: Negative power supply line 101, 201, 301, 102, 202, 302: Photocouplers 103, 203, 303: Delay units for shut-off determination signal 104, 105, 106, 204, 205, 206, 304, 305, 306: Logical product units 107, 207, 307: Signal line for delayed signal 108, 208, 308: signal lines 109, 209, 309 for cutoff determination signals: signal lines 110, 210, 310 on the output side of the logical product unit: first gate electrodes 111, 211, 311: second gate electrodes 112, 212, 312: multi-gate semiconductor elements 113, 213, 313: collector terminals 114, 214, 314: emitter terminals 115, 116, 215, 216, 315, 316: buffer unit 400: gate drivers 401, 402, 403: A/D conversion unit 404: logical sum unit 405: timer counter 406: D/A conversion unit 500: semiconductor circuit 600: power conversion device

Claims (6)

A protection circuit used in a power conversion device including: a drive circuit including a delay unit that receives two or more pulse-width modulated command signals as input and outputs a delay signal obtained by delaying the command signals by a predetermined delay time; and a semiconductor circuit having at least one circuit element to which a signal output from the drive circuit is input,
the protection circuit outputs a cutoff determination signal for cutting off an output of the semiconductor circuit, and is connected to the drive circuit so that the cutoff determination signal is input without passing through the delay unit;
the interruption determination signal is configured to be in an ON state in a normal operating state and in an OFF state in an abnormality detection state, and is switched from the ON state to the OFF state after a state in which all of the command signals are OFF continues for a predetermined period of time;
The protection circuit according to claim 1, wherein when the cutoff determination signal is in an OFF state, the drive circuit and the semiconductor circuit are cut off from each other. The protection circuit of claim 1, wherein the circuit element is a multi-gate semiconductor element having a first control terminal and a second control terminal. The drive circuit
a first AND unit that calculates a logical AND of inputs between a first input terminal and a second input terminal and outputs the logical AND from a first output terminal;
a second AND unit that calculates a logical AND of inputs between a third input terminal and a fourth input terminal and outputs the logical AND from a second output terminal;
a third AND unit that calculates a logical AND of inputs between a fifth input terminal and a sixth input terminal and outputs the logical AND from a third output terminal;
and
the third output terminal of the third AND unit is connected to the third input terminal of the second AND unit;
the delay unit is connected to the first input terminal of the first AND unit and the fifth input terminal of the third AND unit;
the protection circuit is connected to the second input terminal of the first AND unit and the fourth input terminal of the second AND unit;
the command signal is input to the sixth input terminal of the third AND unit;
the first control terminal of the multi-gate semiconductor element is connected to the first output terminal of the first AND section;
3. The protection circuit according to claim 2, wherein the second control terminal of the multi-gate semiconductor element is connected to the second output terminal of the second AND section. The protection circuit includes:
an A/D converter to which the command signal is input;
a logical OR unit connected to the A/D conversion unit, which outputs an output signal of a first logical value when at least one of the command signals is in an ON state, and outputs an output signal of a second logical value when all of the command signals are in an OFF state;
4. The protection circuit according to claim 3 , further comprising: a timer counter connected to the logical sum unit, which switches the shutdown determination signal from an ON state to an OFF state and outputs the shutdown determination signal after a period during which the output signal has the second logical value continues longer than a predetermined period. the command signal is input to the drive circuit via a first photocoupler;
5. The protection circuit according to claim 4, wherein the cutoff determination signal is input to the drive circuit via a second photocoupler. A protection method for a protection circuit used in a power conversion device including: a drive circuit including a delay unit that receives as input at least one pulse-width modulated command signal and outputs a delay signal obtained by delaying the command signal by a predetermined delay time; and a semiconductor circuit having at least one circuit element that receives as input a signal output from the drive circuit,
a cutoff determination step in which the protection circuit outputs a cutoff determination signal for cutting off the output of the semiconductor circuit and inputs the cutoff determination signal to the drive circuit without passing through the delay unit,
the interruption determination signal is configured to be in an ON state in a normal operating state and in an OFF state in an abnormality detection state, and after a state in which all of the command signals are OFF continues for a predetermined period of time or longer, the state is switched from the ON state to the OFF state ;
The protection method, wherein the protection circuit cuts off between the drive circuit and the semiconductor circuit when the cutoff determination signal is in an OFF state.