GB2247113A - A terminal for a multi-layer printed circuit board - Google Patents
A terminal for a multi-layer printed circuit board Download PDFInfo
- Publication number
- GB2247113A GB2247113A GB9117499A GB9117499A GB2247113A GB 2247113 A GB2247113 A GB 2247113A GB 9117499 A GB9117499 A GB 9117499A GB 9117499 A GB9117499 A GB 9117499A GB 2247113 A GB2247113 A GB 2247113A
- Authority
- GB
- United Kingdom
- Prior art keywords
- layer
- board
- multilayer printed
- ivh
- terminal land
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000005476 soldering Methods 0.000 claims abstract description 13
- 239000004020 conductor Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000004806 packaging method and process Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 38
- 238000000034 method Methods 0.000 description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 238000010276 construction Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/114—Pad being close to via, but not surrounding the via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
- H05K2201/09527—Inverse blind vias, i.e. bottoms outwards in multilayer PCB; Blind vias in centre of PCB having opposed bottoms
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
In the multilayer printed board of the present invention, the space for disposing the outer-layer terminal land 11 at a through-hole 8 and the connecting portion between the outer-layer terminal land 11 and the soldering pad 14 for a component 13 to be mounted can completely be eliminated by the sharing of the outer-layer terminal land 11 of the through- hole 8 with the soldering pad 14 of a component 13 to be mounted, thereby to facilitate high-density wiring and packaging. <IMAGE>
Description
A MULTILAYER PRINTED CIRCUIT BOARD
The present invention is related to a multilayer printed circuit board, and particularly to a multilayer printed circuit board having an IVH (International Via Hole).
Such a multilayer printed board has been proposed, which is formed by heating and pressing a plurality of printed boards having a printed circuit formed on one or both sides of a substrate with a prepreg interposed therebetween.
Figures 3 and 4 of the accompanying drawings show the construction when a component to be mounted such as a chip resistor is mounted on the outer-layer terminal land of the IVH connecting the inner and outer layer circuits of a multilayer printed board of this type, which is formed on the outer-layer board.
In Figures 3 and 4, a multilayer printed board 1 is formed by stacking a plurality of inner-layer boards 4 having a circuit conductor 3 formed on one or both sides of a substrate 2 (in the drawing, only one inner-layer board is shown and the other ones are omitted) and an outer-layer board 9 having a circuit conductor 6 formed on one side of a substrate 5 and having formed an IVH 8 connecting the circuit conductor 6 to a circuit conductor 7 formed on the other side (only one outer-layer board 9 is shown and the other one is omitted), with a prepreg 10 being interposed between the inner- and outer-layer boards 4 and 9, and thereafter heating and pressing this.
As to the circuit conductor 3 of the individual inner-layer board 4, a copper-clad laminate is used and the one having the circuit conductor 3 formed by a known method, for instance, etching, is used in the stacking process, and for the outer-layer board 9, after a punching work is applied to a predetermined position of a double-sided copper-clad laminate, a through hole is formed by plating and the circuit conductor 6 is formed by etching. However, the copper foil forming the circuit conductor 7 is left on the whole surface in this process.
In the process of heating and pressing with the prepreg 10 being interposed, the resin of the prepreg 10 in the B stage melts and fills in the through hole of the outer-layer board 9, and flows out from the inner layer portion to the outer layer portion, adheres to the copper foil surface of the outer-layer board 9 and hardens. Such deposited resin is removed by a physical or chemical method in the preliminary treatment when the remaining copper foil on the outer-layer board 9 is etched to form the outer-layer circuit conductor 7.
As described above, the IVH 8 is filled with the resin to the level of the copper foil surface layer of the outer layer.
In addition, a hole is punched in a position at which a through hole is disposed for connecting the circuit conductors 3, 6 and 7 between the layers of each board of the stacked boards after the inner- and outer-layer boards are stacked and processed, and the hole is plated with copper or the like to form the through hole (not shown).
Whereupon, the surface of the filled resin of the IVH 8 is covered with the copper plating (see
Figure 3).
After this, an operation based on the method for forming the outer-layer circuit of a typical through hole substrate is carried out.
Accordingly, the circuit conductor 7 as the outer-layer circuit is formed in the outer-layer board 9, soldering pads 14 of the chip 13 such as a resistor are formed in the outer-layer terminal land 11 of the
IVH 8 through a connecting portion 12, and the chip 13 is mounted between the pads 14.
However, to mount the chip 13 in the multilayer printed board 1, a space for the connecting portion 12 with the soldering pads 14 of the chip component is required in addition to the outer-layer terminal land 11 of the IVH 8, and thus the effectiveness of the high-density wiring and highdensity packaging is impaired in this respect.
The present invention was developed in view of the defect in the conventional multilayer printed board, and seeks to provide a multilayer printed board which can fully exhibit the effectiveness of highdensity wiring and packaging unique to the multilayer printed board.
According to the invention, there is provided a multilayer printed board formed by heating and pressing a plurality of inner-layer boards having a circuit conductor on one or both sides of a substrate and an outer-layer board having a through-hole with a prepreg interposed therebetween, characterised in that the outer-layer terminal land of the IVH formed by the through hole portion of said outer-layer board is shared by the soldering pad for a component to be mounted.
In the multilayer printed board of the present invention, the space for disposing the outer-layer terminal land and the connecting portion between the outer-layer terminal land and the soldering pad for a component to be mounted can be completely eliminated by the sharing of the outer-layer terminal land of the
IVH with the soldering pad of a component to be mounted, thereby to facilitate high-density wiring and packaging.
In order that the invention may be better understood, an embodiment thereof will now be described by way of example only and with reference to the accompanying drawings in which:
Figures 1 and 2 are a schematic plan and sectional views showing an embodiment of the multilayer printed board of the present invention; and
Figures 3 and 4 are explanatory views of a conventional multilayer printed board.
The multilayer printed board 1 shown in
Figures 1 and 2 can be manufactured by a method similar to the individual processes shown in Figures 3 and 4.
And, particularly the position for disposing the IVH 8 of the outer-layer board 9 is previously designed so that it can be shared by the soldering pad 14 of the chip component 13 such as a resistor.
That is, the space within the IVH 8 of the outer-layer board 9 is filled with the molten resin of the prepreg 10 in the B stage in the stacking process of the inner- and outer-layer boards 4 and 9, and the resin surface of the IVH 8 is covered with a plating during the plating process in the process of forming the through hole of the stacked boards after the stacking, so that the outer-layer terminal land 11 of such IVH 8 can be formed so as to be shared by the soldering pad 14 for the chip 13 which is formed in the outer layer of the outer-layer board 9 in the post-process.
Regarding the remaining construction, the same structural elements as Figures 3 and 4 are designated by the same reference numerals and description thereof is omitted.
In addition, as to the strength of the outerlayer terminal land 11 of the IVH 8, as a result of the tensile strength test of the soldering pad 14 without the IVH 8, no remarkable difference in the strength is seen and it has been found that there is no problem in practical use.
As apparent from the above description, in accordance with the multilayer printed board of the present invention, by forming the outer-layer terminal land of the IVH provided in the multilayer board so that it is shared by the soldering pad for mounting a chip component, the space for disposing the outerlayer terminal land and the connecting portion of the land and the soldering pad for component mounting which has so far been required is made unnecessary, and the spaces for wiring and mounting in the unnecessary portion can be provided with a high density or making equipment light, thin, short and small can be facilitated.
Claims (2)
1. A multilayer printed board formed by heating and pressing a plurality of inner-layer boards having a circuit conductor on one or both sides of a substrate and an outer-layer board having a throughhole with a prepreg interposed therebetween, characterised in that the outer-layer terminal land of the IVH formed by the through hole portion of said outer-layer board is shared by the soldering pad for a component to be mounted.
2. A multilayer printed board substantially as hereinbefore described with reference to Figures 1 and 2 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2217908A JPH0499394A (en) | 1990-08-17 | 1990-08-17 | Multilayer printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9117499D0 GB9117499D0 (en) | 1991-09-25 |
| GB2247113A true GB2247113A (en) | 1992-02-19 |
Family
ID=16711637
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9117499A Withdrawn GB2247113A (en) | 1990-08-17 | 1991-08-13 | A terminal for a multi-layer printed circuit board |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH0499394A (en) |
| GB (1) | GB2247113A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6529179B1 (en) * | 1998-07-31 | 2003-03-04 | Kabushiki Kaisha Toshiba | Flat panel display unit |
| EP1209957A3 (en) * | 2000-11-27 | 2003-07-23 | Fujitsu Ten Limited | Substrate structure |
| US8218333B2 (en) | 2008-03-11 | 2012-07-10 | Panasonic Corporation | Printed circuit board and mounting structure for surface mounted device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0183936A1 (en) * | 1984-11-28 | 1986-06-11 | Contraves Ag | Multilayer circuit and method of making the electrical connections |
-
1990
- 1990-08-17 JP JP2217908A patent/JPH0499394A/en active Pending
-
1991
- 1991-08-13 GB GB9117499A patent/GB2247113A/en not_active Withdrawn
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0183936A1 (en) * | 1984-11-28 | 1986-06-11 | Contraves Ag | Multilayer circuit and method of making the electrical connections |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6529179B1 (en) * | 1998-07-31 | 2003-03-04 | Kabushiki Kaisha Toshiba | Flat panel display unit |
| EP1209957A3 (en) * | 2000-11-27 | 2003-07-23 | Fujitsu Ten Limited | Substrate structure |
| US6750537B2 (en) | 2000-11-27 | 2004-06-15 | Fujitsu Ten Limited | Substrate structure |
| US8218333B2 (en) | 2008-03-11 | 2012-07-10 | Panasonic Corporation | Printed circuit board and mounting structure for surface mounted device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0499394A (en) | 1992-03-31 |
| GB9117499D0 (en) | 1991-09-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |