DE102014103042B4 - Image sensor - Google Patents

Abstract

Image sensor (100) comprising:
a first photoelectric conversion element (40-1) configured to provide photocharges to a first charge storage node (CSN1);
a first charge storage element (MCAP1) different from the first charge storage node (CSN1) and configured to store an amount of charge to cancel at least a portion of the charge stored in the first charge storage node in response to a feedback signal (FBA, FBB);
a feedback signal generating circuit (38A, 38B) configured to generate the feedback signal (FBA, FBB) based on an amount of charge in the first charge storage node (CSN1);
a first switch (PTR1) configured to switch the supply of charges from a charge supply source to the first charge storage element (MCAP1); and
a second switch (ITR1) configured to switch the supply of the charges stored in the first charge storage element (MCAP1) to the first charge storage node (CSN1),
wherein the first switch (PTR1) and the second switch (ITR1) are switched on sequentially in a non-overlapping manner.

Description

BACKGROUND

Embodiments of the present inventive concept relate to image recognition technology, and more particularly, embodiments of the present inventive concept relate to image sensors.

A CMOS image sensor is a solid-state image sensing device manufactured using complementary metal-oxide semiconductor (CMOS) technology. As such, compared to other types of image sensors such as charge-coupled devices (CCDs), a CMOS image sensor can be manufactured at relatively low cost. Additionally, the CMOS image sensor exhibits relatively low power consumption compared to CCD image sensors.

These advantages, coupled with improved performance, have led to the CMOS image sensor being widely used in a variety of home electrical appliances as well as portable devices such as smartphones and digital cameras.

One technical challenge presented by CMOS image sensors relates to ambient light. That is, ambient light can add noise to the image data obtained by the CMOS image sensor, and if a varying amount of ambient light falls on pixels contained within the CMOS image sensor, the image data can be distorted.

DE 10 2011 089 642 A1 provides a time-of-flight sensor having at least one time-of-flight pixel, which is constructed in particular as a photonic mixer detector, and at least one photopixel assigned to the time-of-flight pixel. Furthermore, a readout device is provided, which is connected to both the time-of-flight pixel and the photopixel and is designed to read out an electrical quantity, in particular charges and/or voltages, of the time-of-flight pixel and the photopixel. Additionally, an evaluation device is provided, which is designed such that a distance value can be determined based on the electrical quantities of the at least one time-of-flight pixel, wherein the time-of-flight sensor is designed such that the electrical quantity of the photopixel is taken into account for determining the distance value.

DE 10 2011 053 219 A1 relates to a pixel with a phase subpixel having a photosensitive pixel area for detecting incident electromagnetic radiation, wherein the phase subpixel detects the relative phase of an intensity-modulated light signal in comparison to a reference signal whose frequency is correlated with the modulation frequency of the intensity-modulated light signal, and with one or more color-selective subpixels, each having a pixel area selectively photosensitive for a different spectral range, and with pixel electronics with a buffer for detecting the measurement signals of the pixel. To generate a 3D color image point with relatively good quality and good resolution while simultaneously having a relatively small pixel surface, the sum of the photosensitive pixel areas of color-selective subpixels is smaller than the photosensitive pixel area of the phase subpixel.

US 2002/0 176 067 A1 discloses a high dynamic range circuit usable with a ranging system that detects reflected energy to determine the time of flight to a target object reflecting the energy, the circuit comprising: at least one detector to detect the reflected energy and output a detection signal; for each detector, a resettable integrator coupled to integrate the detection signal and output an integration signal, the resettable integrator having a gain G that is dynamically variable; for each detector, a comparator coupled to receive the integration signal and compare it to a threshold and output a pulse when the integration signal exceeds the threshold, an output of the comparator being fed back to reset the detector; and for each detector, a resettable logic counter coupled to count each pulse output by the comparator. Means for providing a RESET signal to the integrator and the logic counter, wherein when the resettable logic counter reaches a predetermined count value, a count value within the logic counter is read and the RESET signal is provided to reset at least two of the detector, comparator and logic counter.

DE 10 2005 056 774 A1 discloses a TOF pixel, consisting of at least one radiation-sensitive region and at least two connection contacts on an integrated semiconductor chip which conduct charges from the radiation-sensitive region, as well as at least one storage region for charges which is assigned to the radiation-sensitive region, wherein free charge carriers are generated in the radiation-sensitive region in response to irradiation, and wherein the radiation-sensitive region can be acted upon simultaneously by intensity-modulated radiation and an electric modulation field, the frequency of which is in a well-defined relationship to the modulation frequency of the intensity-modulated radiation, characterized in that an integrated monitoring circuit is provided which monitors the amount of charge on or the corresponding voltage at the at least one storage area and which has devices for detecting the amount of charge on the at least one storage area or a voltage equivalent thereto or a corresponding current and devices for preventing a storage overflow.

SUMMARY

An embodiment of the present invention is directed to an image sensor comprising a first photoelectric conversion element configured to provide photocharges to a first charge storage node, a first charge storage element different from the first charge storage node (CSN1) and configured to store an amount of charge to cancel at least a portion of the charges stored in the first charge storage node in response to a feedback signal, and a feedback signal generation circuit configured to generate the feedback signal based on the amount of charge in the first charge storage node. The image sensor further comprises a first switch configured to switch the supply of charges from a charge supply source to the first charge storage element; and a second switch configured to switch the supply of the charges stored in the first charge storage element to the first charge storage node, wherein the first switch and the second switch are switched on sequentially in a non-overlapping manner.

According to an exemplary embodiment, the first switch is connected to the charge supply source, and the second switch is connected to the first charge storage node. The first charge storage element is connected between the first switch and the second switch.

According to an exemplary embodiment, the image sensor further includes a second photoelectric conversion element configured to provide charges to a second charge storage node, and a second charge storage element configured to adjust an amount of charge provided by the charge supply source to the second charge storage node in response to the feedback signal. The feedback signal generation circuit may generate the feedback signal based on the amount of charge in the first charge storage node and an amount of charge in the second charge storage node.

According to an exemplary embodiment, the feedback signal generation circuit may include a comparator that compares a first pixel signal related to the amount of charge in the first charge storage node with a second pixel signal related to the amount of charge in the second charge storage node and generates a comparison signal according to a result of the comparison, a first selection circuit configured to output the first pixel signal or the second pixel signal based on the comparison result, and a second selection circuit configured to output a default voltage signal or an output signal of the first selection circuit as the feedback signal based on a charge supply control signal.

According to an exemplary embodiment, the charges generated by the first photoelectric conversion element may be provided to the first charge storage node in response to a clock signal, and the charges generated by the second photoelectric conversion element may be provided to the second charge storage node in response to a complementary clock signal. According to an exemplary embodiment, the first charge storage element and the second charge storage element may each be a MOS capacitor.

According to an exemplary embodiment, the feedback signal generation circuit may further include a comparator that compares a reference signal with a first pixel signal related to the amount of charge in the first charge storage node and generates a comparison signal according to a result of the comparison, and a selection circuit that outputs a default voltage signal or a charge supply control signal as the feedback signal based on the comparison signal. According to an exemplary embodiment, a counter configured to count a transition frequency of a level of the comparison signal and a memory configured to store a count value of the counter may be further included.

According to an exemplary embodiment, the image sensor may further include a second photoelectric conversion element configured to provide charge in a second storage node, and a second charge storage element configured to adjust an amount of charge provided by the charge supply source to the second charge storage node in response to the feedback signal. The feedback signal generating circuit may further include a first comparator that compares a reference signal with a first pixel signal related to the amount of charge in the first charge storage node and generates a first comparison signal according to a result of the comparison, a second comparator that compares the reference signal with a second pixel signal related to the amount of charge in the second charge storage node and generates a second comparison signal, and a selection circuit configured to output a default voltage signal or a charge supply voltage signal as the feedback signal based on the first comparison signal and the second comparison signal.

According to an exemplary embodiment, the charges generated by the first photoelectric conversion element may be provided to the first charge storage node in response to a clock signal, and the charges generated by the second photoelectric conversion element may be provided to the second charge storage node in response to a complementary clock signal. According to an exemplary embodiment, the second photoelectric conversion element configured to provide charges to the second charge storage node may be further included, and the first charge storage element may adjust an amount of charge provided by the charge supply source to the first charge storage node or an amount of charge provided by the charge supply source to the second charge storage node in response to the feedback signal.

According to an exemplary embodiment, a first switch configured to switch a charge supply from the charge supply source to the first charge storage element, a second switch that switches the provision of charges stored in the first charge storage element to the first charge storage node, and a third switch configured to control the provision of charges stored in the second charge storage element to the first charge storage node may be further included. According to an exemplary embodiment, the second switch and the third switch may each be turned on at a different timing.

According to an exemplary embodiment, the first and second switches may be turned on together when a reset operation for resetting the first charge storage node is executed.

According to an exemplary embodiment, a second photoelectric conversion element configured to provide charges to a second charge storage node and a second charge storage element configured to adjust an amount of charge provided by the charge supply source to the second charge storage node may be further included. The first photoelectric conversion element and the second photoelectric conversion element are each arranged in different rows. The feedback signal generation circuit may transmit the feedback signal generated based on an amount of charge in the first charge storage node to the first charge storage node, or transmit the feedback signal generated based on an amount of charge in the second charge storage node to the second charge storage node.

According to an exemplary embodiment, the first charge storage element SMCAP may adjust an amount of charge provided by the charge supply source to the first charge storage node or an amount of charge provided by the charge supply source to the second charge storage node in response to the feedback signal.

BRIEF DESCRIPTION OF THE DRAWINGS

• 1 ein Blockschaltbild eines Bildverarbeitungssystems gemäß einer beispielhaften Ausführungsform der vorliegenden erfinderischen Konzepte ist;
• 2 ein Blockschaltbild gemäß einer beispielhaften Ausführungsform eines Bildsensors, welcher in 1 veranschaulicht ist, ist;
• 3 ein Schaltbild gemäß einer beispielhaften Ausführungsform eines Einheitspixels und einer Rückkopplungssignal-Erzeugungsschaltung, welche in 2 veranschaulicht sind, ist;
• 4 ein Blockschaltbild gemäß einer beispielhaften Ausführungsform der Rückkopplungssignal-Erzeugungsschaltung, welche in 3 veranschaulicht ist, ist;
• 5 ein Zeitverlaufsdiagramm gemäß einer beispielhaften Ausführungsform von Signalen, welche in den 3 und 4 veranschaulicht sind, ist;
• 6 ein Zeitverlaufsdiagramm gemäß einer anderen beispielhaften Ausführungsform der Signale, welche in 3 und 4 veranschaulicht sind, ist;
• 7 ein Schaltbild gemäß einer anderen beispielhaften Ausführungsform des Einheitspixels und der Rückkopplungssignal-Erzeugungsschaltung, welche in 2 veranschaulicht sind, ist;
• 8 ein Schaltbild gemäß noch einer anderen beispielhaften Ausführungsform des Einheitspixels und der Rückkopplungssignal-Erzeugungsschaltung, welche in 2 veranschaulicht sind, ist;
• 9 ein Schaltbild gemäß noch einer anderen beispielhaften Ausführungsform des Einheitspixels und der Rückkopplungssignal-Erzeugungsschaltung, welche in 2 veranschaulicht sind, ist;
• 10 ein Blockschaltbild gemäß einer beispielhaften Ausführungsform der Rückkopplungssignal-Erzeugungsschaltung, welche in 9 veranschaulicht ist, ist;
• 11 ein Blockschaltbild gemäß einer anderen beispielhaften Ausführungsform der Rückkopplungssignal-Erzeugungsschaltung, welche in 9 veranschaulicht ist, ist;
• 12 ein Zeitverlaufsdiagramm gemäß einer beispielhaften Ausführungsform von Signalen, welche in den 9 bis 11 veranschaulicht sind, ist;
• 13 ein Schaltbild gemäß noch einer anderen beispielhaften Ausführungsform des Einheitspixels und der Rückkopplungssignal-Erzeugungsschaltung, welche in 2 veranschaulicht sind, ist;
• 14 ein Schaltbild gemäß noch einer anderen beispielhaften Ausführungsform des Einheitspixels und der Rückkopplungssignal-Erzeugungsschaltung, welche in 2 veranschaulicht sind, ist;
• 15 ein Schaltbild gemäß noch einer anderen beispielhaften Ausführungsform des Einheitspixels und der Rückkopplungssignal-Erzeugungsschaltung, welche in 2 veranschaulicht sind, ist;
• 16 ein Zeitverlaufsdiagramm gemäß einer beispielhaften Ausführungsform von Signalen, welche in 15 veranschaulicht sind, ist;
• 17 ein Schaltbild gemäß noch einer anderen Ausführungsform des Einheitspixels und der Rückkopplungssignal-Erzeugungsschaltung, welche in 2 veranschaulicht sind, ist;
• 18 ein Zeitverlaufsdiagramm gemäß einer beispielhaften Ausführungsform von Signalen, welche in 17 veranschaulicht sind, ist;
• 19 eine beispielhafte Ausführungsform eines Pixel-Array bzw. einer Pixel-Anordnung und der Rückkopplungssignal-Erzeugungsschaltung, welche in 2 veranschaulicht sind, ist;
• 20 ein Zeitverlaufsdiagramm gemäß einer beispielhaften Ausführungsform von Signalen, welche in 19 veranschaulicht sind, ist;
• 21 ein Schaltbild gemäß einem modifizierten Beispiel von Einheitspixeln und einer Rückkopplungssignal-Erzeugungsschaltung, welche in 19 veranschaulicht sind, ist;
• 22 ein modifiziertes Beispiel eines Zeitverlaufsdiagramms, welches in 20 veranschaulicht ist, ist;
• 23 ein Graph zum Erklären einer Umgebungslicht-Auslöschungs (ALC=Ambient Light Cancellation)-Operationsanzahl ist, welche während einer Integrationssektion von Pixeln, welche in 2 veranschaulicht sind, durchgeführt werden kann, ist;
• 24 bis 28 Zeichnungen sind, welche im Muster von Taktsignalen abbilden, welche dem Pixel-Array, welches in 2 veranschaulicht ist, zur Verfügung gestellt werden;
• 29 ein Flussdiagramm eines Verfahrens zum Betreiben eines Bildsensors gemäß einer beispielhaften Ausführungsform der vorliegenden erfinderischen Konzepte ist;
• 30 ein Flussdiagramm eines Verfahrens zum Betreiben eines Bildsensors gemäß einer anderen beispielhaften Ausführungsform der vorliegenden erfinderischen Konzepte ist;
• 31 ein Blockschaltbild gemäß einer beispielhaften Ausführungsform eines Systems, welches den Bildsensor der 1 aufweist, ist; und
• 32 ein Blockschaltbild gemäß einer anderen beispielhaften Ausführungsform des Systems, welches den Bildsensor der 1 aufweist, ist.

These and/or other aspects and advantages of the present general inventive concept will become apparent and more readily appreciated from the following description of the embodiments, taken together with the accompanying drawings, in which:

• 1 is a block diagram of an image processing system according to an exemplary embodiment of the present inventive concepts;
• 2 a block diagram according to an exemplary embodiment of an image sensor, which in 1 is illustrated, is;
• 3 a circuit diagram according to an exemplary embodiment of a unit pixel and a feedback signal generating circuit shown in 2 illustrated is;
• 4 a block diagram according to an exemplary embodiment of the feedback signal generating circuit shown in 3 is illustrated, is;
• 5 a timing diagram according to an exemplary embodiment of signals included in the 3 and 4 illustrated is;
• 6 a timing diagram according to another exemplary embodiment of the signals shown in 3 and 4 illustrated is;
• 7 a circuit diagram according to another exemplary embodiment of the unit pixel and the feedback signal generating circuit shown in 2 illustrated is;
• 8 a circuit diagram according to yet another exemplary embodiment of the unit pixel and the feedback signal generating circuit shown in 2 illustrated is;
• 9 a circuit diagram according to yet another exemplary embodiment of the unit pixel and the feedback signal generating circuit shown in 2 illustrated is;
• 10 a block diagram according to an exemplary embodiment of the feedback signal generating circuit shown in 9 is illustrated, is;
• 11 a block diagram according to another exemplary embodiment of the feedback signal generating circuit shown in 9 is illustrated, is;
• 12 a timing diagram according to an exemplary embodiment of signals included in the 9 to 11 illustrated is;
• 13 a circuit diagram according to yet another exemplary embodiment of the unit pixel and the feedback signal generating circuit shown in 2 illustrated is;
• 14 a circuit diagram according to yet another exemplary embodiment of the unit pixel and the feedback signal generating circuit shown in 2 illustrated is;
• 15 a circuit diagram according to yet another exemplary embodiment of the unit pixel and the feedback signal generating circuit shown in 2 illustrated is;
• 16 a timing diagram according to an exemplary embodiment of signals used in 15 illustrated is;
• 17 a circuit diagram according to yet another embodiment of the unit pixel and the feedback signal generating circuit shown in 2 illustrated is;
• 18 a timing diagram according to an exemplary embodiment of signals used in 17 illustrated is;
• 19 an exemplary embodiment of a pixel array and the feedback signal generating circuit shown in 2 illustrated is;
• 20 a timing diagram according to an exemplary embodiment of signals used in 19 illustrated is;
• 21 a circuit diagram according to a modified example of unit pixels and a feedback signal generating circuit shown in 19 illustrated is;
• 22 a modified example of a time course diagram, which is shown in 20 is illustrated, is;
• 23 is a graph for explaining an ambient light cancellation (ALC) operation number performed during an integration section of pixels located in 2 are illustrated, can be carried out;
• 24 to 28 Drawings are those that depict the pattern of clock signals that correspond to the pixel array that is 2 illustrated;
• 29 is a flowchart of a method of operating an image sensor according to an exemplary embodiment of the present inventive concepts;
• 30 is a flowchart of a method of operating an image sensor according to another exemplary embodiment of the present inventive concepts;
• 31 a block diagram according to an exemplary embodiment of a system, which the image sensor of the 1 has, is; and
• 32 a block diagram according to another exemplary embodiment of the system, which includes the image sensor of the 1 has, is.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to the embodiments of the present general inventive concept, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. The embodiments are described below in order to explain the present general inventive concept by reference to the figures.

1 is a block diagram of an image processing system according to an exemplary embodiment of the present inventive concepts. Referring to 1 An image processing system 10 may include an image sensor 100, an image signal processor (ISP) 200, and a display unit 205.

According to one exemplary embodiment, the image sensor 100 and the ISP 200 may be implemented in a single-chip system. According to another exemplary embodiment, the image sensor 100 and the ISP 200 may be packaged in a multi-chip package. According to yet another exemplary embodiment, the image sensor 100 may be implemented in a separate chip from the ISP 200. For example, the image sensor 100 may be implemented in a CMOS image sensor chip.

The image sensor 100 can output image data IDATA corresponding to an image of an object. According to an exemplary embodiment, the image sensor 100 can perform a function of a depth sensor, which can obtain and process depth information (or a depth image or depth map) of an object. In this case, the image sensor 100 can operate in a time-of-flight (TOF) mode.

The ISP 200 may receive image data IDATA, process the received image data IDATA, and generate the processed image data IDATA'. According to an exemplary embodiment, the ISP 200 may generate the image data IDATA using a frame. According to an exemplary embodiment, the ISP 200 may correct light and shade, contrast, and/or chroma and color saturation of the image data IDATA via a processing step of processing the image data IDATA.

The ISP 200 can transmit the processed image data IDATA' to the display unit 205. The display unit 205 can refer to any type of device that can display the processed image data IDATA'. According to an exemplary embodiment, the display unit 205 can be embodied as a liquid crystal display (LCD), a light-emitting diode (LED) display, an organic LED (OLED), an active matrix OLED (AMOLED), or a flexible display.

2 is a block diagram according to an exemplary embodiment of the image sensor shown in 1 With reference to the 1 and 2 The image sensor 100 may include a light source 22, a pixel array 24, a readout circuit 28, a timing controller 30, a clock generator 32, a line decoder 34, an ambient light cancellation (ALC) control signal generation circuit 36, and a feedback signal generation circuit 38.

According to an exemplary embodiment, the image sensor 100 may operate in a rolling shutter mode or a freeze frame shutter mode.

The light source 22 may include a light source driver (not shown) for driving the light source 22. According to an exemplary embodiment, the light source 22 may output a modified light signal, such as infrared light, to an object. According to an exemplary embodiment, the image sensor 100 may further include an infrared light pass filter (not shown) for passing only a light signal output by the light source 22 and reflected by an object.

The pixel array 24 may include a plurality of unit pixels 26. A structure and operation of each of the plurality of unit pixels 26 will be described in detail with reference to 3 to 20 explained. According to an exemplary embodiment, each of the plurality of unit pixels may be embodied in a TOF sensor pixel.

The readout circuit 28 can generate image data IDATA based on pixel signals output from the pixel array 24.

The timing controller 30 may control any of the components of the image sensor, such as the light source 22, the readout circuit 28, the clock generator 32, the line decoder 34, the ALC control signal generation circuit 36, and/or the feedback signal generation circuit 38.

Clock generator 32 may generate clock signals under control of timing controller 30 and transmit the generated clock signals to pixel array 24. According to an exemplary embodiment, when each of the plurality of unit pixels 26 includes a photogate, clock generator 32 may transmit clock signals capable of driving the photogate to pixel array 24.

Row decoder 34 may decode a plurality of row control signals, such as row address signals, output from timing controller 30, and drive a specific row line included in pixel array 24 according to a decoding result. Row decoder 34 may refer to a concept including a row driver for driving a row line.

The ALC control signal generation circuit 36 may generate a plurality of ALC control signals for controlling an ambient light cancellation (ALC) operation and provide the plurality of generated ALC control signals to the pixel array 24 and/or the feedback signal generation circuit 38. The feedback signal generation circuit 38 may generate a feedback signal for controlling an ALC operation based on pixel signals output from the pixel array 24 and provide the generated feedback signal to each of the unit pixels 26 included in the pixel array 24.

3 is a circuit diagram according to an exemplary embodiment of the unit pixel and the feedback signal generating circuit shown in 2 are illustrated. With reference to the 2 and 3 may be a unit pixel 26A-1 according to an exemplary embodiment of the unit pixel 26 shown in 2 illustrated, a first sub-pixel 50-1A and a second sub-pixel 50-1B. That is, the unit pixel 26A-1 may have a two-TAP structure.

The first subpixel 50-1A may include a first photoelectric conversion element 40-1, a plurality of switches PTR1, ITR1, DTR1, and STR1, and a first charge storage element MCAP1. The plurality of switches PTR1, ITR1, DTR1, and STR1 may each be implemented in a metal oxide silicon field-effect transistor (MOSFET).

A transistor PTR1 can provide charges, for example holes, from a charge supply source, for example a power line VDD, to a first charge storage element MCAP1 in response to a first ALC control signal ALC1.

The first charge storage element MCAP1 can store charges, for example, holes, provided by the transistor PTR1 from the power supply line VDD. According to an exemplary embodiment, the first charge storage element MCAP1 can be implemented as a MOS capacitor. In this case, the capacitance of the first charge storage element MCAP1 can change according to a level of a feedback signal FBA. That is, an amount of charge provided to a first charge storage node CSN1 can be controlled by controlling a level of the feedback signal FBA.

A transistor ITR1 may provide charges, such as holes, stored in the first charge storage element MCAP1 to the first charge storage node CSN1 in response to a second ALC control signal ALC2.

The first photoelectric conversion element 40-1 transfers photocharges generated by the first photoelectric conversion element 40-1 to the first charge storage node CSN1 in response to a clock signal CLKA. The first photoelectric conversion element 40-1 may be implemented as a phototransistor, a photogate, or a pinned photodiode (PPD).

A level of the clock signal CLKA is in complementary relationship with a level of a complementary clock signal/CLKA.

A charge storage node, for example, the first charge storage node CSN1, refers to a node that can store charges generated by a photoelectric conversion element, for example, the first photoelectric conversion element 40-1. The charge storage node, for example, the first charge storage node CSN1, may be the same as or different from a floating diffusion node.

A transistor DTR1 performs a function of a source-follower buffer amplifier, which cher operates in response to a voltage corresponding to charges stored in the first charge storage node CSN1. A transistor STR1 can transmit a first pixel signal PIX1, which corresponds to charges generated by the first photoelectric conversion element 40-1, to each of a readout circuit 28 and a feedback signal generation circuit 38A in response to the selection signal RSEL.

The second subpixel 50-1B may include a second photoelectric conversion element 40-2, a plurality of switches PTR2, ITR2, DTR2, and STR2, and a second charge storage element MCAP2. The plurality of switches PTR2, ITR2, DTR2, and STR2 may each be implemented in a metal oxide silicon field-effect transistor (MOSFET).

The second sub-pixel 50-1B can output a second pixel signal PIX2 corresponding to charges generated by the second photoelectric conversion element 40-2. A detailed structure and operation of the second sub-pixel 50-1B are substantially the same as the structure and operation of the first sub-pixel 50-1A, so an explanation thereof is omitted.

The feedback signal generation circuit 38A may generate a feedback signal FBA based on the first pixel signal PIX1 and the second pixel signal PIX2. That is, the feedback signal generation circuit 38A may generate the feedback signal FBA based on a charge amount in the first charge storage node CSN1 and a charge amount in the second charge storage node CSN2. The feedback signal generation circuit 38A will be described in detail with reference to 4 The first ALC control signal ALC1 and the second ALC control signal ALC2, which are generated by an ALC control signal generating circuit (36 of the 2 ) are transmitted to the unit pixel 26A-1.

4 is a block diagram according to an exemplary embodiment of the feedback signal generating circuit shown in 3 is illustrated. With reference to the 3 and 4 the feedback signal generating circuit 38A may include a comparator 44, a first selection circuit 46A-1 and a second selection circuit 46A-2.

The comparator 44A compares the first pixel signal PIX1 with the second pixel signal PIX2 and transmits a comparison signal COMPA to the first selection circuit 46A-1 according to a result of the comparison.

The first selection circuit 46A-1 selects one of the first pixel signal PIX1 and the second pixel signal PIX2 based on the comparison signal COMPA transmitted from the comparator 44A, and outputs the selected signal as an output signal SOUT. The second selection circuit 46A-2 selects one of a preset voltage signal VOFF and the output signal SOUT based on a charge supply control signal SINJ, and outputs the selected signal as the feedback signal FBA.

The charge supply control signal SINJ may denote a signal for controlling an operation for storing charges, e.g., holes, to each charge storage element, e.g., MCAP1 or MCAP2, or an operation for making available charges, e.g., holes, stored in each charge storage element, e.g., MCAP1 or MCAP2, to each charge storage node, e.g., CSN1 or CSN2.

The default voltage signal VOFF may denote a signal having a voltage level provided by default when charges, such as holes, are not stored in each of the charge storage elements, such as MCAP1 and MCAP2. The charge supply control signal SINJ generated by the ACL control signal generation circuit (36 of the 2 ) is transmitted to the unit pixel 26A-1.

5 is a timing diagram according to an exemplary embodiment of signals included in the 3 and 4 are illustrated. With reference to the 3 to 5 a feedback signal FBA may transition at the same timing as the charge storage control signal SINJ as one of the set voltage signal VOFF and an output signal SOUT selected by the second selection circuit 46A-2 based on the charge supply control signal SINJ.

At a first time T1, the ALC control signal ALC1 may transition to a level, for example, a low level or "0," to turn on the switches PTR1 and PTR2. Here, the feedback signal FBA may transition to a level, for example, a low level or "0," to store charges, for example, holes, in the charge storage element MCAP1 or MCAP2 together with the first ALC control signal ALC1.

When the first ALC control signal ALC1 transitions to a low level or "0" at a first time T1, a transistor PTR1 or PTR2 can provide charges, for example, holes, from a charge supply source, for example, a power line VDD, to the charge storage element MCAP1 or MCAP2 in response to the first ALC control signal ALC1. When the feedback signal FBA transitions to a low level, for example, "0," at a first time T1, the charge storage element MCAP1 or MCAP2 can store charges, for example, holes, provided via the transistor PTR1 or PTR2 from the power line VDD in response to the feedback signal FBA.

At a second time T2, the first ALC control signal ALC1 may transition to a level, for example a high level or “1” to turn off switches PTR1 and PTR2.

At a third time T3, the second ALC control signal ALC2 may transition to a level, for example, a low level or "0," to turn on the switches ITR1 and ITR2. When the second ALC control signal ALC2 transitions to a low level or "0" at the third time T3, the transistor ITR1 or ITR2 may provide charges, for example, holes, stored in the charge storage elements MCAP1 or MCAP2 to the charge storage node CSN1 or CSN2 in response to the second ALC control signal ALC2. When the charges, for example, holes, are provided to the charge storage node CSN1 or CSN2, charges, for example, photocharges, generated by a photoelectric conversion element 40-1 or 40-2 are extinguished, and a level of the pixel signal PIX1 or PIX2 may be increased. As a result, saturation of a subpixel 50-1A or 50-1B by ambient light can be prevented.

At a fourth time T4, the feedback signal FBA may transition to a level, for example, a high level or "1," for completely releasing charges, such as holes, stored in the charge storage element MCAP1 or MCAP2, together with the charge supply control signal SINJ. At a fifth time T5, the second ALC control signal ALC2 may transition to a level, for example, a high level or "1," for turning off the switches ITR1 and ITR2.

6 is a timing diagram according to another exemplary embodiment of signals included in the 3 and 4 are illustrated. With reference to the 3 , 4 and 6 the first ALC control signal ALC, the charge supply control signal SINJ, the second ALC control signal ALC2, and the feedback signal FBA may all transition to a low level or “0” at the first time T1.

The charge storage node CSN1 or CSN2 may be reset at a first time T1. That is, each of the subpixels 50-1A and 50-1B may not include an additional transistor for a reset operation. The first ALC control signal ACL1, the charge supply control signal SINJ, the second ALC control signal ALC2, and the feedback signal FBA may transition to a level, for example, a high level or "1," before the reset operation to complete a reset operation at a second time T2.

7 is a circuit diagram according to another exemplary embodiment of the unit pixel and the feedback signal generating circuit shown in 2 are illustrated. With reference to the 2 , 3 and 7 a unit pixel 26A-2 may be formed according to another exemplary embodiment of the unit pixel 26 of the 2 a first subpixel 50-2A and a second subpixel 50-2B.

Each of the first sub-pixel 50-2A and the second sub-pixel 50-2B may further include a transistor RTR1 or RTR2 for resetting the charge storage node CSN1 or CSN2 compared to each of the first sub-pixel 50-1A and the second sub-pixel 50-1B shown in 2 The transistor RTR1 or RTR2 can reset the charge storage node CSN1 or CSN2 in response to a reset signal RS.

8 is a circuit diagram according to yet another exemplary embodiment of the unit pixel and the feedback signal generating circuit shown in 2 are illustrated. With reference to the 2 , 3 , 7 and 8 a unit pixel 26A-3 according to yet another exemplary embodiment of the unit pixel 26, which in 2 illustrated, have a first sub-pixel 50-3A and a second sub-pixel 50-3B.

Each of the first sub-pixel 50-3A and the second sub-pixel 50-3B may further include a transistor TTR1 or TTR2 for transferring charges generated by the photoelectric conversion element 40-1 or 40-2 to a floating diffusion node FD1 or FD2, compared to each of the first subpixel 50-2A and the second subpixel 50-2B, which are 7 are illustrated.

In this case, the charge storage node CSN1 or CSN2 and the floating diffusion node FD1 or FD2 can be different nodes from each other. The transistor TTR1 or TTR2 can be switched by a transfer signal TS.

9 is a circuit diagram according to yet another exemplary embodiment of the unit pixel and the feedback signal generating circuit shown in 2 According to the 2 , 3 and 9 are a structure and operation of the unit pixel 26B-1 according to an exemplary embodiment of the unit pixel 26 shown in 2 is substantially the same as a structure and operation of the sub-pixel 50-1A or 50-1B shown in 3 That is, the unit pixel 26B-1 may have a one-TAP structure.

A pixel signal PIX3 output from the unit pixel 26B-1 may be transmitted to the readout circuit 28 and the feedback signal generating circuit 38B. The feedback signal generating circuit 38B may generate a feedback signal FBB based on a pixel signal PIX3. A structure and operation of the feedback signal generating circuit 38B will be described in detail with reference to FIG. 10 and 11 be explained.

10 is a block diagram according to an exemplary embodiment of the feedback signal generating circuit shown in 9 With reference to the 9 and 10 a feedback signal generating circuit 38B-1 according to yet another exemplary embodiment of the feedback signal generating circuit 38B of the 9 a comparator 44B-1 and a selection circuit 46B-1.

Comparator 44B-1 can compare pixel signal PIX3 with a reference signal VREF and transmit a comparison signal COMPB, which is generated according to a result of the comparison, to selection circuit 46B-1. Selection circuit 46B-1 selects one of the set voltage signal VOFF and the charge supply control signal SINJ based on comparison signal COMPB and outputs the selected signal as feedback signal FBB.

11 is a block diagram according to another exemplary embodiment of the feedback signal generating circuit shown in 9 With reference to the 9 to 11 a feedback signal generating circuit 38B-2 according to another exemplary embodiment of the feedback signal generating circuit 38B of the 9 further comprises a counter 48 and a memory 50 compared to the feedback signal generating circuit 38B-1 of the 10 have.

The counter 48 can count a transition number of the comparison signal COMPB. The memory 50 can store a count value of the counter. The count value can include information about a number of charges, for example, holes, provided to a charge storage node CSN3 in order to reduce noise caused by ambient light in the unit pixel 26B-1. The count value stored in the memory 50 can be used for the ISP (200 of the 1 ) can be used to process the image data IDATA.

12 is a timing diagram according to an exemplary embodiment of signals included in the 9 to 11 are illustrated. With reference to the 5 and 9 to 12 the first ALC control signal ALC1, the charge supply control signal SINJ and the second ALC control signal ALC2 can be in the same form as in 5 shown will be made available.

When a photoelectric conversion element 40-3 generates photocharges, a level of a pixel signal PIX3 becomes lower and lower from a reset voltage level VRST.

A level of the pixel signal PIX3 becomes identical to a level of the reference signal VREF at a first time T1 and becomes lower than the level of the reference signal VREF after the first time T1. In this case, a level of the comparison signal COMPB transitions, and the selection circuit 46B-1 outputs the charge supply control signal SINJ as the feedback signal FBB through the transitioned comparison signal COMPB.

When both a level of the feedback signal FBB and a level of the charge supply control signal SINJ transition at a second time T2, a charge storage element MCAP3 can store charges, for example holes, provided by a charge supply source, for example a power line VDD, via a transistor PTR3.

When the second ALC control signal ALC2 transitions to a third time T3, a transistor ITR3 can transfer charges, for example holes, stored in the charge storage element MCAP3 to a charge storage node CSN3 in response to the second ALC control signal ALC2. The charges, such as holes, provided by the charge storage element MCAP3 increase a level of the pixel signal PIX3.

Photocharges generated by the photoelectric conversion element 40-3 lower a level of the pixel signal PIX3, and when the level of the pixel signal PIX3 becomes lower than a level of the reference signal VREF, operations performed between the first time T1 and the third time T3 are repeated. That is, an ALC operation of a different number per pixel can be performed.

A level of the feedback signal FBB at a fourth time T4 transitions together with a level of the charge supply control signal SINJ.

13 is a circuit diagram according to yet another exemplary embodiment of the unit pixel and the feedback signal generating circuit shown in 2 are illustrated. With reference to the 2 , 7 and 13 are a structure and operation of a unit pixel 26B-2 according to yet another exemplary embodiment of the unit pixel 26 shown in 2 is substantially the same as a structure and operation of the first sub-pixel 50-2A shown in 7 is illustrated.

14 is a circuit diagram according to yet another exemplary embodiment of the unit pixel and the feedback signal generating circuit shown in 2 are illustrated. With reference to the 2 , 8 and 14 are a structure and operation of a unit pixel 26B-3 according to yet another exemplary embodiment of the unit pixel 26 shown in 2 is substantially the same as a structure and operation of the first sub-pixel 50-3A shown in 8 is illustrated.

15 is a circuit diagram according to yet another exemplary embodiment of the unit pixel and the feedback signal generating circuit shown in 2 are illustrated. With reference to 2 and 15 a feedback signal generating circuit 38B-3 according to yet another exemplary embodiment of the feedback signal generating circuit 38 of the 2 Comparators 44B-2 and 44B-3, a logic circuit 52 and a selection circuit 46B-2.

Comparator 44B-2 can compare a pixel signal PIX1 with the reference signal VREF and transmit a comparison result COMPB-1, which is generated by a result of the comparison, to logic circuit 52. Comparator 44B-3 compares a pixel signal PIX2 with the reference signal VREF and transmits a comparison signal COMPB-2, which is generated according to a result of the comparison, to logic circuit 52.

Logic circuit 52 may transmit a result of performing a logic operation on comparison signal COMPB-1 and comparison signal COMPB-2 to selection circuit 44B-2. According to an exemplary embodiment, logic circuit 52 may be implemented as an AND gate, and in this case, logic circuit 52 may output a high level or "1" when a level of pixel signal PIX1 is lower than a level of reference signal VREF and a level of pixel signal PIX2 is lower than a level of reference signal VREF.

The selection circuit 46B-2 may select one of the set voltage signal VOFF and the charge supply control signal SINJ based on an output value of the logic circuit 52, and output the selected signal as the feedback signal FBB.

16 is a timing diagram according to an exemplary embodiment of signals included in 15 are illustrated. With reference to the 15 and 16 the first ALC control signal ALC1, the charge supply control signal SINJ and the second ALC control signal ALC2 can be in the same form as in 5 shown is made available.

When the photoelectric conversion element 40-1 generates photocharges, a level of the pixel signal PIX1 becomes lower and lower from the reset voltage level VRST.

A level of the pixel signal PIX1 becomes identical to a level of the reference signal VREF at a first time T1 and becomes lower than the level of the reference signal VREF after the first time T1. That is, a level of the pixel signal PIX1 becomes lower than the level of the reference signal VREF, and a level of the pixel signal PIX2 also becomes lower than the level of the reference signal VREF after the first time T1.

In this case, the logic circuit 52 may output a high level or "1" based on a comparison signal COMPB-1 and a comparison signal COMPB-2, and the selection circuit 46B-1 may output the charge supply control signal SINJ as the feedback signal FBB through an output signal output from the logic circuit 42.

When both a level of the feedback signal FBB and a level of the charge supply control signal SINJ transition or switch at a second time T2, the charge storage element MCAP1 or MCAP2 can store charges, for example holes, which are provided from a charge supply source, for example a power line VDD, via the transistor PTR1.

When the second ALC control signal ALC2 transitions to a low level or "0" at a third time T3, a transistor ITR1 or ITR2 may provide charges, such as holes, stored in the charge storage element MCAP1 or MCAP2 to the charge storage node CFN1 or CFN2 in response to the second ALC storage signal ALC2. The charges, such as holes, provided by the charge storage element MCAP1 or MCAP2 increase a level of the pixel signal PIX1 or PIX2.

Photocharges generated by the photoelectric conversion element 40-1 or 40-2 lower the level of the pixel signal PIX1 or PIX2, and operations performed between a first time T1 and a third time T3 are repeated when the level of the pixel signal PIX1 or PIX2 becomes lower than a level of the reference signal VREF. That is, a different number of ALC operations can be performed by the pixel. A level of the feedback signal FBB transitions to a high level or "1" along with a level of the charge supply control signal SINJ at a fourth time T4.

17 is a circuit diagram according to yet another exemplary embodiment of the unit pixel and the feedback signal generating circuit shown in 2 are illustrated. With reference to the 2 , 15 and 17 use two photoelectric conversion elements 40-1 and 40-2, which are arranged in a unit pixel 26C according to yet another exemplary embodiment of the unit pixel 26 of the 2 contain a transistor SPTR and a charge storage element SMCAP in common.

A structure and an operation of the transistor SPTR and the charge storage element SMCAP are substantially the same as a structure and an operation of the transistor PTR1 or PTR2 and the charge storage element MCAP1 or MCAP2 shown in 15 are illustrated.

A transistor ITR1 and a transistor ITR2 can provide charges, for example, holes, to the charge storage node CSN1 or CSN2 at different timings in response to each of the second ALC control signals ALC2-1 and ALC2-1, which are different from each other. The operation of the transistor ITR1 and the transistor ITR2 will be described in detail with reference to 18 be described.

18 is a timing diagram according to an exemplary embodiment of signals included in 17 are illustrated. With reference to the 17 and 18 A second ALC control signal ALC2-1 transitions to a low level or "0" at a first time T1, and a second ALC control signal ALC2-2 transitions to a low level or "0" at a second time T2. This means that each of the transistors ITR1 and ITR2 can be turned on at a different timing and provide charges, such as holes, to the charge storage node CSN1 or CSN2 at a different timing.

19 is an exemplary embodiment of the pixel array and feedback signal generating circuit shown in 2 are illustrated. With reference to the 2 and 19 a pixel array 24-1 according to an exemplary embodiment of the pixel array 24, which is shown in 2 and a feedback signal generating circuit 38-1 according to an exemplary embodiment of the feedback signal generating circuit 38, which is shown in 2 For convenience of explanation, the pixel array 24-1 is illustrated as having four pixels 26-1 through 26-4.

A unit pixel 26-1 and a unit pixel 26-2 are placed on the same row line as each other, and a unit pixel 26-3 and a unit pixel 26-4 are placed on the same row line as each other. The unit pixel 26-1 and the unit pixel 26-3 are placed on the same column line as each other, for example, a j-th column line, and the unit pixel 26-2 and the unit pixel 26-4 are placed on the same column line, for example, a j+1-th column line.

For convenience of explanation, it is assumed that the feedback signal generating circuit 38-1 includes a first feedback signal generating circuit 38B-3 and a second feedback signal generating circuit 38B-3'.

The first feedback signal generating circuit 38B-3 may provide a feedback signal FBB to each of the pixels 26-1 and 26-3 included in the same column line, for example, the j-th column line.

The second feedback signal generating circuit 38B-3' may provide a feedback signal FBB' to each of the pixels 26-2 and 26-4 included in the same column line, for example, the j+1th column line. That is, pixels included in the same column line may include the feedback signal generating circuit 38B-3 or 38B-3'.

20 is a timing diagram according to an exemplary embodiment of signals included in 19 are illustrated. With reference to the 19 and 20 represents a time course diagram, which in 20 illustrates a timing of signals related to the pixels 26-1 and 26-3 included in the j-th column line.

While a selection signal RSEL' retains or maintains a first level, for example, a high level or "1" of the unit pixel 26-1 can be activated.

In a first section TI1, when a level of the pixel signals PIX1 and PIX2 output from the unit pixel 26-1 becomes lower than a level of the reference signal VREF, a level of an output signal (AND) of the logic circuit 52 may change. A level of the feedback signal FBB may be changed by the level-changed output signal (AND) of the logic circuit 52.

In order to reduce disturbances caused by ambient light in a second section TI2, charges, for example holes, may be provided to a charge storage node of the unit pixel 26-1 in response to the first ALC control signal ALC1', the feedback signal FBB and the second ALC control signal ALC2'.

While a selection signal RSEL' transitions to a second level, for example, a low level or "0" and a selection signal RSEL maintains a first level, for example, a high level or "1", a unit pixel 26-3 can be activated.

In a third section TI3, when a level of output signals PIX1 and PIX2 output from the unit pixel 26-3 becomes lower than a level of the reference signal VREF, a level of the output signal (AND) of the logic circuit 52 may change. A level of the feedback signal FBB may be changed by the level-changed output signal (AND) of the logic circuit 52.

In order to reduce disturbances caused by ambient light in a fourth section TI4, charges, for example holes, may be provided to a charge storage node of the unit pixel 26-3 in response to the first ALC control signal ALC1, the feedback signal FBB and the second ALC control signal ALC2.

21 is a circuit diagram according to a modified example of the unit pixels and the feedback signal generating circuit shown in 19 are illustrated. With reference to the 2 , 17 , 19 and 20 Except that the unit pixel 26-1 and the unit pixel 26-3 share a transistor SPTR and a charge storage element SMCAP, a structure and operation of the unit pixel 26-3 are substantially the same as a structure and operation of the unit pixel 26C shown in 17 is illustrated.

Additionally, since unit pixel 26-1 and unit pixel 26-3 share the transistor SPTR and the charge storage element SMCAP, unit pixel 26-1 may not include any component corresponding to the transistor SPTR and the charge storage element SMCAP. That is, unit pixel 26-1 and unit pixel 26-3 may share the transistor SPTR and the charge storage element SMCAP except for the feedback signal generation circuit 38B-3. In this case, unit pixel 26-1 does not need to be provided with the feedback signal FBB.

A structure and operation of switches ITR1', ITR2', DTR1', DTR2', STR1', and STR2' included in the unit pixel 26-1 and photoelectric conversion elements 40-1' and 40-2' are substantially the same as a structure and operation of switches ITR1, ITR2, DTR1, DTR2, STR1, and STR2 and photoelectric conversion elements 40-1 and 40-2, respectively.

The unit pixel 26-1 may be provided with second ALC control signals ALC2-1' and ALC-2-2' having different timings, instead of the second ALC control signal ALC2' of the 19 from the ALC control signal generating circuit 36, and the unit pixel 26-3 may be provided with second ALC control signals ALC2-1 and ALC-2 having different timings, instead of the second ALC control signal ALC2 provided in 19 is illustrated, from the ALC control signal generating circuit 36.

22 is a modified example of the time course diagram shown in 20 illustrated. With reference to the 19 and 20 a first section TI1 of the 20 be defined as a section which performs a measurement for an ALC operation, and a second section TI2 may be defined as a section in which an ALC operation is applied according to a result of the measurement, for example, an output signal (AND) of the logic circuit 52, to the first section TI1, ie, a section in which a charge, for example, a hole, is injected into a charge storage node.

With reference to the 19 , 20 and 22 can, unlike in 20 , a measurement for an ALC operation and an application of the ALC operation can be performed in parallel. For example, a measurement for the ALC operation in a specific row, such as ROW2 or ROW2, and an application of the ALC operation in a different row, such as ROW1 or ROW1, can be performed simultaneously.

According to an exemplary embodiment, the line decoder 34 included in the image sensor 100, which is 2 illustrated, may include a sub-row decoder (not shown) for driving row lines, which performs a measurement for an ALC operation, and an additional sub-row decoder (not shown) for driving row lines, which performs a measurement for an ALC operation. In addition, a measurement for the ALC operation is performed separately from the application of the ALC operation, so that a feedback signal generating circuit 38B-3 or 38B-3' may further include a memory (not shown) for storing a result of the measurement, for example, an output signal (AND) of the logic circuit 52 after performing the measurement for the ALC operation. According to an exemplary embodiment, the memory (not shown) may operate in a first-in-first-out (FIFO) mode.

A length of a measurement section TM for performing a measurement for an ALC operation with respect to each row, for example, ROW1, may be different from a length of an application section TA for performing an application of the ALC operation with respect to each row, for example, ROW1.

The measuring section TM for performing a measurement for an ALC operation with respect to each row, for example ROW1, is not overlapped with a section for reading out the pixel signals PIX1 and PIX2.

An application section TA for performing an application of the ALC operation with respect to each row, for example ROW1, may be overlapped with a section for reading out the pixel signals PIX1 and PIX2.

During a row time TROW, a measurement for one cycle of an ALC operation and an application of the ALC operation can be performed with respect to each row ROW1 to ROWN.

23 is a graph for explaining an operating frequency of an ambient light cancellation (ALC) which occurs during an integration section of pixels arranged in 2 illustrated. With reference to the 2 , 3 and 23 a pixel maximum capacity voltage VMAX can denote a voltage at which a pixel is saturated by a photocharge.

An integration time TINT can refer to a time section in which a pixel performs a photoelectric conversion in a frame.

In 23 It is assumed that the ALC operation is performed N times, an (N-1)th ALC operation is performed at a first time TN-1, and an Nth ALC operation is performed at a second time TN. Δt denotes an interval in which the ALC operation is performed. d denotes a time that runs to the integration time TINT after a last Nth ALC operation is performed.

A common offset voltage VC may denote a voltage value corresponding to a common component of the pixel signal PIX1 or PIX2 output from each of the sub-pixels, for example, 50-1A and 50-1B, included in each unit pixel 26. The common offset voltage VC may change according to VC(t) at an angle of α.

A differential voltage VD may denote a voltage value corresponding to a difference between the pixel signals PIX1 and PIX2 generated by each of the sub-pixels, for example 50-1A and 50-1B of the 3 which are contained in each unit pixel 26. The differential voltage VD can change according to VD (t) at an angle of β.

An ALC threshold voltage h may denote a voltage value that becomes a reference of the ALC operation. According to an exemplary embodiment, a voltage value of the reference signal VREF, which is 10 to 12 and 15 to 17 illustrated, be set to the same as the ALC threshold voltage h. An ALC voltage drop VALC can indicate a voltage value that drops due to the ALC operation. $$\text{VCMAX}=\text{ICMAX}\times \text{TINT}$$

A common offset voltage change rate ICMAX may denote a maximum change rate with respect to time of the common offset voltage VC. As in Equation 1, a maximum common voltage VCMAX (not shown) may be obtained by multiplying the common offset voltage change rate ICMAX by the integration time TINT. $$\text{tan}\left(\mathrm{\alpha }\right)=\text{VCMAX/TINT}$$ α is an angle at which VC (t) changes, and tan (α) can be obtained by equation 2, which is a ratio of the maximum common voltage VCMAX to the integration time TINT. $$\text{tan}\left(\mathrm{\beta }\right)=\text{VDMAX/TINT}$$

A maximum differential voltage VDMAX can denote a maximum value of the differential voltage VD at the integration time TINT. β denotes an angle at which VC(t) changes, and tan(β) can be obtained by Equation 3, which represents a ratio of the maximum differential voltage VDMAX to the integration time TINT. $$\text{tan}\left(\mathrm{\beta }\right)=\left(\text{VMAX}-2\text{h}\right)/\text{TINT}-\text{d}$$

Equation 4, which relates to tan (β), can be obtained using the base and altitude of a triangle. $$\text{h}=\text{d}\times \text{tan}\left(\mathrm{\alpha }\right)-\text{d}\times \text{tan}\left(\mathrm{\beta }\right)=\text{ALC}$$

Equation 5, which concerns the ALC threshold voltage h, can be obtained by adding a lower portion (dx tan (α)) and an upper portion (dx tan (β)) according to a division point DP. $$\text{d}=\left(\text{VMAX}-\text{tan}\left(\mathrm{\beta }\right)\times \text{TINT}\right)/\left(2\times \text{tan}\left(\mathrm{\alpha }\right)+\text{tan}\left(\mathrm{\beta }\right)\right)$$

Equation 6 can be obtained by combining equation 4 and equation 5, and d can be obtained by equation 6. $$\text{a}=\text{d}\times \text{tan}\left(\mathrm{\alpha }\right)$$ a can be obtained using d, which is obtained by Equation 6 and Equation 7. $$\Delta \text{t}=\text{h/tan}\left(\mathrm{\alpha }\right)$$ Δt can be obtained using the ALC threshold voltage h, which is obtained by Equation 5 and Equation 8. $$\text{TN}=\text{TINT}-\text{d}$$

A second time TN can be obtained using d, which is obtained by Equation 6 and Equation 9. $$\text{N}=\left[\text{TN/}\Delta \text{t}\right]$$ N, which represents a frequency of ALC operations that can be performed during the integration time TINT, can be obtained using Δt obtained by Equation 8, TN obtained by Equation 9, and Equation 10. That is, N can be obtained by rounding off decimal places from a value obtained by dividing the time TN in which an ALC operation is performed N times by Δt, which denotes an interval in which the ALC operation is performed.

The 24 to 28 are drawings that depict patterns of clock signals that correspond to the pixel array that is 2 illustrated, are made available. With reference to the 24 to 28 may be a pixel array 24A to 24E according to an exemplary embodiment of the pixel array 24 shown in 2 illustrated, have a plurality of unit pixels 26, each of which has a two-TAP structure.

With reference to the 24 and 25 Each of the plurality of unit pixels 26 included in a pixel array 24A or 24B may have a structure in which a column direction size is different from a row direction size, for example, a column direction size is larger than a row direction size. According to an exemplary embodiment, a ratio of the column direction size to the row direction size may be 2:1.

Referring to 24 Each different clock signal CLK1 or CLK2 may be provided alternately to each of the sub-pixels included in each of the plurality of unit pixels 26 in a row direction. A phase of a clock signal CLK1 and a phase of a clock signal CLK2 may be opposite to each other. That is, a phase difference between the clock signals CLK1 and CLK2 may be 180°.

Referring to 25 each different clock signal CLK1 or CLK2 may be alternately provided to each of the sub-pixels included in each of the plurality of unit pixels 26 in a row and column direction.

With reference to the 26 and 27 Each of the plurality of unit pixels 26 included in a pixel array 24C or 24D may have a different structure in which a column direction size is different from a row direction size, for example, a structure in which a column direction size is smaller than a row direction size. According to an exemplary embodiment, a ratio of the column direction size to the row direction size may be 1:2.

Referring to 26 Each different clock signal CLK1 or CLK2 may be provided alternately to each of the sub-pixels included in each of the plurality of unit pixels 26 in the column direction. Referring to 27 each different clock signal CLK1 or CLK2 may be alternately provided to each of the sub-pixels included in each of the plurality of unit pixels 26 in row and column directions.

Referring to 28 Each of the plurality of unit pixels 26 included in a pixel array 24E may have a structure in which a column direction size is different from a row direction size, for example, the column direction size is smaller than the row direction size. According to an exemplary embodiment, a ratio of the column direction size to the row direction size may be 1:4.

Each different clock signal CLK1 or CLK2 may be alternately provided to each of the sub-pixels included in each of the plurality of unit pixels 26 in row and column directions.

An ALC unit pixel 26' may be composed of two subpixels adjacent to each other in a column direction. The subpixels included in the ALC unit pixel 26' are included in different rows, and each different clock signal CLK1 or CLK2 may be provided to the subpixels. The ALC unit pixel 26' may denote a pixel representing a unit in which an ALC operation is performed, and the ALC operation may be performed based on a pixel signal output from each of the subpixels included in the ALC unit pixel 26'.

According to an exemplary embodiment, each of the plurality of unit pixels 26 included in the pixel array 24E may have a structure in which a size in a column direction is larger than a size in a row direction. For example, a ratio of the column direction to the row direction may be 4:1. In this case, the ALC unit pixel 26' may be composed of two sub-pixels adjacent to each other in a row direction. The sub-pixels included in the ALC unit pixel 26' may be included in different columns, and the sub-pixels may be provided with a different clock signal CLK1 or CLK2.

29 is a flowchart of a method for operating an image sensor according to an exemplary embodiment of the present inventive concepts. Referring to the 9 to 14 and 29 the photoelectric conversion element 40-3 may generate charges, for example, photocharges, according to light incident on the photoelectric conversion element 40-3, and provide the generated charges to the charge storage node CSN3 (S10).

By a charge storage element MCAP3 operating in response to a feedback signal FBB, the amount of charge supplied from a charge supply source, such as a power line VDD, to a charge storage node CSN3 can be adjusted (S12). The feedback signal generation circuit 38B can control generation of the feedback signal FBB based on a pixel signal PIX3 generated according to the amount of charge in the charge storage node CSN3 (S14).

30 is a flowchart of a method of operating the image sensor according to another exemplary embodiment of the present inventive concepts. Referring to the 3 to 8, 15 to 18 and 30 a photoelectric conversion element 40-1 may generate charges, for example, photocharges according to light incident on the photoelectric conversion element 40-1, and provide the generated charges to the charge storage node CSN1 (S20).

A photoelectric conversion element 40-2 may generate charges, for example, photocharges according to light incident on the photoelectric conversion element 40-2, and supply the generated charges to the charge storage node CSN2 (S22).

By means of a charge storage element MCAP1 or SMCAP, which operates in response to the feedback signal FBA or FBB, the amount of charge provided by a charge supply source, for example, a power line VDD, to a charge storage node CSN1 can be adjusted (S24). By means of a charge storage element MCAP2 or SMCAP, which operates in response to the feedback signal FBA or FBB, the amount of charge provided by a charge supply source, for example, a power line VDD, to a charge storage node CSN2 can be adjusted (S26).

A feedback signal generation circuit 38A or 38B-3 may control the generation of the feedback signal FBA or FBB based on the pixel signals PIX1 or PIX2 generated according to each amount of charge in the charge storage node CSN1 and the amount of charge in the charge storage node CSN2.

31 is a block diagram according to an exemplary embodiment of a system that uses the image sensor of the 1 Referring to the 1 and 31 An electronic system 1000 may be embodied in a data processing device that can use or support a mobile industrial processor interface (MIPI), such as a personal digital assistant (PDA), a portable multimedia player (PMP), an Internet Protocol television (IPTV), or a smartphone.

The electronic system 1000 has in the image sensor 100 the 1 , an application processor 1010 and a display 1050.

A camera serial interface (CSI) host 1012 embodied in the application processor 1010 can perform serial communication with a CSI device 1041 of the image sensor 100 via a camera serial interface. Here, the CSI host 1012 can include, for example, a de-serializer (DES), and the CSI device 1041 can include a serializer (SER). A DSI host 1011 embodied in the application processor 1010 can perform serial communication with a DSI device 1051 of the display 1050 for a display serial interface (DSI). Here, for example, the DSI host 1011 can include a serializer (SER), and the DSI device 1051 can include a de-serializer (DES).

According to an exemplary embodiment, the electronic system 100 may further include an RF chip 1060 that can communicate with the application processor 1010. A physical layer (PHY) 1013 included in the application processor 1010 and a PHY 1061 included in the RF chip 1060 can each transmit or receive data according to MIPI DigRF. According to an exemplary embodiment, the electronic system 1000 may further include a GPS receiver 1020, a memory 1070, a microphone (MIC) 1080, a dynamic access memory (DRAM) 1085, and a speaker 1090.

The electronic system 1000 may communicate using a World Interoperability For Microwave Access (Wimax) module 1030, a Wireless LAN (WLAN) module 100, and/or an Ultra Wideband module 1110.

32 is a block diagram according to another exemplary embodiment of the system including the image sensor of the 1 Referring to the 1 and 32 a bit processing system 1200 may process the image sensor 100 of the 1 , a processor 1210, a memory 1220, a display unit 1230 and an interface 1240.

According to an exemplary embodiment, the image processing system 1200 may be embodied in a medical device or a portable electronic device. The portable electronic device may be embodied in a mobile phone, a smartphone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a portable multimedia player (PMP), or an e-book.

Processor 1210 may remove an operation of image sensor 100 or process image data output from image sensor 100. According to an exemplary embodiment, processor 1210 may refer to ISP 200.

Memory 1220 may store a program for controlling operation of image sensor 100 and an image generated by processor 1210 via bus 1250 under control of processor 1210, and processor 1210 may execute the program by accessing the stored information. Memory 1220 may be implemented, for example, in a non-volatile memory.

The display unit 1230 may receive an image from the processor or the memory 1220 and display the image via a display, such as a liquid crystal display (LCD), an LED display, an OLED display, an active matrix organic light emitting diode (AMOLED) display, or a flexible display.

An interface 1240 may be embodied as an interface for inputting/outputting two-dimensional or three-dimensional images. According to an exemplary embodiment, the interface 1240 may be embodied as a wireless interface.

A method and apparatus according to an exemplary embodiment of the present inventive concepts can prevent a pixel from being saturated by ambient light by adjusting an amount of charge in a charge storage node and can expand a dynamic range of a pixel. A method and apparatus according to an exemplary embodiment of the present inventive concepts can reduce varying levels of noise occurring at the pixel by adjusting, by pixel, an amount of charge in a charge storage node included in each pixel.

A method and apparatus according to an exemplary embodiment of the present inventive concepts can have an efficient layout by sharing a circuit for an ambient light cancellation (ALC) operation between two sub-pixels included in a unit pixel or pixels included in different row wirings.

Claims (10)

An image sensor (100) comprising: a first photoelectric conversion element (40-1) configured to provide photocharges to a first charge storage node (CSN1); a first charge storage element (MCAP1) different from the first charge storage node (CSN1) and configured to store an amount of charge to cancel at least a portion of the charges stored in the first charge storage node in response to a feedback signal (FBA, FBB); a feedback signal generation circuit (38A, 38B) configured to generate the feedback signal (FBA, FBB) based on an amount of charge in the first charge storage node (CSN1); a first switch (PTR1) configured to switch the supply of charges from a charge supply source to the first charge storage element (MCAP1); and a second switch (ITR1) configured to switch the supply of the charges stored in the first charge storage element (MCAP1) to the first charge storage node (CSN1), wherein the first switch (PTR1) and the second switch (ITR1) are switched on sequentially in a non-overlapping manner. Image sensor (100) after Claim 1 , wherein the first switch (PTR1) is connected to the charge supply source, and the second switch (ITR1) is connected to the first charge storage node (CSN1), and wherein the first charge storage element (MCAP1) is connected between the first switch (PTR1) and the second switch (ITR1). Image sensor (100) after Claim 1 , further comprising: a second photoelectric conversion element (40-2) configured to provide charges to a second charge storage node (CSN2); and a second charge storage element (MCAP2) configured to adjust an amount of charge provided by the charge supply source to the second charge storage node (CSN2) in response to the feedback signal (FBA, FBB), wherein the feedback signal generating circuit (38A, 38B) generates the feedback signal (FBA, FBB) based on the amount of charge in the first charge storage node (CSN1) and the amount of charge in the second charge storage node (CSN2). Image sensor (100) after Claim 3 , wherein the feedback signal generation circuit (38A, 38B) comprises: a comparator (44) configured to compare a first pixel signal (PIX1) related to the amount of charge in the first charge storage node (CSN1) with a second pixel signal (PIX2) related to the amount of charge in the second charge storage node (CSN2), and to generate a comparison signal (COMPA) according to a result of the comparison; a first selection circuit (46A-1, 46B-1) configured to output the first pixel signal (PIX1) or the second pixel signal (PIX2) based on the comparison signal (COMPA); and a second selection circuit (46A-2, 46B-2) configured to output a default voltage signal (VOFF) or an output signal of the first output selection circuit (46A-1, 46B-1) as the feedback signal (FBA, FBB) based on a charge supply control signal. Image sensor (100) after Claim 3 , wherein the charges generated by the first photoelectric conversion element (40-1) are provided to the first charge storage node (CSN1) in response to a clock signal, and the charges generated by the second photoelectric conversion element (40-2) are provided to the second charge storage node (CSN2) in response to a complementary clock signal. Image sensor (100) after Claim 3 , wherein each of the first charge storage element (MCAP1) and the second charge storage element (MCAP2) is a MOS capacitor. Image sensor (100) after Claim 1 , wherein the feedback signal generation circuit (38A, 38B) comprises: a comparator (44) configured to compare a reference signal with a first pixel signal (PIX1) related to the amount of charge in the first charge storage node (CSN1), and to generate a comparison signal (COMPB) according to a result of the comparison; and a selection circuit (46A-1, 46B-1; 46A-2, 46B-2) configured to output a default voltage signal (VOFF) or a charge supply control signal as the feedback signal (FBA, FBB) based on the comparison signal (COMPB). Image sensor (100) after Claim 1 , further comprising: a second photoelectric conversion element (40-2) configured to provide charges to a second charge storage node (CSN2); and a second charge storage element (MCAP2) configured to adjust an amount of charge provided by the charge supply source to the second charge storage node (CSN2) in response to the feedback signal (FBA, FBB), wherein the feedback signal generating circuit (38A, 38B) comprises: a first comparator (44) configured to compare a reference signal with a first pixel signal (PIX1) related to the amount of charge in the first charge storage node (CSN1), and to generate a first comparison signal (COMPA); a second comparator (44) configured to compare the reference signal with a second pixel signal (PIX2) related to the amount of charge in the second charge storage node (CSN2) and to generate a second comparison signal (COMPB); and a selection circuit (46A-1, 46B-1; 46A-2, 46B-2) configured to output a default voltage signal (VOFF) or a charge supply control signal as the feedback signal (FBA, FBB) based on the first comparison signal (COMPA) and the second comparison signal (COMPB). Image sensor (100) after Claim 1 , further comprising a second photoelectric conversion element (40-2) configured to provide charges to the second charge storage node (CSN2), wherein the first charge storage element (MCAP1) adjusts an amount of charge provided by the charge supply source to the first charge storage node (CSN1) or an amount of charge provided by the charge supply source to the second charge storage node (CSN2). Image sensor (100) after Claim 1 , further comprising: a second photoelectric conversion element (40-2) configured to provide charges to a second charge storage node (CSN2); and a second charge storage element (MCAP2) configured to adjust an amount of charge provided from the charge supply source to the second charge storage node (CSN2) in response to the feedback signal (FBA, FBB), wherein the first photoelectric conversion element (40-1) and the second photoelectric conversion element (40-2) are each arranged in different rows, and the feedback signal generation circuit (38A, 38B) transmits the feedback signal (FBA, FBB) generated based on an amount of charge in the first storage node to the first charge storage node (CSN1) or transmits the feedback signal (FBA, FBB) generated based on an amount of charge in the second charge storage node (CSN2) to the second charge storage node (CSN2).