CN119400114A

CN119400114A - Gate driving circuit and driving method of display panel, and display device

Info

Publication number: CN119400114A
Application number: CN202411666894.8A
Authority: CN
Inventors: 黄悦; 黄寅虎; 杨盛际; 白枭; 朱志坚; 张大成
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd; Yunnan Chuangshijie Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd; Yunnan Chuangshijie Optoelectronics Technology Co Ltd
Priority date: 2024-11-20
Filing date: 2024-11-20
Publication date: 2025-02-07

Abstract

A gate driving circuit and a driving method of a display panel and a display device are provided, and belong to the technical field of display. The first input control circuit of each stage of driving unit can control the input end of the current stage of driving unit to be conducted with the input ends of other stages of driving units under the control of synchronous luminous control signals so that luminous signals are simultaneously transmitted into the multistage driving units, and the second input control circuit of each stage of driving unit can control the output end of the current stage of driving unit to be conducted with the input ends of other stages of driving units under the control of sequential luminous control signals so that luminous signals are transmitted into the multistage driving units step by step. The gate driving circuit can not only simultaneously output light-emitting signals to the plurality of rows of pixels to drive the plurality of rows of pixels to emit light synchronously, but also sequentially output light-emitting signals to the plurality of rows of pixels to drive the plurality of rows of pixels to emit light sequentially. The driving mode of the grid driving circuit is diversified, and the driving effect is good.

Description

Gate driving circuit and driving method of display panel and display device

Technical Field

The present application relates to the field of display technologies, and in particular, to a gate driving circuit and a driving method of a display panel, and a display device.

Background

The gate driving circuit is a circuit for transmitting a gate driving signal such as a light emitting signal to a pixel in a display panel to drive the pixel to emit light, and is an indispensable part of a display device.

In the related art, a gate driving circuit generally includes a plurality of driving units connected in cascade. The driving units are connected with the rows of pixels in the display panel in a one-to-one correspondence manner and are used for outputting luminous signals to the rows of pixels row by row so as to drive the rows of pixels to emit light row by row, namely, the progressive scanning is realized.

However, the current gate driving circuit has a single driving mode and a poor driving effect.

Disclosure of Invention

The grid driving circuit, the driving method and the display device of the display panel can solve the problems that the driving mode of the grid driving circuit is single and the driving effect is poor in the related art. The technical scheme is as follows:

in one aspect, a gate driving circuit of a display panel is provided, the gate driving circuit includes a cascaded multi-stage driving unit including a first input control circuit, a second input control circuit, and an output circuit;

The first input control circuit is respectively connected with the synchronous light-emitting control end, the input end of the output circuit and the input ends of the cascaded other stage driving units and is used for responding to the synchronous light-emitting control signals provided by the synchronous light-emitting control end to control the on-off of the input end of the output circuit and the input ends of the other stage driving units so as to enable the signals received by the input end of the output circuit to be transmitted to the input ends of the other stage driving units;

The second input control circuit is respectively connected with the sequential light-emitting control end, the output end of the output circuit and the input end of the other stage driving unit, and is used for responding to the sequential light-emitting control signal provided by the sequential light-emitting control end and controlling the on-off of the output end of the output circuit and the input end of the other stage driving unit so that the signal output by the output end of the output circuit is transmitted to the input end of the other stage driving unit, wherein the potential of the sequential light-emitting control signal is opposite to the potential of the synchronous light-emitting control signal in the same period;

the input end of the output circuit is used for receiving a luminous signal, the clock end of the output circuit is used for receiving a clock signal, the output end of the output circuit is used for being connected with pixels in the display panel, and the output circuit is used for outputting the luminous signal to the pixels through the output end after sampling the luminous signal based on the clock signal.

Optionally, the output circuit comprises a flip-flop;

The output circuit is used for sampling the luminous signals based on the jump edges of the clock signals and outputting the luminous signals to the pixels through the output end.

Optionally, the trigger is a double-edge D trigger, the second input control circuit is connected with the intermediate state end of the double-edge D trigger, and the driving unit further comprises a logic circuit;

the logic circuit is used for being connected between the output end of the double-edge D trigger and the pixel, and is also connected with the intermediate state end of the double-edge D trigger, and the logic circuit is used for carrying out logic operation on signals output by the output end and the intermediate state end of the double-edge D trigger and outputting the signals to the pixel.

Optionally, the logic operation is processed as an AND gate;

and the two input ends of the AND gate are respectively connected with the output end and the intermediate state end of the double-edge D trigger, and the output end of the AND gate is used for being connected with the pixel.

Optionally, the driving unit further comprises a third input control circuit, a first normal scan control circuit and a first reverse scan control circuit;

The first input control circuit is connected with the input ends of the other stage driving units through the third input control circuit, the third input control circuit is also connected with the synchronous light-emitting control end, and the first input control circuit and the third input control circuit are used for responding to the synchronous light-emitting control signal and controlling the on-off of the input ends of the output circuit and the input ends of the other stage driving units so as to enable signals received by the input ends of the output circuit to be transmitted to the input ends of the other stage driving units or enable signals received by the input ends of the other stage driving units to be transmitted to the input ends of the output circuit;

the first positive scan control circuit and the first negative scan control circuit are both connected between the first input control circuit and the third input control circuit, the first positive scan control circuit is also connected with a positive scan control end, the first negative scan control circuit is also connected with a negative scan control end, the first positive scan control circuit is used for responding to a positive scan control signal provided by the positive scan control end to control the on-off of the first input control circuit and the third input control circuit so that signals received by the input end of the output circuit are sequentially transmitted to the input end of the other stage driving unit through the first input control circuit and the third input control circuit, and the first negative scan control circuit is used for responding to a negative scan control signal provided by the negative scan control end to control the on-off of the first input control circuit and the third input control circuit so that signals received by the input end of the other stage driving unit are sequentially transmitted to the input end of the output circuit through the third input control circuit and the first input control circuit;

And in the same period, the potential of the reverse scanning control signal is opposite to the potential of the normal scanning control signal.

Optionally, the first input control circuit and the third input control circuit are further connected with the sequential light-emitting control end, and are used for responding to the synchronous light-emitting control signal and the sequential light-emitting control signal to control on-off of the input end of the output circuit and the input end of the other stage driving unit;

The first positive scanning control circuit is also connected with the negative scanning control end and is used for responding to the positive scanning control signal and the negative scanning control signal to control the on-off of the first input control circuit and the third input control circuit;

The first reverse scanning control circuit is also connected with the forward scanning control end and used for responding to the forward scanning control signal and the reverse scanning control signal to control the on-off of the first input control circuit and the third input control circuit.

Optionally, the first input control circuit comprises a first transmission gate, the third input control circuit comprises a second transmission gate, the first normal scan control circuit comprises a third transmission gate and a fourth transmission gate, and the first reverse scan control circuit comprises a fifth transmission gate and a sixth transmission gate;

The control end of the first transmission gate and the control end of the second transmission gate are respectively connected with the synchronous light-emitting control end and the sequential light-emitting control end, the control end of the third transmission gate to the control end of the sixth transmission gate are respectively connected with the positive scanning control end and the negative scanning control end, the input end of the first transmission gate is connected with the input end of the output circuit, the output end of the first transmission gate is connected with the input end of the third transmission gate and the output end of the fifth transmission gate, the output end of the third transmission gate is connected with the input end of the fourth transmission gate, the input end of the fifth transmission gate is connected with the output end of the sixth transmission gate, the output end of the fourth transmission gate and the input end of the sixth transmission gate are respectively connected with the output end of the second transmission gate, and the input end of the second transmission gate is connected with the input end of the other stage driving unit.

Optionally, the driving unit further comprises a first enhancing circuit and/or a second enhancing circuit;

the first enhancement circuit is connected between the third transmission gate and the fourth transmission gate and is used for enhancing signals output by the third transmission gate and transmitting the signals to the fourth transmission gate;

The second enhancement circuit is connected between the fifth transmission gate and the sixth transmission gate and is used for enhancing the signal output by the sixth transmission gate and transmitting the signal to the fifth transmission gate.

Optionally, the first enhancement circuit comprises an even number of first inverters connected in series; the second enhancement circuit comprises an even number of second inverters connected in series;

The input ends of the even number of first inverters connected in series are connected with the output end of the third transmission gate, and the output ends of the even number of first inverters connected in series are connected with the input end of the fourth transmission gate;

the input ends of the even number of second inverters connected in series are connected with the output end of the sixth transmission gate, and the output ends of the even number of second inverters connected in series are connected with the input end of the fifth transmission gate.

Optionally, the driving unit further comprises a fourth input control circuit, a second normal scan control circuit and a second reverse scan control circuit;

The fourth input control circuit is respectively connected with the sequential light-emitting control end, the input end of the output circuit and the output end of the other stage driving unit and is used for responding to the sequential light-emitting control signal and controlling the on-off of the output end of the other stage driving unit and the input end of the output circuit so as to enable the signals output by the output end of the other stage driving unit to be transmitted to the input end of the output circuit;

the second positive scanning control circuit is connected between the output end of the output circuit and the second input control circuit, is also connected with the positive scanning control end and is used for responding to a positive scanning control signal provided by the positive scanning control end to control the on-off of the output end of the output circuit and the second input control circuit so that a signal output by the output end of the output circuit is transmitted to the input end of the other stage driving unit through the second input control circuit;

The second reverse scanning control circuit is connected between the input end of the output circuit and the fourth input control circuit, is also connected with the reverse scanning control end and is used for responding to a reverse scanning control signal provided by the reverse scanning control end to control the on-off of the input end of the output circuit and the fourth input control circuit so that signals output by the output ends of the other stage driving units are transmitted to the input end of the output circuit through the fourth input control circuit;

Optionally, the second input control circuit and the fourth input control circuit are both connected with the sequential light-emitting control end, the second input control circuit is used for responding to the synchronous light-emitting control signal and the sequential light-emitting control signal to control the on-off of the output end of the output circuit and the input end of the other stage driving unit, and the fourth input control circuit is used for responding to the synchronous light-emitting control signal and the sequential light-emitting control signal to control the on-off of the output end of the other stage driving unit and the input end of the output circuit;

the second positive scanning control circuit is also connected with the negative scanning control end and is used for responding to the positive scanning control signal and the negative scanning control signal to control the on-off of the output end of the output circuit and the second input control circuit;

The second reverse scanning control circuit is also connected with the positive scanning control end and is used for responding to the positive scanning control signal and the reverse scanning control signal to control the on-off of the input end of the output circuit and the fourth input control circuit.

Optionally, the second input control circuit comprises a seventh transmission gate, the fourth input control circuit comprises an eighth transmission gate, the second normal scan control circuit comprises a ninth transmission gate, and the second reverse scan control circuit comprises a tenth transmission gate;

The control end of the seventh transmission gate and the control end of the eighth transmission gate are respectively connected with the synchronous light-emitting control end and the sequential light-emitting control end, the control end of the ninth transmission gate to the control end of the tenth transmission gate are respectively connected with the positive scanning control end and the negative scanning control end, the input end of the seventh transmission gate is connected with the output end of the ninth transmission gate, the output end of the seventh transmission gate is connected with the input end of the other stage driving unit, the input end of the ninth transmission gate is connected with the output end of the output circuit, the input end of the eighth transmission gate is connected with the output end of the other stage driving unit, the output end of the eighth transmission gate is connected with the input end of the tenth transmission gate, and the output end of the tenth transmission gate is connected with the input end of the output circuit.

Optionally, the driving unit further comprises an inverter circuit;

The inverting circuit is used for being connected between the output end of the output circuit and the pixel, and is used for transmitting signals output by the output end of the output circuit to the pixel after inverting processing.

Optionally, the inverting circuit includes a third inverter;

The input end of the third inverter is connected with the output end of the output circuit, and the output end of the third inverter is used for being connected with the pixel.

In another aspect, a driving method of a display panel is provided, which is applied to the gate driving circuit according to the above aspect, and the method includes:

In response to a synchronous light-emitting instruction, the first input control circuit responds to a synchronous light-emitting control signal provided by a synchronous light-emitting control end, controls the input end of the output circuit to be conducted with the input ends of other stage driving units, so that signals received by the input ends of the output circuit are transmitted to the input ends of the other stage driving units, and the output circuit in each stage driving unit synchronously outputs the received light-emitting signals to a plurality of rows of pixels in the display panel through the output end after sampling the received light-emitting signals based on the received clock signals so as to synchronously lighten the plurality of rows of pixels;

And responding to the sequential light-emitting instruction, controlling the on-off of the output end of the output circuit and the input end of the other stage driving unit by the second input control circuit in response to the sequential light-emitting control signal provided by the sequential light-emitting control end, transmitting the signal output by the output end of the output circuit to the input end of the other stage driving unit, sampling the received light-emitting signal by the output circuit in each stage driving unit based on the received clock signal, and sequentially outputting the sampled light-emitting signal to a plurality of rows of pixels in the display panel through the output end so as to sequentially light the plurality of rows of pixels.

In yet another aspect, a display device is provided, the display device including a display panel, and a gate driving circuit as described in the above aspect;

the display panel comprises a plurality of rows of pixels, and the grid driving circuit is connected with the plurality of rows of pixels and used for driving the plurality of rows of pixels to emit light.

In summary, the beneficial effects brought by the technical scheme provided by the application at least include:

A gate driving circuit and driving method of a display panel and a display device are provided. The first input control circuit of each stage of driving unit can control the input end of the current stage of driving unit to be conducted with the input ends of other stages of driving units under the control of synchronous luminous control signals so that luminous signals are simultaneously transmitted into the multistage driving units, and the second input control circuit of each stage of driving unit can control the output end of the current stage of driving unit to be conducted with the input ends of other stages of driving units under the control of sequential luminous control signals so that luminous signals are transmitted into the multistage driving units step by step. The gate driving circuit can not only simultaneously output light-emitting signals to the plurality of rows of pixels to drive the plurality of rows of pixels to emit light synchronously, but also sequentially output light-emitting signals to the plurality of rows of pixels to drive the plurality of rows of pixels to emit light sequentially. The driving mode of the grid driving circuit is diversified, and the driving effect is good.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a gate driving circuit according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a driving unit according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of another driving unit according to an embodiment of the present application;

fig. 4 is a schematic structural view of a driving unit according to another embodiment of the present application;

fig. 5 is a schematic view of a part of a driving unit according to an embodiment of the present application;

fig. 6 is a schematic view of a part of a driving unit according to another embodiment of the present application;

fig. 7 is a schematic view of a part of a driving unit according to another embodiment of the present application;

Fig. 8 is a schematic view of a part of a driving unit according to another embodiment of the present application;

fig. 9 is a schematic view of a part of a structure of a further driving unit according to an embodiment of the present application;

fig. 10 is a schematic view of a part of a structure of a further driving unit according to an embodiment of the present application;

fig. 11 is a schematic view of a part of a structure of a further driving unit according to an embodiment of the present application;

Fig. 12 is a schematic diagram of an overall circuit structure of a driving unit according to an embodiment of the present application;

fig. 13 is a schematic circuit diagram of a cascaded plurality of driving units according to an embodiment of the present application;

fig. 14 is a schematic diagram of a driving timing diagram of a gate driving circuit according to an embodiment of the present application;

Fig. 15 is a flowchart of a driving method of a display panel according to an embodiment of the present application;

fig. 16 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.

It is understood that the transistors used in the embodiments of the present application may be thin film transistors (thin film transistor, TFTs) or field effect transistors or other devices with the same characteristics, and examples of the field effect transistors may be metal-oxide-semiconductor (MOS) field effect transistors, which are also referred to as MOS transistors. The transistors employed in the embodiments of the present application are mainly switching transistors according to their roles in circuits. Since the source and drain of the switching transistor employed herein are symmetrical, the source and drain are interchangeable. In the embodiment of the present application, the source electrode is referred to as a first electrode, and the drain electrode is referred to as a second electrode. The middle terminal of the transistor is defined as a control electrode according to the form in the figure, and may be called a gate electrode, a signal input terminal as a source electrode, and a signal output terminal as a drain electrode. In addition, the switching transistor adopted in the embodiment of the application may include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level, turned off when the gate is at a high level, and the N-type switching transistor is turned on when the gate is at a high level, and turned off when the gate is at a low level. In addition, the plurality of signals in the various embodiments of the present application each correspond to a first potential and a second potential. The first potential and the second potential only represent that the potential of the signal has 2 state quantities, and do not represent that the first potential or the second potential has a specific value in the whole text.

With the development of display technology, various types of displays have been developed. Among them, a typical Organic LIGHT EMITTING Diode (OLED) micro-display is a silicon-based Organic Light Emitting Diode (OLED) micro-display. Silicon-based OLED microdisplays are active organic light emitting diode display devices fabricated with monocrystalline silicon as the active drive backplate, combining Complementary Metal Oxide Semiconductor (CMOS) processes and OLED technology. Silicon-based OLED microdisplays are widely used in devices such as augmented reality (augmented reality, AR), virtual Reality (VR), mixed Reality (MR), electronic viewfinder (electronic viewfinder, EVF), first person viewing angle (first person view, FPV), unmanned aerial vehicle, thermal imager, night vision device, infrared camera and/or medical device, due to their high resolution, high PPI, high contrast, high brightness, low power consumption, small volume and light weight. Where PPI refers to the number of pixels (pixels per inch) contained on a display, reflecting the pixel density of the display.

Structurally, the display driver integrated circuit (DISPLAY DRIVER INTEGRATE circuits, DDIC) and the silicon-based backplane (silicon backplane, si-BP) of a silicon-based OLED microdisplay may be integrated on the same IC. Among them, the Si-BP generally includes a pixel driving circuit array (ACTIVE AREA), a gate driving (GOA) circuit, and a source driver (GOA) circuit, which is also called a GOA control circuit. The embodiment of the application mainly researches a GOA circuit in Si-BP, which is mainly realized by a digital circuit and aims at providing a control signal for row driving of a pixel circuit array. Such as an emission SIGNAL (em_signal), abbreviated as an EM SIGNAL.

It will be appreciated that an EM signal is typically transmitted to a light emission control transistor in the pixel circuit array connected between the pull-up power supply line VDD (or the light emitting element OLED) and the driving transistor to control the light emission control transistor to be turned on or off. When the light-emitting control transistor is turned on, a path can be formed from the pull-up power line VDD to the pull-down power line VSS connected to the light-emitting element OLED, so that the light-emitting element OLED can be driven to emit light, and the silicon-based OLED micro-display displays a picture.

In some embodiments, the GOA circuit generally includes a plurality of driving units (also referred to as shift register GOA units) connected in cascade, where the plurality of GOA units are connected to the plurality of rows of pixels in a one-to-one correspondence, and output light emission signals to the plurality of rows of pixels row by row to drive the plurality of rows of pixels to emit light row by row. The light emitting element in a pixel is generally referred to as the above-described self-luminous OLED. That is, for an OLED, in this embodiment, it does not emit light at the same time for all pixels as a Liquid Crystal Display (LCD), i.e., the LCD is fully lit in its entirety. This results in a different time for each pixel in the OLED to operate.

For example, in an example in which the pixels are three primary color pixels capable of displaying red, green, and blue, some pixels display blue for a relatively long time. In this way, the blue color of the pixel is attenuated more than that of other pixels, and the blue color displayed by the pixel is slightly lighter than that displayed by other pixels when the blue color is displayed later, so that the same problems as red and green are displayed. Further, the display effect is poor.

Based on this, the embodiment of the application provides a new GOA circuit for an OLED display product such as a silicon-based OLED microdisplay. The GOA circuit not only can output the luminous signals EM to the pixels of the plurality of rows row by row to drive the pixels of the plurality of rows to emit light row by row, but also can output the luminous signals EM to the pixels of the plurality of rows simultaneously to drive the pixels of the plurality of rows to emit light synchronously, so that the display panel of the display can emit light synchronously on the whole surface (Global Emission). Therefore, the driving mode of the grid driving circuit can be enriched, the driving effect of the grid driving circuit can be improved, the grid driving circuit can drive the display panel to reliably display, and the display effect of the display panel is improved. Of course, the application is not limited to the silicon-based OLED micro-display.

Fig. 1 is a schematic diagram of a gate driving circuit (also referred to as a GOA circuit or a GOA control circuit) of a display panel according to an embodiment of the present application. As shown in fig. 1, the gate driving circuit includes a cascade of multi-stage driving units 00 (also called GOA units).

Alternatively, it may be that the nth stage driving unit 00 is cascaded with the n+i-th stage driving unit 00. Wherein n is more than or equal to 1 and less than or equal to M-i, M is the total number of stages of the multi-stage driving unit 00, M is more than or equal to 1, and i is a positive integer greater than or equal to 1. For example, referring to fig. 1, a gate driving circuit is shown in which every two adjacent driving units 00 are cascaded, i.e., i=1.

Taking the nth stage driving unit 00 of the multi-stage driving units 00 as an example on the basis of fig. 1, fig. 2 shows a schematic configuration of one driving unit 00. As can be seen in connection with fig. 1 and 2, the driving unit 00 comprises a first input control circuit 01, a second input control circuit 02 and an output circuit 03.

The first input control circuit 01 is connected to the synchronous light emission control terminal en_global, the input terminal D of the output circuit 03, and the input terminal of the cascade of other stage driving units 00, respectively. The first input control circuit 01 is configured to control on-off of the input terminal D of the output circuit 03 and the input terminal of the other stage driving unit 00 in response to the synchronous light emission control signal provided by the synchronous light emission control terminal en_global, so that the signal received by the input terminal D of the output circuit 03 is transmitted to the input terminal of the other stage driving unit 00.

It will be appreciated that in connection with fig. 2, the input of the other stage driving unit 00 according to the embodiment of the present application may refer to the input D of the output circuit 03 in the other stage driving unit 00. On the basis of this, the first input control circuit 01 is capable of controlling the input terminal D of the output circuit 03 in the current stage driving unit 00 to be turned on with the input terminal D of the output circuit 03 in the other stage driving unit 00 when the potential of the synchronous light emission control signal provided by the synchronous light emission control terminal en_global is the first potential, so that the signal received by the input terminal D of the output circuit 03 in the current stage driving unit 00 can be transmitted to the input terminal D of the output circuit 03 in the other stage driving unit 00, and the first input control circuit 01 is capable of controlling the input terminal D of the output circuit 03 in the current stage driving unit 00 to be disconnected from the input terminal D of the output circuit 03 in the other stage driving unit 00 when the potential of the synchronous light emission control signal provided by the synchronous light emission control terminal en_global is the second potential.

That is, for each stage driving unit 00, the first input control circuit 01 in the stage driving unit 00 can control the input terminal D of the output circuit 03 in the stage driving unit 00 to be directly conducted with the input terminal D of the output circuit 03 in the other stage driving unit 00 under the control of the synchronous light emitting control signal, so that the signal is directly transferred to the input terminal of each stage driving unit 00 without passing through the output circuit 03. In this way, the input terminal D of the output circuit 03 in each stage of the driving unit 00 can be made to receive the signal input to the input terminal D of the output circuit 03 in the driving unit 00. That is, the input terminals D of the output circuits 03 in the respective stages of the driving units 00 can be made to receive the same signal at the same time.

Alternatively, the first potential may be an effective potential, the second potential may be an ineffective potential, and the first potential may be a high potential with respect to the second potential. That is, the first potential may be a high potential and the second potential may be a low potential. Of course, in some embodiments, the first potential may also be a low potential relative to the second potential. Also, for an N-type transistor, the effective potential (i.e., the first potential) may be a high potential and the ineffective potential (i.e., the second potential) may be a low potential. For a P-type transistor, the active potential (i.e., the first potential) may be a low potential and the inactive potential (i.e., the second potential) may be a high potential.

The second input control circuit 02 is connected to the sequential emission control terminal en_global', the output terminal Q of the output circuit 03, and the input terminal of the other stage driving unit 00, respectively. And, the second input control circuit 02 is configured to control on-off of the output terminal Q of the output circuit 03 and the input terminal of the other stage driving unit 00 in response to the sequential light emission control signal provided by the sequential light emission control terminal en_global', so that the signal output by the output terminal Q of the output circuit 03 is transmitted to the input terminal of the other stage driving unit 00.

As described above, the input terminal of the other stage driving unit 00 may refer to the input terminal D of the output circuit 03 included in the other stage driving unit 00. On the basis of this, for example, the second input control circuit 02 can control the output terminal Q of the output circuit 03 in the current stage driving unit 00 to be turned on with the input terminal D of the output circuit 03 in the other stage driving unit 00 when the potential of the sequential emission control signal supplied from the sequential emission control terminal en_global 'is the first potential, so that the signal output from the output terminal Q of the output circuit 03 in the current stage driving unit 00 can be transmitted to the input terminal D of the output circuit 03 in the other stage driving unit 00, and the second input control circuit 02 can control the output terminal Q of the output circuit 03 in the current stage driving unit 00 to be disconnected from the input terminal D of the output circuit 03 in the other stage driving unit 00 when the potential of the sequential emission control signal supplied from the sequential emission control terminal en_global' is the second potential. The output Q of the current n-th stage drive unit 00 is denoted Qn in the figure.

That is, for each stage driving unit 00, the second input control circuit 02 in the stage driving unit 00 can control the output terminal Q of the output circuit 03 in the stage driving unit 00 to be conductive to the input terminal D of the output circuit 03 in the other stage driving unit 00 under the control of the sequential light emitting control signal, so that the signal is transferred to the input terminal of the other stage driving unit 00 after passing through the output circuit 03. In this way, the input terminal D of the output circuit 03 in each stage of the driving unit 00 can sequentially receive the signal output through the output terminal Q of the output circuit 03 in the driving unit 00. That is, the input terminals D of the output circuits 03 in the respective stages of the driving units 00 can be made to sequentially receive the same signal. For example, in the scenario where two adjacent driving units 00 are cascaded, the input end D of the output circuit 03 in the 2 nd driving unit 00 can first receive the signal output by the output end Q of the output circuit 03 in the cascaded 1 st driving unit 00, then the input end D of the output circuit 03 in the 3 rd driving unit 00 can further receive the signal output by the output end Q of the output circuit 03 in the cascaded 2 nd driving unit 00, and so on, so as to realize the cascade transmission of the signals.

Wherein, in the same period, the potential of the sequential light-emitting control signal is opposite to the potential of the synchronous light-emitting control signal. That is, when the potential of the synchronous light emission control signal is the first potential, the potential of the sequential light emission control signal may be the second potential, whereas when the potential of the synchronous light emission control signal is the second potential, the potential of the sequential light emission control signal may be the first potential. The first potential may be, for example, a high potential and the second potential may be, for example, a low potential.

As is clear from the above description, when the first input control circuit 01 controls the input terminal D of the output circuit 03 to be connected to the input terminal of the other stage driving unit 00 so that the signal is simultaneously transmitted to the input terminal of the driving unit 00 of each stage, the second input control circuit 02 may be configured to control the output terminal Q of the output circuit 03 to be disconnected from the input terminal of the driving unit 00 of the other stage, and when the second input control circuit 02 controls the output terminal Q of the output circuit 03 to be connected to the input terminal of the driving unit 00 of the other stage so that the signal is sequentially transmitted to the input terminal of the driving unit 00 of each stage in a cascade manner, the first input control circuit 01 may be configured to control the input terminal D of the output circuit 03 to be disconnected from the input terminal of the driving unit 00 of the other stage. That is, the input terminals of the respective stages of the driving units 00 may be made to receive signals either simultaneously or sequentially in order within one period.

The input terminal D of the output circuit 03 is for receiving the light emitting signal EM, the clock terminal CK of the output circuit 03 is for receiving the clock signal CLK, and the output terminal Q of the output circuit 03 is for connecting with a pixel (not shown in the figure) in the display panel. The output circuit 03 samples the emission signal EM based on the clock signal CLK and outputs the emission signal EM to the pixel via the output terminal Q. That is, the output circuit 03 can sample the light emitting signal EM received by the input terminal D under the control of the clock signal CLK and output the sampled light emitting signal EM to the pixel via the output terminal Q.

Alternatively, as can be seen in connection with fig. 1 and 2, in each stage of the driving unit 00, the input terminal D of the output circuit 03 may also be connected to the light emitting signal line Dn to receive the light emitting signal EM supplied from the light emitting signal line Dn. Here Dn may refer to a light emitting signal line to which the input terminal D of the output circuit 03 in the n-th stage driving unit 00 is connected. Accordingly, dn+1 may refer to a light emitting signal line connected to the input terminal D of the output circuit 03 in the n+1th stage driving unit 00.

Accordingly, cascading the n-th and n+1th stage driving units 00 may mean that the output terminal Q of the output circuit 03 in the n-th stage driving unit 00 is connected to the input terminal D of the output circuit 03 in the n+1th stage driving unit 00. In the embodiment of the present application, the output terminal Q of the output circuit 03 in the n-th driving unit 00 may be connected to the input terminal D of the output circuit 03 in the n+1th driving unit 00 via the second input control circuit 02. The light-emitting signal line dn+1 to which the input terminal D of the output circuit 03 in the n+1th stage driving unit 00 is connected is schematically shown in the figure. Of course, the input terminal D of the output circuit 03 in the first-stage driving unit 00 may be connected to a separate on signal line STV to receive the on signal provided by the on signal line STV, which is the light-emitting signal EM. Of course, the on signal line STV may be connected to the DDIC to receive the light-emitting signal EM supplied from the DDIC.

Also, the output terminals Q of the output circuit 03 in the multi-stage driving unit 00 may be connected in one-to-one correspondence with the rows of pixels in the display panel. That is, the output terminal Q of the output circuit 03 in each stage of the driving unit 00 may be connected to one row of pixels, and the output terminal Q of the output circuit 03 in each stage of the driving unit 00 may be connected to a different row of pixels. Of course, the one-to-one connection is not limited. For example, in some other embodiments, the output terminals Q of the output circuits 03 in each stage of the driving unit 00 may be connected to two or more rows of pixels.

As described above, as is clear from the foregoing description, the first input control circuit 01 can simultaneously receive the same emission signal EM which is not transmitted through the output circuit 03 at the input terminal D of the output circuit 03 in each stage of the driving unit 00 under the control of the synchronous emission control signal. Thus, the output circuit 03 in each stage of the driving unit 00 can simultaneously sample the same light-emitting signal EM based on the received clock signal CLK and simultaneously output the same light-emitting signal EM to the plurality of rows of pixels in the display panel via the output terminal Q, so as to drive the plurality of rows of pixels to emit light simultaneously. For example, the light-emitting control transistors are simultaneously output to the gates of the light-emitting control transistors in the plurality of rows of pixels, so that the light-emitting control transistors in each pixel are synchronously turned on, and then the plurality of rows of pixels of the display panel synchronously emit light for the same duration, so that the effect of whole-plane synchronous light-emitting display (Global Emission) is achieved.

The input terminals D of the output circuits 03 in each stage of the driving unit 00 can sequentially receive the light emission signal EM transmitted through the output circuits 03 under the control of the second input control circuit 02 in response to the sequential light emission control signal. Thus, the output circuit 03 in each stage of the driving unit 00 can sequentially sample the same light-emitting signal EM based on the received clock signal CLK and sequentially output the same light-emitting signal EM to the plurality of rows of pixels in the display panel via the output terminal Q, so as to drive the plurality of rows of pixels to sequentially emit light. For example, the pixel signals are output to the gates of the light-emitting control transistors in the pixels of a plurality of rows row by row, so that the light-emitting control transistors in each pixel are sequentially turned on, and then the pixels of a plurality of rows of the display panel emit light row by row, thereby achieving the effect of sequential light-emitting display (Sequential Emission).

That is, the gate driving circuit according to the embodiment of the present application can be compatible with two light Emission modes, namely Global Emission and Sequential Emission. In addition, in the same period, the potential of the sequential light-emitting control signal is opposite to the potential of the synchronous light-emitting control signal, so that the two light-emitting modes can be switched to be executed according to the display requirement under the control of the first input control circuit 01 and the second input control circuit 02, and the aim of adapting to various use scenes is fulfilled.

In summary, the embodiment of the application provides a gate driving circuit. The first input control circuit in each stage of driving unit can control the input end of the current stage of driving unit to be conducted with the input ends of other stages of driving units under the control of synchronous luminous control signals so that luminous signals are simultaneously transmitted into the multi-stage driving units, and the second input control circuit in each stage of driving unit can control the output end of the current stage of driving unit to be conducted with the input ends of other stages of driving units under the control of sequential luminous control signals so that luminous signals are transmitted into the multi-stage driving units step by step. The gate driving circuit can not only simultaneously output light-emitting signals to the plurality of rows of pixels to drive the plurality of rows of pixels to simultaneously emit light in synchronization, but also sequentially output light-emitting signals to the plurality of rows of pixels to drive the plurality of rows of pixels to sequentially emit light in sequence. That is, the gate driving circuit can be compatible with two light emitting modes of Global Emission and Sequential Emission, and the driving mode of the gate driving circuit is diversified and the driving effect is good.

In addition, on the basis of controlling the simultaneous synchronous light emission of a plurality of rows of pixels, the problem of poor display uniformity caused by inconsistent light emission time can be also improved. That is, a good display effect of the display panel can be ensured.

Alternatively, in some embodiments, the output circuit 03 may include a flip-flop. Correspondingly, the output circuit 03 may be configured to sample the light emitting signal EM based on the transition edge of the clock signal CLK and output the sampled light emitting signal EM to the pixel via the output terminal.

For example, the transition edge of the clock signal CLK may refer to a rising edge at which the potential of the clock signal CLK transitions from a low potential to a high potential. That is, the output circuit 03 may sample the light emission signal EM at the timing when the rising edge of the clock signal CLK comes, and output the sampled light emission signal EM to the pixel via the output terminal. Accordingly, the flip-flop included in the output circuit 03 may be a rising edge flip-flop.

Of course, in some other embodiments, the flip-flop may also be a falling edge flip-flop. That is, the transition edge of the clock signal CLK may also be referred to as a falling edge of the clock signal CLK from a high potential to a low potential.

Alternatively, as can be seen with reference to the schematic diagram of the structure of another driving unit 00 shown in fig. 3, the Flip-Flop is, for example, a double edge D Flip-Flop (DFF).

Accordingly, as shown in fig. 3, the second input control circuit 02 may be connected to the intermediate state terminal q_inter of the double edge D flip-flop DFF. And, the driving unit 00 may further include a logic circuit 04.

The logic circuit 04 may be used to connect between the output terminal Q of the double-edge D flip-flop DFF and the pixel, and the logic circuit 04 may also be connected to the intermediate state terminal q_inter of the double-edge D flip-flop DFF. The logic circuit 04 may be configured to perform logic operation on signals output by the output terminal Q of the dual edge D flip-flop DFF and the intermediate state terminal q_inter, and output the signals to the pixel.

It can be understood that the dual-edge D flip-flop DFF is a D flip-flop that can sample an input signal at both rising and falling edges of a clock signal, and the data processing efficiency can be improved by using the dual-edge D flip-flop DFF. In the double-edge D flip-flop DFF, the intermediate state terminal q_inter serves as an intermediate state output terminal, and can temporarily store the input signal until the transition edge of the next clock signal updates and outputs, thereby ensuring that stable output can still be achieved when the potential of the clock signal changes. For example, the input signal can be sampled and stored into the intermediate state terminal q_inter when the rising edge of the clock signal comes. When the falling edge of the clock signal comes, the input signal is output through the intermediate state terminal Q_INTER. Thus, two data sampling and output updating can be completed within one clock cycle. Further, referring to fig. 3, wherein Q 'of the dual-edge D flip-flop DFF means an inverting output terminal, a signal output through the Q' is exactly opposite in potential to a signal output through the output terminal Q. And, the dual-edge D flip-flop DFF further has a reset terminal Rn for receiving the reset signal RST, so as to be flexibly initialized under the control of the reset signal RST.

Alternatively, on the basis of setting the output circuit 03 as the dual-edge D flip-flop DFF, the second input control circuit 02 may be connected to an intermediate state terminal q_inter of the dual-edge D flip-flop DFF, and configured to control on-off of the intermediate state terminal q_inter and an input terminal of the other stage driving unit 00 under control of the sequential light emission control signal.

Alternatively, in some embodiments, the logical operation process may be an and process. The AND processing means that the logic circuit 04 outputs a high-potential signal when the potentials of all received signals are high, otherwise outputs a low potential. Accordingly, as can be seen from the schematic diagram of the further driving unit 00 shown in fig. 4, the logic circuit 04 may comprise an AND gate AND.

The two inputs a & B of the AND gate AND may be connected to the output Q of the double edge D flip-flop AND the intermediate state q_inter, respectively, AND the output OUT of the AND gate AND may be used for connection to a pixel.

Of course, neither is it limited to AND processing, and accordingly, the logic circuit 04 is not limited to AND gate design. For example, in some embodiments, logic 04 may include multiple gates combined.

Alternatively, fig. 5 is a schematic view of a part of the structure of a driving unit 00 according to an embodiment of the present application. As shown in fig. 5, the driving unit 00 may further include a third input control circuit 05, a first normal scan control circuit 06, and a first reverse scan control circuit 07.

The first input control circuit 01 may be connected to an input terminal of the other stage driving unit 00 through the third input control circuit 05, and the third input control circuit 05 may also be connected to the synchronous light emission control terminal en_global. The first input control circuit 01 and the third input control circuit 05 may be configured to control on-off of the input terminal D of the output circuit 03 and the input terminal D of the other stage driving unit 00 in response to the synchronous light emission control signal, so that the signal received by the input terminal D of the output circuit 03 is transmitted to the input terminal D of the other stage driving unit 00, or the signal received by the input terminal D of the other stage driving unit 00 is transmitted to the input terminal D of the output circuit 03.

For example, when the potential of the synchronous light emission control signal is the first potential, the first input control circuit 01 and the third input control circuit 05 may control the input terminal D of the output circuit 03 in the current stage driving unit 00 to be conductive to the input terminal D of the output circuit 03 in the other stage driving unit 00, so that the signal received by the input terminal D of the output circuit 03 in the current stage driving unit 00 is transmitted to the input terminal D of the output circuit 03 in the other stage driving unit 00 in a forward direction, or the signal received by the input terminal D of the output circuit 03 in the other stage driving unit 00 is transmitted to the input terminal D of the output circuit 03 in the current stage driving unit 00 in a reverse direction. The first input control circuit 01 and the third input control circuit 05 may control the input terminal D of the output circuit 03 in the current stage driving unit 00 to be disconnected from the input terminal D of the output circuit 03 in the other stage driving unit 00 when the potential of the synchronous light emission control signal is the second potential. At this time, the signal received by the input terminal D of the output circuit 03 in the current stage driving unit 00 cannot be transmitted to the input terminal D of the output circuit 03 in the other stage driving unit 00, and the signal received by the input terminal D of the output circuit 03 in the other stage driving unit 00 cannot be transmitted to the input terminal D of the output circuit 03 in the current stage driving unit 00. The signals here may all refer to the luminescence signal EM.

That is, the first input control circuit 01 and the third input control circuit 05 may jointly respond to the synchronous light Emission control signal to control the forward transmission and the backward transmission of the signal (e.g., the light Emission signal EM) received by the input terminal D of the output circuit 03 in the driving unit 00 of each cascaded stage, so as to realize Global Emission while being compatible with the forward and backward scanning functions. The positive and negative scanning functions include a positive scanning function and a negative scanning function, the positive scanning function may refer to transmitting signals along a direction from a first row of pixels to a last row of pixels to scan a plurality of rows of pixels, and the negative scanning function may refer to transmitting signals along a direction from a last row of pixels to a first row of pixels to scan a plurality of rows of pixels.

The first normal scan control circuit 06 and the first reverse scan control circuit 07 may be both connected between the first input control circuit 01 and the third input control circuit 05, and the first normal scan control circuit 06 may be further connected to the normal scan control terminal gsd_fw, and the first reverse scan control circuit 07 may be further connected to the reverse scan control terminal gsd_bw. The first positive scan control circuit 06 may be configured to control on-off of the first input control circuit 01 and the third input control circuit 05 in response to a positive scan control signal provided by the positive scan control terminal gsd_fw, so that a signal received by the input terminal D of the output circuit 03 is sequentially transmitted to the input terminals of the other stage driving units 00 through the first input control circuit 01 and the third input control circuit 05. The first reverse scan control circuit 07 may be configured to control on-off of the first input control circuit 01 and the third input control circuit 05 in response to a reverse scan control signal provided by the reverse scan control terminal gsd_bw, so that signals received by the input terminals of the other stage driving units 00 are sequentially transmitted to the input terminal D of the output circuit 03 through the third input control circuit 05 and the first input control circuit 01.

For example, the first positive scan control circuit 06 may control the first input control circuit 01 and the third input control circuit 05 to be turned on when the electric potential of the positive scan control signal provided by the positive scan control terminal gsd_fw is the first electric potential, so that the signal received by the input terminal D of the output circuit 03 in the current stage driving unit 00 is sequentially transmitted to the input terminal D of the output circuit 03 in the other stage driving unit 00 through the first input control circuit 01 and the third input control circuit 05, and may control the first input control circuit 01 and the third input control circuit 05 to be disconnected when the electric potential of the positive scan control signal provided by the positive scan control terminal gsd_fw is the second electric potential, and at this time, the signal received by the input terminal D of the output circuit 03 in the current stage driving unit 00 cannot be sequentially transmitted to the input terminal D of the output circuit 03 in the other stage driving unit 00 through the first input control circuit 01 and the third input control circuit 05.

Similarly, the first reverse scan control circuit 07 may control the first input control circuit 01 to be turned on with the third input control circuit 05 when the electric potential of the reverse scan control signal provided by the reverse scan control terminal gsd_bw is the first electric potential, so that the signal received by the input terminal D of the output circuit 03 in the other stage driving unit 00 is sequentially transmitted to the input terminal D of the output circuit 03 in the current stage driving unit 00 through the third input control circuit 05 and the first input control circuit 01, and may control the first input control circuit 01 to be disconnected from the third input control circuit 05 when the electric potential of the reverse scan control signal provided by the reverse scan control terminal gsd_bw is the second electric potential, and at this time, the signal received by the input terminal D of the output circuit 03 in the other stage driving unit 00 cannot be sequentially transmitted to the input terminal D of the output circuit 03 in the current stage driving unit 00 through the third input control circuit 05 and the first input control circuit 01.

That is, under the control of the first normal-scan control circuit 06 and the first reverse-scan control circuit 07, the normal-scan and reverse-scan can be realized in cooperation with the first input control circuit 01 and the third input control circuit 05, and the signal transmission paths under the normal-scan and reverse-scan are independent from each other. The signal transmission path under the normal scan is that the signal is transmitted through the input end D of the output circuit 03 in the current stage driving unit 00 and then transmitted to the input end D of the output circuit 03 in the other stage driving unit 00 through the first input control circuit 01, the first normal scan control circuit 06 and the third input control circuit 05 in sequence. The signal transmission path under the reverse scanning is that the signal is transmitted into the input end D of the output circuit 03 in the driving unit 00 of the other stage and then transmitted to the input end D of the output circuit 03 in the driving unit 00 of the current stage through the third input control circuit 05, the first reverse scanning control circuit 07 and the first input control circuit 01 in sequence. The design can relatively avoid crosstalk of signals transmitted in normal scanning and reverse scanning from the perspective of signal transmission, so that the signal transmission efficiency of a circuit in operation is improved.

Wherein, in the same period, the potential of the reverse scan control signal is opposite to the potential of the normal scan control signal. That is, when the potential of the normal scan control signal is the first potential, the potential of the reverse scan control signal may be the second potential, whereas when the potential of the normal scan control signal is the second potential, the potential of the reverse scan control signal may be the first potential. As described above, in the above example, when the first forward-scan control circuit 06 controls the first input control circuit 01 to be turned on and the third input control circuit 05 to perform forward-scan, the first backward-scan control circuit 07 may control the first input control circuit 01 to be disconnected from the third input control circuit 05, and when the first backward-scan control circuit 07 controls the first input control circuit 01 to be turned on and the third input control circuit 05 to perform backward-scan, the first forward-scan control circuit 06 may control the first input control circuit 01 to be disconnected from the third input control circuit 05. That is, it is possible to make either a normal scan or a reverse scan in one period and while Global Emission is being achieved.

Alternatively, as can be seen with continued reference to fig. 5, the first input control circuit 01 and the third input control circuit 05 may also be connected to a sequential emission control terminal en_global'. And, the first input control circuit 01 and the third input control circuit 05 may be used to control the on-off of the input terminal D of the output circuit 03 and the input terminal of the other stage driving unit 00 in response to the synchronous light emission control signal and the sequential light emission control signal.

For example, the first input control circuit 01 and the third input control circuit 05 may control the input terminal D of the output circuit 03 in the current stage driving unit 00 to be turned on with the input terminal D of the output circuit 03 in the other stage driving unit 00 when the potential of the synchronous light emission control signal and/or the potential of the sequential light emission control signal are the first potential, and may control the input terminal D of the output circuit 03 in the current stage driving unit 00 to be disconnected with the input terminal D of the output circuit 03 in the other stage driving unit 00 when the potential of the synchronous light emission control signal and the potential of the sequential light emission control signal are both the second potential.

That is, the first input control circuit 01 and the third input control circuit 05 may control the on-off of the input terminal D of the output circuit 03 in the current stage driving unit 00 and the input terminal D of the output circuit 03 in the other stage driving unit 00 under the control of the two control signals, i.e., the synchronous light emission control signal and the sequential light emission control signal. In this way, control reliability and flexibility can be improved.

Alternatively, in some embodiments, the potential of the synchronous light emission control signal and the potential of the sequential light emission control signal may be exactly opposite potentials. That is, assuming that the first potential (i.e., the effective potential) of the synchronous light emission control signal is a high potential, the first potential (i.e., the effective potential) of the sequential light emission control signal may be a low potential. The first potential (i.e., the effective potential) of the sequential light emission control signal may be a high potential assuming that the first potential (i.e., the effective potential) of the synchronous light emission control signal is a low potential. On this basis, in some embodiments, only the synchronous light-emitting control terminal en_global may be set, and then an inverter is further set to invert the synchronous light-emitting control signal provided by the synchronous light-emitting control terminal en_global to obtain the required sequential light-emitting control signal, without setting the sequential light-emitting control terminal en_global additionally. Or only the sequential light-emitting control terminal en_global 'may be set, and then an inverter is set to invert the sequential light-emitting control signal provided by the sequential light-emitting control terminal en_global' to obtain the required synchronous light-emitting control signal, without setting the synchronous light-emitting control terminal en_global additionally. In this way, the number of signal terminals to be provided can be simplified, thereby facilitating wiring.

Alternatively, as can be seen with continued reference to fig. 5, the first normal scan control circuit 06 may also be connected to the reverse scan control terminal gsd_bw. And, the first positive scan control circuit 06 may be configured to control on-off of the first input control circuit 01 and the third input control circuit 05 in response to the positive scan control signal and the negative scan control signal.

The first positive scan control circuit 06 may control the first input control circuit 01 and the third input control circuit 05 to be turned on when the potential of the positive scan control signal and/or the potential of the negative scan control signal is the first potential, and may control the first input control circuit 01 and the third input control circuit 05 to be turned off when the potential of the positive scan control signal and the potential of the negative scan control signal are both the second potentials, for example. That is, as with the first input control circuit 01 and the third input control circuit 05, the first positive scan control circuit 06 may control the on/off of the first input control circuit 01 and the third input control circuit 05 under the control of the positive scan control signal and the negative scan control signal. In this way, control reliability and flexibility can be improved.

Alternatively, as can be seen with continued reference to fig. 5, the first reverse scan control circuit 07 may also be connected to the forward scan control terminal gsd_fw. And, the first reverse scan control circuit 07 may be used to control the on-off of the first input control circuit 01 and the third input control circuit 05 in response to the forward scan control signal and the reverse scan control signal.

The first reverse scan control circuit 07 may control the first input control circuit 01 and the third input control circuit 05 to be turned on when the potential of the forward scan control signal and/or the potential of the reverse scan control signal is a first potential, and may control the first input control circuit 01 and the third input control circuit 05 to be turned off when the potential of the forward scan control signal and the potential of the reverse scan control signal are both second potentials, for example. That is, as with the first normal scan control circuit 06, the first reverse scan control circuit 07 may control the on/off of the first input control circuit 01 and the third input control circuit 05 under the control of the two control signals, i.e., the normal scan control signal and the reverse scan control signal. In this way, control reliability and flexibility can be improved.

Alternatively, in some embodiments, the potential of the normal scan control signal and the potential of the reverse scan control signal may be exactly opposite potentials. That is, assuming that the first potential (i.e., the effective potential) of the normal scan control signal is a high potential, the first potential (i.e., the effective potential) of the reverse scan control signal may be a low potential. Assuming that the first potential (i.e., the effective potential) of the normal scan control signal is a low potential, the first potential (i.e., the effective potential) of the reverse scan control signal may be a high potential. On this basis, in some embodiments, only the normal scan control terminal gsd_fw may be set, and then an inverter is set to invert the normal scan control signal provided by the normal scan control terminal gsd_fw to obtain the required reverse scan control signal, without setting the reverse scan control terminal gsd_bw additionally. Or only the reverse scanning control end GSD_BW is arranged, then an inverter is arranged to carry out reverse phase treatment on the reverse scanning control signal provided by the reverse scanning control end GSD_BW to obtain the required normal scanning control signal, and the normal scanning control end GSD_FW is not required to be additionally arranged. In this way, the number of signal terminals to be provided can be simplified, thereby facilitating wiring.

It will be appreciated that the potentials of the positive scan control signals received by the first positive scan control circuit 06 and the first negative scan control circuit 07 may be exactly opposite, and the potentials of the received negative scan control signals may also be exactly opposite. That is, assuming that the first potential of the positive-going scan control signal received by the first positive-going scan control circuit 06 is a high potential and the first potential of the negative-going scan control signal received is a low potential, the first potential of the positive-going scan control signal received by the first negative-going scan control circuit 07 may be a low potential and the first potential of the negative-going scan control signal received may be a high potential. Assuming that the second potential of the normal scan control signal received by the first normal scan control circuit 06 is a low potential and the second potential of the reverse scan control signal received by the first reverse scan control circuit 07 is a high potential, the second potential of the normal scan control signal received by the first reverse scan control circuit 07 may be a high potential and the second potential of the reverse scan control signal received by the first reverse scan control circuit may be a low potential. In this way, only one of the first normal scan control circuit 06 and the first reverse scan control circuit 07 can control the first input control circuit 01 and the third input control circuit 05 to be turned on in one period, so that normal scan or reverse scan is realized.

For example, with 1 representing high potential, 0 representing low potential, and the first potential of the positive scan control signal received by the first positive scan control circuit 06 being high potential 1, the first potential of the negative scan control signal received by the first negative scan control circuit 07 being low potential 0, and the first potential of the negative scan control signal received by the first negative scan control circuit 07 being high potential 1, the following table 1 schematically shows a truth table of positive scan control signals provided by the positive scan control terminal gsd_fw and negative scan control signals provided by the negative scan control terminal gsd_bw when positive and negative scan are implemented:

TABLE 1

Signal Name	Value Case1	Value Case2
			GSD_FW	1	0
GSD_BW	0	1
			Scan State	Forward Scan	Backward Scan

As can be seen from table 1 and the above description, when the potential of the normal scan control signal provided by the normal scan control terminal gsd_fw is a high potential 1 and the potential of the reverse scan control signal provided by the reverse scan control terminal gsd_bw is a low potential 0, the first normal scan control circuit 06 can control the first input control circuit 01 and the third input control circuit 05 to be turned on, so that the signal received by the input terminal D of the output circuit 03 in the current stage driving unit 00 is sequentially transmitted to the input terminal D of the output circuit 03 in the other stage driving unit 00 in the forward direction through the first input control circuit 01, the first normal scan control circuit 06 and the third input control circuit 05, thereby realizing the normal scan. That is, in the first Value Case1 mode, GSD_FW=1 and GSD_BW=0, the scanning mode (SCAN STATE) may be a Forward Scan. At this time, the first reverse scan control circuit 07 may control the first input control circuit 01 and the third input control circuit 05 to be disconnected.

When the potential of the positive scan control signal provided by the positive scan control terminal gsd_fw is a low potential 0 and the potential of the negative scan control signal provided by the negative scan control terminal gsd_bw is a high potential 1, the first negative scan control circuit 07 may control the first input control circuit 01 and the third input control circuit 05 to be turned on, so that the signals received by the input terminal D of the output circuit 03 in the other stage driving unit 00 are reversely transmitted to the input terminal D of the output circuit 03 in the current stage driving unit 00 through the third input control circuit 05, the first negative scan control circuit 07 and the first input control circuit 01 in sequence, and negative scan is achieved. That is, in the second Value Case2 mode, GSD_FW=0 and GSD_BW=1, the scanning mode (SCAN STATE) may be a reverse Scan (Backward Scan). At this time, the first normal scan control circuit 06 may control the first input control circuit 01 and the third input control circuit 05 to be disconnected.

Alternatively, as can be seen with continued reference to fig. 6 on the basis of fig. 5, the first input control circuit 01 may comprise a first transmission gate TG1. The third input control circuit 05 may include a second transmission gate TG2. The first normal scan control circuit 06 may include a third transmission gate TG3 and a fourth transmission gate TG4. The first reverse scan control circuit 07 may include a fifth transmission gate TG5 and a sixth transmission gate TG6.

The control terminal T & T ' of the first transmission gate TG1 and the control terminal T & T ' of the second transmission gate TG2 may be connected to the synchronous light emission control terminal en_global and the sequential light emission control terminal en_global ', respectively. The control terminals T & T 'of the third to sixth transmission gates TG3 to T & T' of the sixth transmission gate TG6 may be connected to the normal scan control terminal gsd_fw and the reverse scan control terminal gsd_bw, respectively. The input terminal IN of the first transmission gate TG1 may be connected to an input terminal D (not shown IN the figure) of the output circuit 03. The output terminal OUT of the first transmission gate TG1 may be connected to the input terminal IN of the third transmission gate TG3 and the output terminal OUT of the fifth transmission gate TG5, the output terminal OUT of the third transmission gate TG3 may be connected to the input terminal IN of the fourth transmission gate TG4, the input terminal IN of the fifth transmission gate TG5 may be connected to the output terminal OUT of the sixth transmission gate TG6, the output terminal OUT of the fourth transmission gate TG4 and the input terminal IN of the sixth transmission gate TG6 may be connected to the output terminal OUT of the second transmission gate TG2, and the input terminal IN of the second transmission gate TG2 may be connected to the input terminal (not shown) of the other stage driving unit 00.

It is understood that the transmission gate generally includes an N-type transistor and a P-type transistor in parallel. On this basis, the control terminal T of the transfer gate may refer to a gate of an N-type transistor therein, the control terminal T' of the transfer gate may refer to a gate of a P-type transistor therein, the input terminal IN of the transfer gate may refer to a first pole of the N-type transistor and a first pole of the P-type transistor connected IN parallel, and the output terminal OUT of the transfer gate may refer to a second pole of the N-type transistor and a second pole of the P-type transistor connected IN parallel.

On the basis, as can be seen from the description of the above embodiments and fig. 6, the control terminal T of the first transmission gate TG1 and the control terminal T of the second transmission gate TG2 may be connected to the synchronous light emission control terminal en_global, and the control terminal T ' of the first transmission gate TG1 and the control terminal T ' of the second transmission gate TG2 may be connected to the sequential light emission control terminal en_global '. Among the third transmission gate TG3 and the fourth transmission gate TG4 included in the first normal scan control circuit 06, the control terminal T of each transmission gate may be connected to the normal scan control terminal gsd_fw, and the control terminal T' of each transmission gate may be connected to the reverse scan control terminal gsd_bw. The first reverse scan control circuit 07 includes a fifth transmission gate TG5 and a sixth transmission gate TG6, a control terminal T of each of which may be connected to the reverse scan control terminal gsd_bw, and a control terminal T' of each of which may be connected to the normal scan control terminal gsd_fw. In this way, only one control circuit of the first normal scan control circuit 06 and the first reverse scan control circuit 07 can control the first input control circuit 01 and the third input control circuit 05 to be turned on in the same period, so as to realize normal scan or reverse scan.

Optionally, as can be seen with continued reference to fig. 6, the driving unit 00 may further comprise a first enhancement circuit 08 and/or a second enhancement circuit 09.

The first boosting circuit 08 may be connected between the third and fourth transmission gates TG3 and TG4. The first enhancement circuit 08 may be configured to enhance the signal output from the third transmission gate TG3 and then transmit the signal to the fourth transmission gate TG4. In this way, the problem of attenuation existing when the signal is transmitted to the fourth transmission gate TG4 through the third transmission gate TG3 can be solved, and thus the signal received by the current stage driving unit 00 can be ensured to be reliably transmitted to the other stage driving units 00 through the third transmission gate TG 3.

The second enhancement circuit 09 may be connected between the fifth transmission gate TG5 and the sixth transmission gate TG 6. The second enhancement circuit 09 may be configured to perform enhancement processing on the signal output from the sixth transmission gate TG6 and then transmit the signal to the fifth transmission gate TG5. In this way, the problem of attenuation occurring when the signal is transmitted to the fifth transmission gate TG5 through the sixth transmission gate TG6 can be solved, and thus it can be ensured that the signal received by the other stage driving unit 00 is reliably transmitted to the current stage driving unit 00 through the sixth transmission gate TG 6.

Alternatively, as can be seen with continued reference to FIG. 7 on the basis of FIG. 6, the first enhancement circuit 08 may include an even number of first inverters F1 in series. The second boost circuit 09 may include an even number of second inverters F2 connected in series.

The input terminal IN of the even number of first inverters F1 connected IN series may be connected to the output terminal OUT of the third transmission gate TG3, and the output terminal OUT of the even number of first inverters F1 connected IN series may be connected to the input terminal IN of the fourth transmission gate TG 4.

An even number of the input terminals IN of the second inverters F2 connected IN series may be connected to the output terminal OUT of the sixth transmission gate TG6, and an even number of the output terminals OUT of the second inverters F2 connected IN series may be connected to the input terminal IN of the fifth transmission gate TG 5.

Of course, the even number of first inverters F1 connected IN series may mean that the input terminal IN of each adjacent two of the first inverters F1 is connected to the output terminal OUT. Similarly, the even number of second inverters F2 connected IN series may also mean that the input terminal IN of each adjacent two of the second inverters F2 is connected to the output terminal OUT.

Thus, by providing an even number of first inverters F1 connected in series and an even number of second inverters F2 connected in series, the purpose of reliably enhancing the signal can be achieved. Of course, in some other embodiments, an even number of first inverters F1 connected in series may be replaced by a buffer (buffer), which may also serve the purpose of signal enhancement. An even number of second inverters F2 connected in series can be replaced in the same way.

Alternatively, the number of first inverters F1 included in the first enhancement circuit 08 and the number of second inverters F2 included in the second enhancement circuit 09 may be the same. Therefore, the enhancement effect of the transmitted signals can be kept consistent during normal scanning and reverse scanning, and the display uniformity during normal scanning and reverse scanning is good. Of course, the number of first inverters F1 included in the first enhancement circuit 08 and the number of second inverters F2 included in the second enhancement circuit 09 may also be different. By way of example, fig. 7 schematically shows 2 first inverters F1 in series and 2 second inverters F2 in series.

As can be seen from the foregoing description, the partial structures shown in fig. 5 to 7 can control the light emitting signal EM to be simultaneously transmitted to the input terminal D of the output circuit 03 (e.g., DFF) in the driving unit 00 of each cascaded stage, without sequentially transmitting the light emitting signal EM after passing through the DFF. Therefore, the light-emitting signals EM can enter the output circuits 03 in the driving units 00 at all levels at the same time, so that the output circuits 03 in the driving units 00 at all levels can be synchronously processed, and finally, the light-emitting signals EM output to the pixels by the driving units 00 at all levels in cascade can be synchronously kept, so that the display panel can synchronously emit light and display the whole surface, namely, the display panel works in a Global Emission mode. Accordingly, the partial structures shown in fig. 5 to 7 may also be referred to as data transmission control modules.

In addition, the third input control circuit 05, the first normal scan control circuit 06, and the first reverse scan control circuit 07 (i.e., the structure formed by the transmission gate and the inverter) may be matched to be compatible with the normal scan function on the basis of controlling the display panel to operate in the Global Emission mode. And, during normal display, only one state of normal or reverse scan exists.

For example, in connection with fig. 7, in the normal scan state, the signal transmission path may be the path (1) shown in fig. 7. That is, the light emission signal EM may be introduced from above, first through a first transmission gate TG1 controlled by en_global=1, then through a third transmission gate TG3 controlled by gsd_fw=1, then two first inverters F1 connected in series may enhance the light emission signal EM to avoid attenuation of the light emission signal EM, and finally, through a fourth transmission gate TG4 controlled by gsd_fw=1 and then through a second transmission gate TG2 controlled by en_global=1. The fourth transmission gate TG4 may also be used to prevent the back flow of the emission signal EM to ensure a single path of signal transfer, i.e., to ensure either forward transfer or reverse transfer of the emission signal EM. In the reverse scan state, the signal transmission path may be the path (2) shown in fig. 7, the number of devices through which the light emission signal EM passes is the same, and the functions of the devices are the same, except that the light emission signal EM is transmitted from below at this time, and gsd_bw=1.

Here, en_global=1 may refer to that the first potential of the synchronous light emission control signal provided by the synchronous light emission control terminal en_global is a high potential 1, gsd_fw=1 may refer to that the first potential of the positive scan control signal provided by the positive scan control terminal gsd_fw is a high potential 1, and gsd_bw=1 may refer to that the first potential of the negative scan control signal provided by the negative scan control terminal gsd_bw is a high potential 1.

Optionally, in some embodiments, the third transmission gate TG3, the fourth transmission gate TG4 and the even number of first inverters F1 connected in series on the forward path (1) may be replaced by a tri-state buffer, which may also serve the purpose of controlling the forward path. The fifth transmission gate TG5, the sixth transmission gate TG6, and an even number of second inverters F2 connected in series on the forward path (1) can be replaced similarly.

Alternatively, fig. 8 is a schematic structural view of another part of a driving unit 00 according to an embodiment of the present application. As shown in fig. 8, the driving unit 00 may further include a fourth input control circuit 10, a second normal scan control circuit 11, and a second reverse scan control circuit 12.

The fourth input control circuit 10 may be connected to the sequential emission control terminal en_global', the input terminal D of the output circuit 03, and the output terminal of the other stage driving unit 00, respectively. And, the fourth input control circuit 10 may be configured to control on-off of the output terminal of the other stage driving unit 00 and the input terminal D of the output circuit 03 in response to the sequential light emission control signal, so that the signal output from the output terminal of the other stage driving unit 00 is transmitted to the input terminal D of the output circuit 03.

It will be appreciated that, in connection with fig. 8, the output terminal of the other stage driving unit 00 according to the embodiment of the present application may refer to the output terminal Q of the output circuit 03 in the other stage driving unit 00. Of course, the output terminals of the other stage driving units 00 may be referred to herein as intermediate state terminals q_inter of the output circuits 03 in the other stage driving units 00, on the basis that the output circuits 03 are double edge D flip-flops DFF. Fig. 8 identifies this as q_ INTERn +1, indicating that the other stage driving unit 00 is the n+1th stage driving unit 00.

On the basis of this, the fourth input control circuit 10 may control the output terminal Q of the output circuit 03 in the other stage driving unit 00 to be conductive to the input terminal D of the output circuit 03 in the current stage driving unit 00 when the potential of the sequential light emission control signal is the first potential so that the signal output from the output terminal Q of the output circuit 03 in the other stage driving unit 00 is transmitted to the input terminal D of the output circuit 03 in the current stage driving unit 00, and may control the output terminal Q of the output circuit 03 in the other stage driving unit 00 to be disconnected from the input terminal D of the output circuit 03 in the current stage driving unit 00 when the potential of the sequential light emission control signal is the second potential, at which time the signal output from the output terminal Q of the output circuit 03 in the other stage driving unit 00 cannot be transmitted to the input terminal D of the output circuit 03 in the current stage driving unit 00.

That is, the second input control circuit 02 and the fourth input control circuit 10 may control the forward transmission and the backward transmission of the signal (e.g., the light emitting signal EM) output from the output terminal Q of the output circuit 03 in each of the cascaded driving units 00 in response to the sequential light emitting control signal provided from the sequential light emitting control terminal en_global', respectively, so as to realize Sequential Emission and also be compatible with the forward and backward scanning functions.

The second positive scan control circuit 11 may be connected between the output terminal Q (e.g., the intermediate state terminal q_inter) of the output circuit 03 and the second input control circuit 02, and may also be connected to the positive scan control terminal gsd_fw. The second positive scan control circuit 11 may be configured to control on-off of the output terminal Q of the output circuit 03 and the second input control circuit 02 in response to a positive scan control signal provided by the positive scan control terminal gsd_fw, so that a signal output by the output terminal Q of the output circuit 03 is transmitted to the input terminal of the other stage driving unit 00 through the second input control circuit 02.

For example, the second positive scan control circuit 11 may control the output terminal Q of the output circuit 03 in the current stage driving unit 00 to be conductive to the second input control circuit 02 when the electric potential of the positive scan control signal provided by the positive scan control terminal gsd_fw is the first electric potential, so that the signal output from the output terminal Q of the output circuit 03 in the current stage driving unit 00 is transmitted to the input terminal D of the output circuit 03 in the other stage driving unit 00 via the second input control circuit 02, and may control the output terminal Q of the output circuit 03 in the current stage driving unit 00 to be disconnected from the second input control circuit 02 when the electric potential of the positive scan control signal provided by the positive scan control terminal gsd_fw is the second electric potential, and at this time, the signal output from the output terminal Q of the output circuit 03 in the current stage driving unit 00 cannot be transmitted to the input terminal D of the output circuit 03 in the other stage driving unit 00 via the second input control circuit 02.

The second reverse scan control circuit 12 may be connected between the input terminal D of the output circuit 03 and the fourth input control circuit 10, and may also be connected with the reverse scan control terminal gsd_bw. The second reverse scan control circuit 12 may be configured to control on-off of the input terminal D of the output circuit 03 and the fourth input control circuit 10 in response to a reverse scan control signal provided by the reverse scan control terminal gsd_bw, so that signals output by the output terminals of the other stage driving units 00 are transmitted to the input terminal D of the output circuit 03 through the fourth input control circuit 10.

For example, the second reverse scan control circuit 12 may control the input terminal D of the output circuit 03 in the current stage driving unit 00 to be connected to the fourth input control circuit 10 when the potential of the reverse scan control signal provided by the reverse scan control terminal gsd_bw is the first potential, so that the signal output from the output terminal Q (e.g., the intermediate state terminal q_ INTERn +1) of the output circuit 03 in the other stage driving unit 00 is transmitted to the input terminal D of the output circuit 03 in the current stage driving unit 00 via the fourth input control circuit 10, and may control the input terminal D of the output circuit 03 in the current stage driving unit 00 to be disconnected from the fourth input control circuit 10 when the potential of the reverse scan control signal provided by the reverse scan control terminal gsd_bw is the second potential, and at this time, the signal output from the output terminal Q of the output circuit 03 in the other stage driving unit 00 is not transmitted to the input terminal D of the output circuit 03 in the current stage driving unit 00 via the fourth input control circuit 10.

That is, under the control of the second normal-scan control circuit 11 and the second reverse-scan control circuit 12, the normal-scan and reverse-scan can be realized in cooperation with the second input control circuit 02 and the fourth input control circuit 10, and the signal transmission paths under the normal-scan and reverse-scan are independent of each other. The signal transmission path under the normal scan is that the signal is transmitted in through the output end Q of the output circuit 03 in the current stage driving unit 00 and then transmitted to the input end D of the output circuit 03 in the other stage driving unit 00 through the second normal scan control circuit 11 and the second input control circuit 02 in sequence. The signal transmission path under the reverse scanning is that the signal is transmitted in through the output end Q of the output circuit 03 in the driving unit 00 of the other stage and then transmitted to the input end D of the output circuit 03 in the driving unit 00 of the current stage through the fourth input control circuit 10 and the second reverse scanning control circuit 12 in sequence. Similarly, the design can relatively avoid crosstalk of signals transmitted in normal and reverse scanning from the perspective of signal transmission, so that the signal transmission efficiency of the circuit in operation is improved.

As described above, the potential of the reverse scan control signal is opposite to the potential of the normal scan control signal in the same period. As described above, in the above example, when the second normal scan control circuit 11 controls the output terminal Q of the output circuit 03 in the current stage driving unit 00 to be connected to the second input control circuit 02, the second reverse scan control circuit 12 may control the input terminal D of the output circuit 03 in the current stage driving unit 00 to be disconnected from the fourth input control circuit 10, and when the second reverse scan control circuit 12 controls the input terminal D of the output circuit 03 in the current stage driving unit 00 to be connected to the fourth input control circuit 10, the second normal scan control circuit 11 may control the output terminal Q of the output circuit 03 in the current stage driving unit 00 to be disconnected from the second input control circuit 02. That is, it is possible to make either a normal scan or a reverse scan during one period and while Sequential Emission is being implemented.

Alternatively, as can be seen with continued reference to fig. 8, the second input control circuit 02 and the fourth input control circuit 10 may also each be connected to a sequential light-emitting control terminal en_global'. And, the second input control circuit 02 may be configured to control on-off of the output terminal Q of the output circuit 03 and the input terminal of the other stage driving unit 00 in response to the synchronous light emission control signal and the sequential light emission control signal. The fourth input control circuit 10 may be configured to control on-off of the output terminal of the other stage driving unit 00 and the input terminal D of the output circuit 03 in response to the synchronous light emission control signal and the sequential light emission control signal.

For example, the second input control circuit 02 may control the output terminal Q of the output circuit 03 in the current stage driving unit 00 to be on with the input terminal D of the output circuit 03 in the other stage driving unit 00 when the potential of the synchronous light emission control signal and/or the potential of the sequential light emission control signal are at the first potential, and may control the output terminal Q of the output circuit 03 in the current stage driving unit 00 to be disconnected with the input terminal D of the output circuit 03 in the other stage driving unit 00 when the potential of the synchronous light emission control signal and the potential of the sequential light emission control signal are both at the second potential.

Likewise, the fourth input control circuit 10 may control the output terminal Q of the output circuit 03 in the other stage driving unit 00 to be on with the input terminal D of the output circuit 03 in the current stage driving unit 00 when the potential of the synchronous light emission control signal and/or the potential of the sequential light emission control signal are the first potential, and may control the output terminal Q of the output circuit 03 in the other stage driving unit 00 to be off with the input terminal D of the output circuit 03 in the current stage driving unit 00 when both the potential of the synchronous light emission control signal and the potential of the sequential light emission control signal are the second potential.

That is, the second input control circuit 02 and the fourth input control circuit 10 may control the on/off of the two ends connected under the control of the two control signals, i.e., the synchronous light emission control signal and the sequential light emission control signal, like the first input control circuit 01 and the third input control circuit 05. In this way, control reliability and flexibility can be improved.

It will be appreciated that the potential of the synchronous light emission control signal received by each of the second input control circuit 02 and the fourth input control circuit 10 may be exactly opposite to the potential of the synchronous light emission control signal received by each of the first input control circuit 01 and the second input control circuit 02, and the potential of the received sequential light emission control signals may also be exactly opposite.

That is, taking the first input control circuit 01 and the second input control circuit 02 as an example for comparison, assuming that the first potential of the synchronous light emission control signal received by the first input control circuit 01 is high and the first potential of the sequential light emission control signal received by the first input control circuit is low, the first potential of the synchronous light emission control signal received by the second input control circuit 02 may be low and the first potential of the sequential light emission control signal received by the second input control circuit 02 may be high. Assuming that the second potential of the synchronous light emission control signal received by the first input control circuit 01 is a low potential and the second potential of the received sequential light emission control signal is a high potential, the second potential of the synchronous light emission control signal received by the second input control circuit 02 may be a high potential and the second potential of the received sequential light emission control signal may be a low potential. In this way, only one of the first input control circuit 01 and the second input control circuit 02 controls the connection of the two ends to be conducted in a period of time, so as to realize Global transmission or Sequential Emission.

In other words, in the embodiment of the present application, a synchronous light Emission control terminal en_global may be configured to provide a synchronous light Emission control signal to switch the GLOBAL Emission mode and the Sequential Emission mode. For example, the GLOBAL Emission mode is defined as en_global=1, and the Sequential Emission mode is defined as en_global=0. Here, en_global=1 may mean that the potential of the synchronous light emission control signal provided by the synchronous light emission control terminal en_global is a high potential 1, and en_global=0 may mean that the potential of the synchronous light emission control signal provided by the synchronous light emission control terminal en_global is a low potential 0.

Alternatively, as can be seen with continued reference to fig. 8, the second normal scan control circuit 11 may also be connected to the reverse scan control terminal gsd_bw. And, the second positive scan control circuit 11 may be configured to control on-off of the output terminal Q of the output circuit 03 and the second input control circuit 02 in response to the positive scan control signal and the negative scan control signal.

The second positive scan control circuit 11 may control the output terminal Q of the output circuit 03 in the current stage driving unit 00 to be connected to the second input control circuit 02 when the potential of the positive scan control signal and/or the potential of the negative scan control signal is the first potential, and may control the output terminal Q of the output circuit 03 in the current stage driving unit 00 to be disconnected from the second input control circuit 02 when the potential of the positive scan control signal and the potential of the negative scan control signal are both the second potentials, for example. That is, as with the first positive scan control circuit 06, the second positive scan control circuit 11 may control the on/off of the output terminal Q of the output circuit 03 and the second input control circuit 02 in the current stage driving unit 00 under the control of the positive scan control signal and the negative scan control signal. In this way, control reliability and flexibility can be improved.

Alternatively, as can be seen with continued reference to fig. 8, the second reverse scan control circuit 12 may also be connected to the positive scan control terminal gsd_fw. And, the second reverse scan control circuit 12 may be configured to control the on-off of the input terminal D of the output circuit 03 and the fourth input control circuit 10 in response to the forward scan control signal and the reverse scan control signal.

The second reverse scan control circuit 12 may control the input terminal D of the output circuit 03 in the current stage driving unit 00 to be turned on with the fourth input control circuit 10 when the potential of the forward scan control signal and/or the potential of the reverse scan control signal is the first potential, and may control the input terminal D of the output circuit 03 in the current stage driving unit 00 to be turned off with the fourth input control circuit 10 when both the potential of the forward scan control signal and the potential of the reverse scan control signal are the second potential, for example. That is, as with the second reverse scanning circuit 07, the second reverse scanning control circuit 12 may control the on/off of the input terminal D of the output circuit 03 and the fourth input control circuit 10 in the current stage driving unit 00 under the control of the two control signals, i.e., the normal scanning control signal and the reverse scanning control signal. In this way, control reliability and flexibility can be improved.

It will be appreciated that the potentials of the positive scan control signals received by the second positive scan control circuit 11 and the second negative scan control circuit 12 may be exactly opposite, and the potentials of the received negative scan control signals may also be exactly opposite. The potentials of the positive scan control signals received by the second positive scan control circuit 11 and the first positive scan control circuit 06 may be the same, and the potentials of the negative scan control signals received by the second negative scan control circuit 12 and the first negative scan control circuit 07 may be the same, and the potentials of the negative scan control signals received by the negative scan control circuit 07 may be the same. The potential design may refer to the above description for the first normal scan control circuit 06 and the first reverse scan control circuit 07, and will not be described in detail herein. In this way, in the same time period, only one control circuit of the second normal scan control circuit 11 and the second reverse scan control circuit 12 controls the connection of the two ends to realize normal scan or reverse scan.

Alternatively, as can be seen with continued reference to fig. 9 on the basis of fig. 8, the second input control circuit 02 may include a seventh transmission gate TG7. The fourth input control circuit 10 may include an eighth transmission gate TG8. The second normal scan control circuit 11 may include a ninth transmission gate TG9. The second reverse scan control circuit 12 may include a tenth transmission gate TG10.

The control terminal T & T ' of the seventh transmission gate TG7 and the control terminal T & T ' of the eighth transmission gate TG8 may be connected to the synchronous light emission control terminal en_global and the sequential light emission control terminal en_global ', respectively. The control terminals T & T ' of the ninth to tenth transmission gates TG9 to T & T ' of the tenth transmission gate TG10 may be connected to the normal scan control terminal gsd_fw and the reverse scan control terminal ' gsd_bw, respectively. The input terminal IN of the seventh transmission gate TG7 may be connected to the output terminal OUT of the ninth transmission gate TG9, the output terminal OUT of the seventh transmission gate TG7 may be connected to the input terminal IN of the other stage driving unit 00, the input terminal IN of the ninth transmission gate TG9 may be connected to the output terminal OUT of the output circuit 03, the input terminal IN of the eighth transmission gate TG8 may be connected to the output terminal OUT of the other stage driving unit 00, the output terminal OUT of the eighth transmission gate TG8 may be connected to the input terminal IN of the tenth transmission gate TG10, and the output terminal OUT of the tenth transmission gate TG10 may be connected to the input terminal IN of the output circuit 03.

As can be seen from the foregoing description and fig. 9, the control terminal T of the seventh transmission gate TG7 and the control terminal T of the eighth transmission gate TG8 may be connected to the sequential emission control terminal en_global ', and the control terminal T ' of the seventh transmission gate TG7 and the control terminal T ' of the eighth transmission gate TG8 may be connected to the synchronous emission control terminal en_global. The control terminal T of the ninth transmission gate TG9 included in the second normal scan control circuit 11 may be connected to the normal scan control terminal gsd_fw, and the control terminal T 'may be connected to the reverse scan control terminal' gsd_bw. The control terminal T of the tenth transmission gate TG10 included in the second reverse scan control circuit 12 may be connected to the reverse scan control terminal gsd_bw, and the control terminal T 'may be connected to the positive scan control terminal' gsd_fw. In this way, only one control circuit of the second normal scan control circuit 11 and the second reverse scan control circuit 12 controls the connection of the two ends to realize normal scan or reverse scan in the same period. In addition, in the normal scanning scene, only one control circuit in the first input control circuit 01 and the second input control circuit 02 controls the connection of two ends to be conducted in the same period, so that Global Emission or Sequential Emission is realized. In the same way, under the reverse scanning scene, only one control circuit in the first input control circuit 01 and the fourth input control circuit 04 controls the connection of two ends to be conducted in the same period, so that Global Emission or Sequential Emission is realized.

Alternatively, as can be seen with continued reference to fig. 10 on the basis of fig. 9, the drive unit 00 may further comprise an inverter circuit 13.

The inverter circuit 13 may be adapted to be connected between an output Q of the output circuit 03 and a pixel (not shown). The inverter circuit 13 may be configured to invert the signal output from the output terminal Q of the output circuit 03 and transmit the signal to the pixel. Therefore, two signals with opposite potentials can be output to flexibly adapt to the potential requirements of the N-type transistor and the P-type transistor in the pixel, and the application scene is richer.

Alternatively, as can be seen with continued reference to FIG. 11 on the basis of FIG. 10, the inverter circuit 13 may include a third inverter F3.

The input terminal IN of the third inverter F3 may be connected to the output terminal Q of the output circuit 03, and the output terminal OUT of the third inverter F3 may be used for connection to a pixel.

Optionally, referring to fig. 3 to 11, it can also be seen that in the embodiment of the present application, the dual-edge D flip-flop DFF, each transmission gate and each inverter may further have a power supply terminal Vdd and a ground terminal GND, the power supply terminal Vdd may be used to receive a power supply signal, and the dual-edge D flip-flop DFF, each transmission gate and each inverter may be used to operate reliably under the control of the power supply signal.

It will be appreciated that, as is apparent from the foregoing description, the partial structures shown in fig. 8 to 11 can control the light-emitting signal EM to be sequentially transmitted to the input terminal D of the output circuit 03 (e.g., DFF) in the driving unit 00 of each cascaded stage, and then sequentially transmitted after passing through the DFF. In this way, the light-emitting signals EM can sequentially enter the output circuits 03 in the driving units 00 at all levels, so that the output circuits 03 in the driving units 00 at all levels are processed step by step, and finally the driving units 00 at all levels in cascade sequentially (e.g., row by row) output the light-emitting signals EM to the pixels at all levels, so that the pixels at all levels sequentially emit light, i.e., the display panel works in Sequential Emission mode. Accordingly, the partial structures shown in fig. 8 to 11 may also be referred to as signal shift register modules.

On the basis of controlling the display panel to work in Sequential Emission modes, the fourth input control circuit 10, the second normal scanning control circuit 11 and the second reverse scanning control circuit 12 can be matched for compatibility of normal scanning and reverse scanning functions. And, during normal display, only one state of normal or reverse scan exists.

For example, in connection with fig. 9, in the normal scan state, the signal transmission path may be the path (1) shown in fig. 9. That is, the light emission signal EM may be transmitted from above, first through a ninth transmission gate TG9 controlled by gsd_fw=1, and then transmitted through a seventh transmission gate TG7 controlled by en_global=0. In the reverse scan state, the signal transmission path may be the path (2) shown in fig. 9, the number of devices through which the light emission signal EM passes is the same, and the functions of the devices are the same, except that the light emission signal EM is transmitted from below at this time, and gsd_bw=1.

Alternatively, the module may include a DFF, a transmission gate, an and gate, and an inverter, as viewed from a circuit structure of the module. The upper two transfer gates (i.e., the ninth transfer gate TG9 and the tenth transfer gate TG 10) may serve as the normal/reverse scan control switch in the Sequential Emission mode, and the lower two transfer gates (i.e., the seventh transfer gate TG7 and the eighth transfer gate TG 8) may serve as the control switch for the control signal transfer or not in the Sequential Emission mode and the Global transmission mode. For example, in Sequential Emission mode, en_global=0, the seventh transmission gate TG7 corresponds to the on state, the Emission signal EM may be transmitted through the DFF post-stage, and in GLOBAL Emission mode, en_global=1, the seventh transmission gate TG7 corresponds to the off state, the Emission signal EM cannot be transmitted through the DFF post-stage. However, in either mode, the emission signal EM is output after passing through the AND gate AND.

Alternatively, fig. 12 schematically shows an overall circuit configuration diagram of a driving unit 00 in combination with fig. 7 and 11. In addition, as can be seen from fig. 12 and the foregoing description, the driving unit 00 in the gate driving circuit according to the embodiment of the application may mainly include two modules, namely, a data transmission control module and a signal shift register module. Under the control of the data transmission control module, the multi-stage driving unit 00 can simultaneously transmit the same light-emitting signal EM to a plurality of rows of pixels in the display panel in the same period, so that the display panel achieves the effect of whole-surface synchronous light-emitting display, i.e., the display panel can work in a Global Emission mode. Under the control of the signal shift register module, the multi-stage driving unit 00 can sequentially transmit the light emitting signals EM to the plurality of rows of pixels in the display panel row by row, so that the plurality of rows of pixels are sequentially lighted, i.e., the display panel can operate in Sequential Emission mode. And the display panel can be flexibly controlled to work in one of a Global Emission mode and a Sequential Emission mode in the same period. In addition, the embodiment of the application also maintains the positive and negative scanning function while supporting the display panel to work in the Global Emission mode and the Sequential Emission mode. The gate driving circuit can be suitable for more display product requirements.

By way of example, fig. 12 also illustrates schematically two signal transmission paths in Global transmission mode and in Sequential Emission mode, taking the normal scan as an example. As can be seen in conjunction with fig. 12, in Global transmission mode, signals can be transmitted via path a. That is, a signal may be input from the input terminal D of the double-edge D flip-flop DFF in the current stage driving unit 00 and sequentially output to the input terminal D of the double-edge D flip-flop DFF in the other stage driving unit 00 through the first transmission gate TG1, the third transmission gate TG3, the two first inverters F1, the fourth transmission gate TG4, and the second transmission gate TG 2. In Sequential Emission mode, signals may be transmitted via path B. That is, a signal may be input from the output terminal Q of the double-edge D flip-flop DFF in the current stage driving unit 00 and sequentially output to the input terminal D of the double-edge D flip-flop DFF in the other stage driving unit 00 through the ninth transmission gate TG9 and the seventh transmission gate TG 7.

As described above, when the control display panel is operated in the Global Emission mode, the light Emission time, the light Emission start point, and even the light Emission end point of the plurality of rows of pixels and even all the rows of pixels in the display panel can be kept uniform, that is, the whole-area pixels can be supported to simultaneously emit light for display, so that the problem of poor display effect caused by inconsistent light Emission time can be alleviated to a certain extent.

Alternatively, taking the structure shown in fig. 12 as an example, two adjacent stages of driving units 00 (1) and 00 (2) are cascaded, and each stage of driving unit 00 is connected to a row of pixels as an example, fig. 13 schematically shows a schematic diagram of a cascade circuit structure. Referring to fig. 13, it can be seen that in the Global Emission mode, the light Emission signals EM may be simultaneously transmitted to the input terminals D of the DFFs in the two-stage driving unit 00 through the left data transmission control module, so that the DFFs in the two-stage driving unit 00 can simultaneously output the light Emission signals EM received by the respective input terminals D through the respective output terminals Q when the rising edge of the clock signal comes, AND simultaneously output to the connected row of pixels after being processed through the AND gate AND logic included in each. Thus, two rows of pixels connected by the two-stage driving unit 00 can be simultaneously lighted for display. Where Line1 Output shown in fig. 13 means a light emission signal EM Output from the first stage driving unit 00 (1) to the connected 1 st Line pixel, and Line2 Output means a light emission signal EM Output from the second stage driving unit 00 (2) to the connected 2 nd Line pixel.

That is, as can be seen from the timing chart shown in fig. 14 again, in the Global Emission mode, the light Emission signals EM of the same potential can be simultaneously output to the plurality of rows of pixels, so that the plurality of rows of pixels can simultaneously start light Emission and simultaneously stop light Emission. Among them, fig. 14 schematically shows the light emission signals EM output to 10 lines (Line 1 to Line 10) of pixels.

It is understood that the gate driving circuit according to the embodiment of the present application is not limited to outputting the light emitting signal EM. For example, in some other embodiments, the GATE driving signal GATE may also be output.

The embodiment of the application also provides a driving method of the display panel, which is applied to the grid driving circuit described in the embodiment. As shown in fig. 15, the method includes:

In step 1501, in response to the synchronous light emitting instruction, the first input control circuit controls the input end of the output circuit to be conducted with the input ends of the other stage driving units in response to the synchronous light emitting control signal provided by the synchronous light emitting control end, so that the signals received by the input ends of the output circuit are transmitted to the input ends of the other stage driving units, and the output circuit in each stage driving unit synchronously outputs the received light emitting signals to the plurality of rows of pixels in the display panel through the output end after sampling the received light emitting signals based on the received clock signals, so as to synchronously light the plurality of rows of pixels.

In step 1502, in response to the sequential light-emitting instruction, the second input control circuit controls the on-off of the output end of the output circuit and the input end of the other stage driving unit in response to the sequential light-emitting control signal provided by the sequential light-emitting control end, so that the signal output by the output end of the output circuit is transmitted to the input end of the other stage driving unit, and the output circuit in each stage driving unit samples the received light-emitting signal based on the received clock signal and sequentially outputs the sampled light-emitting signal to the multiple rows of pixels in the display panel through the output end, so as to sequentially light the multiple rows of pixels.

Alternatively, the synchronous light-emitting instruction and the sequential light-emitting instruction may be generated by the DDIC. And, the DDIC may provide the synchronous light emission control signal and the sequential light emission control signal described above based on the above-mentioned instructions to synchronously light up a plurality of rows of pixels or sequentially light up a plurality of rows of pixels.

It is understood that, since the driving method of the display panel may have substantially the same implementation and technical effects as the gate driving circuit of the display panel described in the previous embodiments, the implementation and technical effects of the driving method of the display panel are not repeated herein for the sake of brevity.

The embodiment of the application also provides a display device. As shown in fig. 16, the display device includes a display panel 100 and a gate driving circuit 000 described in the above embodiment.

The display panel 100 includes a plurality of rows of pixels. The gate driving circuit 000 is connected to the plurality of rows of pixels and is used to drive the plurality of rows of pixels to emit light. Among them, fig. 16 only schematically illustrates the display panel 100.

Alternatively, the display device according to the embodiment of the present application may be any product or component having a display function, such as an organic light-emitting diode (OLED) display device or a silicon-based OLED display device. And, the display device may be any suitable display device, including but not limited to a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, an electronic book, and any other product or component with a display function.

Since the display device may have substantially the same technical effects as the gate driving circuit described in the previous embodiments, the technical effects of the gate driving circuit are not repeated here for the sake of brevity.

It is to be noted that the terminology used in the description of the embodiments of the application is for the purpose of describing the embodiments only and is not intended to be limiting of the application. Unless defined otherwise, technical or scientific terms used in the embodiments of the present application should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present application belongs.

As used in the specification and claims of this application, the terms "first," "second," or "third," and the like, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another.

Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

The word "comprising" or "comprises", and the like, is intended to mean that elements or items that are present in front of "comprising" or "comprising" are included in the word "comprising" or "comprising", and equivalents thereof, without excluding other elements or items.

"Upper", "lower", "left" or "right" etc. are only used to indicate relative positional relationships, which may also be changed accordingly when the absolute position of the object to be described is changed. "connected" or "coupled" refers to electrical connections.

"And/or" means that there may be three relationships, e.g., A and/or B, and that there may be three cases where A alone exists, while A and B exist, and B alone exists. The character "/" generally indicates that the context-dependent object is an "or" relationship.

The foregoing description of the preferred embodiments of the present application is not intended to limit the application, but rather, the application is to be construed as limited to the appended claims.

Claims

1. A gate driving circuit for a display panel, characterized in that the gate driving circuit comprises: a cascaded multi-stage driving unit, the driving unit comprising: a first input control circuit, a second input control circuit and an output circuit;

The first input control circuit is respectively connected to the synchronous light-emitting control terminal, the input terminal of the output circuit and the input terminals of other stage driving units of the cascade, and is used to control the on-off of the input terminal of the output circuit and the input terminals of other stage driving units in response to the synchronous light-emitting control signal provided by the synchronous light-emitting control terminal, so that the signal received by the input terminal of the output circuit is transmitted to the input terminal of the other stage driving unit;

The second input control circuit is connected to the sequential light emitting control terminal, the output terminal of the output circuit and the input terminal of the other stage driving unit respectively, and is used to control the on-off of the output terminal of the output circuit and the input terminal of the other stage driving unit in response to the sequential light emitting control signal provided by the sequential light emitting control terminal, so that the signal output by the output terminal of the output circuit is transmitted to the input terminal of the other stage driving unit, wherein, in the same time period, the potential of the sequential light emitting control signal is opposite to the potential of the synchronous light emitting control signal;

The input end of the output circuit is used to receive a luminous signal, the clock end of the output circuit is used to receive a clock signal, the output end of the output circuit is used to connect to a pixel in the display panel, and the output circuit is used to sample the luminous signal based on the clock signal and output it to the pixel via the output end.

2. The gate driving circuit according to claim 1, characterized in that the output circuit comprises: a trigger;

The output circuit is used for sampling the luminous signal based on the transition edge of the clock signal and outputting the sample to the pixel via the output terminal.

3. The gate drive circuit according to claim 2, characterized in that the trigger is a double-edge-triggered D trigger; the second input control circuit is connected to the middle state end of the double-edge-triggered D trigger; the drive unit further comprises: a logic circuit;

The logic circuit is used to be connected between the output end of the double-edge D trigger and the pixel, and the logic circuit is also connected to the intermediate state end of the double-edge D trigger. The logic circuit is used to perform logical operations on the signals output from the output end and the intermediate state end of the double-edge D trigger and then output them to the pixel.

4. The gate driving circuit according to claim 3, characterized in that the logic operation process is an AND process, and the logic circuit comprises: an AND gate;

The two input terminals of the AND gate are respectively connected to the output terminal and the intermediate state terminal of the double-edge D flip-flop, and the output terminal of the AND gate is used to be connected to the pixel.

5. The gate driving circuit according to any one of claims 1 to 4, characterized in that the driving unit further comprises: a third input control circuit, a first forward scan control circuit and a first reverse scan control circuit;

The first input control circuit is connected to the input end of the other stage driving unit via the third input control circuit, and the third input control circuit is also connected to the synchronous light emitting control end, and the first input control circuit and the third input control circuit are used to control the on-off of the input end of the output circuit and the input end of the other stage driving unit in response to the synchronous light emitting control signal, so that the signal received by the input end of the output circuit is transmitted to the input end of the other stage driving unit, or the signal received by the input end of the other stage driving unit is transmitted to the input end of the output circuit;

The first forward scan control circuit and the first reverse scan control circuit are both connected between the first input control circuit and the third input control circuit, and the first forward scan control circuit is also connected to the forward scan control terminal, and the first reverse scan control circuit is also connected to the reverse scan control terminal, the first forward scan control circuit is used to control the on-off of the first input control circuit and the third input control circuit in response to the forward scan control signal provided by the forward scan control terminal, so that the signal received by the input terminal of the output circuit is sequentially transmitted to the input terminal of the other stage driving unit through the first input control circuit and the third input control circuit, and the first reverse scan control circuit is used to control the on-off of the first input control circuit and the third input control circuit in response to the reverse scan control signal provided by the reverse scan control terminal, so that the signal received by the input terminal of the other stage driving unit is sequentially transmitted to the input terminal of the output circuit through the third input control circuit and the first input control circuit;

Wherein, in the same time period, the potential of the reverse scan control signal is opposite to the potential of the forward scan control signal.

6. The gate driving circuit according to claim 5, characterized in that the first input control circuit and the third input control circuit are also connected to the sequential light emitting control terminal, and are used to control the on/off of the input terminal of the output circuit and the input terminal of the other stage driving unit in response to the synchronous light emitting control signal and the sequential light emitting control signal;

The first forward scan control circuit is also connected to the reverse scan control terminal, and is used to control the on/off of the first input control circuit and the third input control circuit in response to the forward scan control signal and the reverse scan control signal;

The first reverse scan control circuit is also connected to the forward scan control terminal, and is used to control the on/off of the first input control circuit and the third input control circuit in response to the forward scan control signal and the reverse scan control signal.

7. The gate drive circuit according to claim 6, characterized in that the first input control circuit comprises: a first transmission gate; the third input control circuit comprises: a second transmission gate; the first forward scan control circuit comprises: a third transmission gate and a fourth transmission gate; the first reverse scan control circuit comprises: a fifth transmission gate and a sixth transmission gate;

The control end of the first transmission gate and the control end of the second transmission gate are respectively connected to the synchronous light-emitting control end and the sequential light-emitting control end, the control end of the third transmission gate to the control end of the sixth transmission gate are respectively connected to the forward scanning control end and the reverse scanning control end, the input end of the first transmission gate is connected to the input end of the output circuit, the output end of the first transmission gate is connected to the input end of the third transmission gate and the output end of the fifth transmission gate, the output end of the third transmission gate is connected to the input end of the fourth transmission gate, the input end of the fifth transmission gate is connected to the output end of the sixth transmission gate, the output end of the fourth transmission gate and the input end of the sixth transmission gate are both connected to the output end of the second transmission gate, and the input end of the second transmission gate is connected to the input end of the other stage driving unit.

8. The gate driving circuit according to claim 7, characterized in that the driving unit further comprises: a first enhancement circuit and/or a second enhancement circuit;

The first enhancement circuit is connected between the third transmission gate and the fourth transmission gate, and is used to enhance the signal output by the third transmission gate and then transmit it to the fourth transmission gate;

The second enhancement circuit is connected between the fifth transmission gate and the sixth transmission gate, and is used for enhancing the signal output by the sixth transmission gate and then transmitting the signal to the fifth transmission gate.

9. The gate driving circuit according to claim 8, characterized in that the first enhancement circuit comprises: an even number of first inverters connected in series; the second enhancement circuit comprises: an even number of second inverters connected in series;

The input ends of the even number of first inverters connected in series are connected to the output end of the third transmission gate, and the output ends of the even number of first inverters connected in series are connected to the input end of the fourth transmission gate;

The input ends of the even number of second inverters connected in series are connected to the output end of the sixth transmission gate, and the output ends of the even number of second inverters connected in series are connected to the input end of the fifth transmission gate.

10. The gate driving circuit according to any one of claims 1 to 4, characterized in that the driving unit further comprises: a fourth input control circuit, a second forward scanning control circuit and a second reverse scanning control circuit;

The fourth input control circuit is connected to the sequential light emitting control terminal, the input terminal of the output circuit and the output terminal of the other stage driving unit respectively, and is used to control the on-off of the output terminal of the other stage driving unit and the input terminal of the output circuit in response to the sequential light emitting control signal, so that the signal output by the output terminal of the other stage driving unit is transmitted to the input terminal of the output circuit;

The second positive scan control circuit is connected between the output end of the output circuit and the second input control circuit, and is also connected to the positive scan control end, and is used to control the on-off of the output end of the output circuit and the second input control circuit in response to the positive scan control signal provided by the positive scan control end, so that the signal output by the output end of the output circuit is transmitted to the input end of the other stage driving unit through the second input control circuit;

The second reverse sweep control circuit is connected between the input end of the output circuit and the fourth input control circuit, and is also connected to the reverse sweep control end, and is used to control the on-off between the input end of the output circuit and the fourth input control circuit in response to the reverse sweep control signal provided by the reverse sweep control end, so that the signal output by the output end of the other stage driving unit is transmitted to the input end of the output circuit via the fourth input control circuit;

11. The gate driving circuit according to claim 10, characterized in that the second input control circuit and the fourth input control circuit are also connected to the sequential light emitting control terminal, the second input control circuit is used to control the on-off of the output terminal of the output circuit and the input terminal of the other stage driving unit in response to the synchronous light emitting control signal and the sequential light emitting control signal, and the fourth input control circuit is used to control the on-off of the output terminal of the other stage driving unit and the input terminal of the output circuit in response to the synchronous light emitting control signal and the sequential light emitting control signal;

The second forward scan control circuit is also connected to the reverse scan control terminal, and is used to control the on/off connection between the output terminal of the output circuit and the second input control circuit in response to the forward scan control signal and the reverse scan control signal;

The second reverse scan control circuit is also connected to the forward scan control terminal, and is used to control the on/off of the input terminal of the output circuit and the fourth input control circuit in response to the forward scan control signal and the reverse scan control signal.

12. The gate drive circuit according to claim 11, characterized in that the second input control circuit comprises: a seventh transmission gate; the fourth input control circuit comprises: an eighth transmission gate; the second forward scan control circuit comprises: a ninth transmission gate; the second reverse scan control circuit comprises: a tenth transmission gate;

The control end of the seventh transmission gate and the control end of the eighth transmission gate are respectively connected to the synchronous light-emitting control end and the sequential light-emitting control end, the control end of the ninth transmission gate to the control end of the tenth transmission gate are respectively connected to the forward scanning control end and the reverse scanning control end, the input end of the seventh transmission gate is connected to the output end of the ninth transmission gate, the output end of the seventh transmission gate is connected to the input end of the other-stage driving unit, the input end of the ninth transmission gate is connected to the output end of the output circuit, the input end of the eighth transmission gate is connected to the output end of the other-stage driving unit, the output end of the eighth transmission gate is connected to the input end of the tenth transmission gate, and the output end of the tenth transmission gate is connected to the input end of the output circuit.

13. The gate driving circuit according to any one of claims 1 to 4, characterized in that the driving unit further comprises: an inverting circuit;

The inverting circuit is used to be connected between the output end of the output circuit and the pixel, and is used to invert the signal output from the output end of the output circuit and then transmit it to the pixel.

14. The gate driving circuit according to claim 13, wherein the inverting circuit comprises: a third inverter;

The input end of the third inverter is connected to the output end of the output circuit, and the output end of the third inverter is used to be connected to the pixel.

15. A method for driving a display panel, characterized in that it is applied to the gate driving circuit according to any one of claims 1 to 14; the method comprising:

In response to the synchronous light-emitting instruction, the first input control circuit controls the input end of the output circuit to be connected with the input end of the other stage driving unit in response to the synchronous light-emitting control signal provided by the synchronous light-emitting control end, so that the signal received by the input end of the output circuit is transmitted to the input end of the other stage driving unit, and the output circuit in each stage driving unit samples the received light-emitting signal based on the received clock signal and synchronously outputs it to the multiple rows of pixels in the display panel through the output end, so as to synchronously light up the multiple rows of pixels;

In response to the sequential light-emitting instruction, the second input control circuit controls the on-off connection between the output end of the output circuit and the input end of the other level driving unit in response to the sequential light-emitting control signal provided by the sequential light-emitting control end, so that the signal output by the output end of the output circuit is transmitted to the input end of the other level driving unit, and the output circuit in each level driving unit samples the received light-emitting signal based on the received clock signal and outputs it sequentially to the multiple rows of pixels in the display panel through the output end, so as to light up the multiple rows of pixels in sequence.

16. A display device, characterized in that the display device comprises: a display panel, and a gate driving circuit according to any one of claims 1 to 14;

The display panel includes a plurality of rows of pixels. The gate driving circuit is connected to the plurality of rows of pixels and is used to drive the plurality of rows of pixels to emit light.