CN118298771B - Display panel and display device - Google Patents
Display panel and display deviceInfo
- Publication number
- CN118298771B CN118298771B CN202410311475.6A CN202410311475A CN118298771B CN 118298771 B CN118298771 B CN 118298771B CN 202410311475 A CN202410311475 A CN 202410311475A CN 118298771 B CN118298771 B CN 118298771B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3614—Control of polarity reversal in general
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
本申请提供了一种显示面板以及显示装置，该显示面板包括：驱动芯片，驱动方式为列翻转驱动；多个数据线，沿第一方向间隔排布且沿第二方向延伸，多个数据线的第一端与驱动芯片的输出端电连接；多个子像素，沿第一方向和第二方向阵列排布，沿第二方向位于同一列的子像素构成一个子像素列，一个子像素列对应至少一个数据线，数据线的第二端与对应的子像素列中的至少部分子像素电连接；逻辑门电路，目标数据线通过逻辑门电路与目标结构电连接，逻辑门电路用于改变传输至目标子像素的电压极性，使得各子像素以行翻转模式或者帧翻转模式翻转，目标结构包括驱动芯片和/或目标子像素。本申请解决了显示屏透过率低的问题。
This application provides a display panel and a display device. The display panel includes: a driver chip, driven by column flipping; multiple data lines, spaced apart along a first direction and extending along a second direction, with the first ends of the data lines electrically connected to the output of the driver chip; multiple sub-pixels, arrayed along the first and second directions, with sub-pixels in the same column along the second direction forming a sub-pixel column, each sub-pixel column corresponding to at least one data line, and the second ends of the data lines electrically connected to at least some of the sub-pixels in the corresponding sub-pixel column; and a logic gate circuit, through which the target data lines are electrically connected to a target structure. The logic gate circuit is used to change the polarity of the voltage transmitted to the target sub-pixels, causing each sub-pixel to flip in a row flipping mode or a frame flipping mode. The target structure includes the driver chip and/or the target sub-pixels. This application solves the problem of low transmittance of the display screen.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a display device.
Background
The Liquid crystal display device (Liquid CRYSTAL DISPLAY, LCD) has advantages of good image quality, small volume, light weight, low driving voltage, low power consumption, no radiation and relatively low manufacturing cost, and is dominant in the field of flat panel display.
VR (Virtual Reality) head-displaying LCDs are called FAST Liquid CRYSTAL DISPLAY LCDs (FAST Liquid crystal displays), and high PPI is required, but after PPI (pixel density) is high, the pixel pitch becomes small, and the electric fields of adjacent sub-pixels in the row direction affect each other, which affects the transmittance and color shift.
Disclosure of Invention
The application aims to provide a display panel and a display device, which at least solve the problem of low transmittance of a display screen caused by the mutual influence of electric fields between adjacent sub-pixels in a row direction in the display screen with high pixel density in the prior art.
In order to achieve the above object, according to one aspect of the present application, there is provided a display panel including:
The driving mode of the driving chip is column overturning driving;
The data lines are arranged at intervals along a first direction and extend along a second direction, the first direction intersects with the second direction, and first ends of the data lines are electrically connected with output ends of the driving chip;
The plurality of sub-pixels are arranged in an array along the first direction and the second direction, the sub-pixels located in the same column along the second direction form a sub-pixel column, one sub-pixel column corresponds to at least one data line, and the second end of the data line is electrically connected with at least part of the sub-pixels in the corresponding sub-pixel column;
The logic gate circuit is used for changing the polarity of voltage transmitted to a target sub-pixel so that each sub-pixel can be turned in a row turning mode or a frame turning mode, the target structure comprises at least one of a driving chip and the target sub-pixel, the target data line is at least one of a plurality of data lines, and the plurality of sub-pixels comprise the target sub-pixel.
According to still another aspect of the present application, there is provided a display device including any one of the display panels.
By applying the technical scheme of the application, the logic gate circuit is arranged between the data line and the driving chip, or the logic gate circuit is arranged between the data line and the sub-pixels, and the voltage polarity of the sub-pixels in the middle of the sub-pixel array is changed through the logic gate circuit, so that the driving chip using column inversion driving as a driving mode can realize row inversion or frame inversion of the display panel, the pressure difference between the adjacent sub-pixels in the row direction is eliminated, the influence of the pressure difference between the adjacent sub-pixels in the column inversion mode on the transmittance is solved, and the higher transmittance of the display panel is ensured.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:
FIG. 1 is a schematic diagram of voltage polarities of subpixels in a column inversion mode according to an embodiment of the present application;
Fig. 2 (a) to 2 (d) respectively show schematic cross-sectional structures of a display panel provided according to an embodiment of the present application;
fig. 3 is a schematic structural view of a display panel according to an embodiment of the present application;
fig. 4 is a schematic view showing a specific structure of a display panel according to an embodiment of the present application;
Fig. 5 is a schematic view showing a specific structure of another display panel according to an embodiment of the present application;
Fig. 6 is a schematic view showing a specific structure of still another display panel according to an embodiment of the present application;
fig. 7 is a schematic view showing a specific structure of yet another display panel provided according to an embodiment of the present application;
Fig. 8 is a schematic view showing a specific structure of another display panel according to an embodiment of the present application;
Fig. 9 shows a schematic structural diagram of a display device according to an embodiment of the present application.
Wherein the above figures include the following reference numerals:
10. Data line, 11, subpixel, 12, logic gate circuit, 13, target data line, 14, target subpixel, 15, first inverter, 16, NAND gate, 17, NOR gate, 18, second inverter, 19, first data line, 20, second data line, 21, third inverter, 100, TFT substrate, 101, CF substrate, 102, insulating layer, 103, pixel electrode, 104, common electrode, 105, light shielding layer.
Detailed Description
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the application herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As described in the background art, in the display screen with high pixel density in the prior art, electric fields between adjacent sub-pixels in the row direction affect each other, resulting in lower transmittance of the display screen. Specifically, when each of the above sub-pixels is turned over in a column inversion manner, the voltage polarity of the corresponding sub-pixel is shown in fig. 1, wherein "+" indicates that the voltage polarity of the sub-pixel is positive and "-" indicates that the voltage polarity of the sub-pixel is negative, as can be seen from fig. 1, when the columns are turned over, the voltage polarities of the adjacent sub-pixel columns are different, so that in the row direction, a voltage difference exists between the adjacent sub-pixels, and an electric field is formed between the adjacent sub-pixels, as indicated by horizontal arrows in fig. 2 (a) and 2 (c), which causes a disorder of the molecular state of the liquid crystal in the region, as shown in fig. 2 (a), when the display panel is in a normally black mode liquid crystal and is displayed as a white picture, a dark region is formed in the region, and a problem of reduced transmittance is caused, as shown in fig. 2 (c), and when the display panel is in a normally white mode liquid crystal and is displayed as a black picture, the region forms a bright region, and light leakage is caused. As shown in fig. 2 (b) and (d), when the voltages of adjacent sub-pixels are the same, a dark area or a bright area is not formed. Fig. 2 (a) - (d) are schematic cross-sectional structures of a display panel, and fig. 2 (a) - (d) show a TFT (Thin Film Transistor ) substrate 100, a CF (Color Filter) substrate 101, a sub-pixel 11, an insulating layer 102, a pixel electrode 103 and a common electrode 104 between the TFT substrate 100 and the CF substrate 101 of the display panel, where the display panel further includes a light shielding layer 105 located on a side of the CF substrate 101 near the TFT substrate 100.
In order to solve the above technical problems, embodiments of the present application provide a display panel and a display device.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
In this embodiment, a display panel is provided, and fig. 3 is a schematic structural diagram of the display panel according to an embodiment of the present application. As shown in fig. 3, the display panel includes:
A driving chip (not shown in the figure), wherein the driving mode of the driving chip is Column Inversion (Column Inversion) driving, and the sub-pixels in the display panel are turned over in Column sequence under the driving of the driving chip, and the voltage polarities of the sub-pixels in adjacent columns are opposite, so that a voltage difference exists;
A plurality of data lines 10, wherein the plurality of data lines 10 are arranged at intervals along a first direction and extend along a second direction, the first direction is a row direction of the display panel, the second direction is a column direction of the display panel, the first direction intersects the second direction, and first ends of the plurality of data lines 10 are electrically connected with output ends of the driving chip;
specifically, the first direction and the second direction are perpendicular to each other.
A plurality of sub-pixels 11, wherein the plurality of sub-pixels 11 are arranged in an array along the first direction and the second direction, the sub-pixels located in the same column along the second direction form a sub-pixel column, one sub-pixel column corresponds to at least one data line 10, and a second end of the data line 10 is electrically connected to at least part of the sub-pixels 11 in the corresponding sub-pixel column;
A logic gate circuit 12, the target data line 13 is electrically connected to a target structure through the logic gate circuit 12, the logic gate circuit 12 is configured to change a polarity of a voltage transmitted to a target sub-pixel, so that each of the sub-pixels is turned in a Row Inversion (Row Inversion) mode or a Frame Inversion (Frame Inversion) mode, wherein voltages of the sub-pixels located on a same Row are the same when each of the sub-pixels is turned in the Row Inversion mode, and voltages of any adjacent two of the sub-pixels are the same when each of the sub-pixels is turned in the Frame Inversion mode, the target structure includes at least one of the driving chip and the target sub-pixel (not shown), the target data line 13 is at least one of the plurality of the data lines 10, and the plurality of the sub-pixels 11 include the target sub-pixel.
Through the embodiment, the logic gate circuit is arranged between the data line and the driving chip, or the logic gate circuit is arranged between the data line and the sub-pixels, and the voltage polarity of the sub-pixels in the middle of the sub-pixel array is changed through the logic gate circuit, so that the driving chip using column inversion driving as a driving mode can realize row inversion or frame inversion of the display panel, the pressure difference between the adjacent sub-pixels in the row direction is eliminated, the influence of the pressure difference between the adjacent sub-pixels on the transmittance in the column inversion mode is solved, and the higher transmittance of the display panel is ensured.
The display panel of the present application may be an LTPS (Low Temperature Poly-Silicon, low temperature polysilicon) LCD. The driving mode of the driving chip of the current LTPS LCD does not support line inversion and frame inversion, and the embodiment of the application can realize high transmittance of the display panel by utilizing the current driving chip without redevelopment of the driving chip of the LTPS LCD.
It should be noted that, each sub-pixel in the sub-pixel column is electrically connected to the second end of the data line, where in a case where there is one data line corresponding to the sub-pixel column, all sub-pixels in the sub-pixel column are electrically connected to the corresponding data line, and in a case where there are a plurality of data lines corresponding to the sub-pixel column, for example, there are two data lines, some sub-pixels in the sub-pixel column are electrically connected to the corresponding data line, and the rest of sub-pixels are electrically connected to the corresponding other data line.
The display panel further includes a plurality of multiplexers, the driving chip is electrically connected to the data lines through the multiplexers, specifically, in the case where a logic gate circuit is provided between the driving chip and the data lines, the driving chip is electrically connected to the first ends of the data lines sequentially through the multiplexers and the logic gate circuit, and in the case where no logic gate circuit is provided between the driving chip and the data lines, the driving chip is electrically connected to the first ends of the data lines through the multiplexers. One of the multiple gates corresponds to at least two of the data lines. Fig. 4 to 8 are schematic views illustrating polarities of voltages of sub-pixels in the case of 1:2demux for a multiplexer, that is, one multiplexer is correspondingly connected to two data lines, and the connection ends are S1 and S2 respectively. The implementation principle of the 1:3demux or other multiplexers is the same as that of the 1:2demux, and the application is not repeated.
In an alternative, as shown in fig. 4, the target structure includes the driving chip, the target data line 13 is the data line 10 corresponding to the sub-pixel column located in the even column or the odd column, the odd column and the even column are the sub-pixel column located in the odd column and the even column located in the first direction, fig. 4 shows a case where the data line is arranged in the horizontal direction, the first direction may specifically be a direction from the horizontal left to the horizontal right, or may be a direction from the horizontal right to the horizontal left, fig. 4 shows the target data line 13 as the data line 10 corresponding to the sub-pixel column located in the odd column, the logic gate circuit includes a first inverter 15, an input end of the first inverter 15 is electrically connected to an output end of the driving chip, an output end of the first inverter 15 is electrically connected to a first end of the target data line 13, and the driving signal is outputted to the sub-pixels 11 in the inversion mode when the driving chip inverts the data line 11.
In the above embodiment, the data lines corresponding to the sub-pixel columns along the first direction to one of the even columns and the odd columns are electrically connected to the driving chip through the first inverter, and the voltage polarity of the sub-pixel column located in one of the even columns and the odd columns can be changed through the first inverter so as to be the same as the voltage polarity of the sub-pixel column located in the other of the even columns and the odd columns, that is, in the process that the driving chip drives each sub-pixel in a column inversion driving mode, the voltage polarities of any two adjacent sub-pixel columns are the same, which is equivalent to realizing that the display panel is turned in a frame inversion mode, and no voltage difference exists between the adjacent sub-pixel columns, thereby further solving the influence of an electric field formed by the voltage difference on the transmittance, and further improving the transmittance of the display panel.
It will be appreciated that in the above embodiment, as shown in fig. 4, each sub-pixel column corresponds to one of the data lines 10, and each sub-pixel 11 in the sub-pixel column is electrically connected to the second end of the corresponding data line 10. The other data lines 10 are not electrically connected to the driving chip through the first inverter 15, but are directly electrically connected to the driving chip, except for the target data line 13.
As shown in fig. 4, in the case where the logic gate circuit includes the first inverter, when the input signal of the S1 terminal is at a high level, the output of the B terminal is at a low level, when the input signal of the S1 terminal is at a low level, the output of the B terminal is at a high level, the inversion mode of the input of the driving chip is column inversion, and the inversion mode of the display panel is frame inversion, so as to realize the function of improving the transmittance.
Specifically, the display panel further includes a display area and a non-display area surrounding the display area, and the first inverter is located in the non-display area of the display panel. Therefore, the first inverter can be prevented from occupying the layout wiring space of the display area, and the higher aperture opening ratio of the display panel is ensured.
As shown in fig. 4, in the logic gate circuit, the number of the first inverters is plural, and the specific number of the first inverters may be the same as the number of the multiplexers.
In another alternative, as shown in fig. 5, the target structure includes the driving chip, the target data line 13 is the data line 10 corresponding to the sub-pixel column located in the even column or the odd column, the odd column and the even column are the sub-pixel column located in the odd column and the even column located in the first direction, fig. 5 shows a case where the data line is arranged in the horizontal direction, the first direction may specifically be a direction from the horizontal left to the horizontal right, or may be a direction from the horizontal right to the horizontal left, fig. 5 exemplarily shows that the target data line 13 is the data line 10 corresponding to the sub-pixel column located in the odd column, the logic gate circuit includes a nand gate 16 having two input terminals and one output terminal, the first input terminal of the nand gate 16 is electrically connected to the output terminal of the driving chip, the second input terminal of the nand gate 16 is used for receiving the first level signal, the output terminal of the nand gate 16 is electrically connected to the output terminal of the driving chip, and the data line 11 is electrically connected to the respective driving sub-pixels 11 in the case where the driving chip is turned over by the respective data line 11.
In the above embodiment, the data lines corresponding to the sub-pixel columns located in one of the even columns and the odd columns along the first direction are electrically connected to the driving chip through the nand gate, and the voltage polarity of the sub-pixel column located in one of the even columns and the odd columns can be changed by controlling the first level signal through the nand gate so as to be the same as the voltage polarity of the sub-pixel column located in the other of the even columns and the odd columns, that is, in the process that the driving chip drives each sub-pixel in a column inversion driving mode, the voltage polarities of any two adjacent sub-pixel columns are the same, which is equivalent to realizing that the display panel is turned in a frame inversion mode, and no voltage difference exists between the adjacent sub-pixel columns, further solving the influence of an electric field formed by the voltage difference on the transmittance, and further improving the transmittance of the display panel.
In addition, in the above embodiment, by adjusting the first level signal, the display panel can be turned from column inversion to frame inversion when the driving chip is driven by the column driving method, and the display panel can be turned from frame inversion to column inversion when the driving chip is driven by the column driving method, so that the high transmittance requirement of the display panel can be met, and the high image quality requirement of the display panel can be met.
It will be appreciated that in the above embodiment, as shown in fig. 5, each sub-pixel column corresponds to one of the data lines 10, and each sub-pixel 11 in the sub-pixel column is electrically connected to the second end of the corresponding data line 10. The other data lines 10 are not electrically connected to the driving chip through the nand gate 16, but are directly electrically connected to the driving chip, except for the target data line 13.
In the case of the logic gate circuit including a nand gate, when the input signal at the S1 terminal is at a high level, the input level of the second input terminal a of the nand gate may be controlled to achieve whether the output terminal B is at a high level or a low level, so that switching of the flip mode, that is, switching between column flip and frame flip, may be achieved, a frame flip mode may be selected when high transmittance is required, and a column flip mode may be selected when high image quality is required.
Further, in the case where the display panel is required to perform frame inversion, the first level signal includes a high level signal. Under the condition that the first level signal is a high level signal, the level of the first input end of the NAND gate is opposite to the level of the output end, so that the problem that the transmittance of the display panel is poor due to high PPI is further avoided by overturning the display panel in a frame overturning mode in the process that the driving chip drives each sub-pixel to overturn in a column overturning driving mode.
Specifically, the display panel further includes a display area and a non-display area surrounding the display area, and the nand gate is located in the non-display area of the display panel. Therefore, the NAND gate can be prevented from occupying the layout wiring space of the display area, and the higher aperture opening ratio of the display panel is ensured.
As shown in fig. 5, in the logic gate circuit, the number of nand gates is plural, and the specific number of nand gates may be the same as the number of multiplexers.
In still another alternative, as shown in fig. 6, the target structure includes the driving chip, the target data line 13 is the data line 10 corresponding to the sub-pixel column located in the even column or the odd column, the odd column and the even column are the sub-pixel column located in the odd column and the even column located in the first direction, fig. 6 shows a case where the data line is arranged in the horizontal direction, the first direction may specifically be a direction from the horizontal left to the horizontal right, or may be a direction from the horizontal right to the horizontal left, fig. 6 exemplarily shows that the target data line 13 is the data line 10 corresponding to the sub-pixel column located in the even column, the logic gate circuit includes a nor gate 17 having two input terminals and one output terminal, the first input terminal of the nor gate 17 is electrically connected to the output terminal of the driving chip, the second input terminal of the nor gate 17 is used for receiving the second signal, the second input terminal of the nor gate 17 is electrically connected to the output terminal of the driving chip, and the data line 11 is flipped over each of the data line, and the data line 11 is electrically flipped over each of the data line is connected to each of the data lines 11.
In the above embodiment, the data lines corresponding to the sub-pixel columns located in one of the even columns and the odd columns are electrically connected to the driving chip through the nor gate, and through the nor gate, the voltage polarity of the sub-pixel column located in one of the even columns and the odd columns can be changed to be the same as the voltage polarity of the sub-pixel column located in the other of the even columns and the odd columns, that is, in the process that the driving chip drives each sub-pixel to turn in a column-turning driving manner, the voltage polarities of any two adjacent sub-pixel columns are the same, which is equivalent to realizing that the display panel turns in a frame-turning manner, and no voltage difference exists between the adjacent sub-pixel columns, thereby further solving the influence of the electric field formed by the voltage difference on the transmittance, and further improving the transmittance of the display panel.
In addition, in the above embodiment, by adjusting the second level signal, the display panel can be turned from column inversion to frame inversion when the driving chip is driven by the column driving method, and the display panel can be turned from frame inversion to column inversion when the driving chip is driven by the column driving method, so that the high transmittance requirement of the display panel can be met, and the high image quality requirement of the display panel can be met.
It will be appreciated that in the above embodiment, as shown in fig. 6, each sub-pixel column corresponds to one of the data lines 10, and each sub-pixel 11 in the sub-pixel column is electrically connected to the second end of the corresponding data line 10. The other data lines 10 are not electrically connected to the driving chip through the nor gate 17, but are directly electrically connected to the driving chip, except for the target data line 13.
In the case where the logic gate circuit includes a nor gate, as shown in fig. 6, when the input signal of S2 is at a low level, it is possible to control the input level of the second input terminal C of the nor gate to realize whether the output terminal D of the nor gate is at a high level or a low level, so that switching of the flip mode, that is, switching between column flip and frame flip, may be realized, a frame flip mode may be selected when high transmittance is required, and a column flip mode may be selected when high image quality is required.
Further, in the case where the display panel is required to perform frame inversion, the second level signal includes a low level signal. Under the condition that the second level signal is a low level signal, the level of the first input end of the nor gate is opposite to the level of the output end, so that the problem that the transmittance of the display panel is poor due to high PPI is further avoided by overturning the display panel in a frame overturning mode in the process that the driving chip drives each sub-pixel to overturn in a column overturning driving mode.
Specifically, the display panel further includes a display area and a non-display area surrounding the display area, and the nor gate is located in the non-display area of the display panel. Therefore, the nor gate can be prevented from occupying the layout wiring space of the display area, and the higher aperture opening ratio of the display panel is ensured.
As shown in fig. 6, in the logic gate circuit, the number of nor gates is plural, and the specific number of nor gates may be the same as the number of multiplexers.
In still another alternative, as shown in fig. 7, the plurality of data lines 10 are all the target data lines 13, the target structure includes the target sub-pixels 14, the other sub-pixels 11 except the target sub-pixels 14 and the target sub-pixels 14 are alternately arranged at intervals in the first direction and the second direction, that is, the target sub-pixels 14 and the other sub-pixels 11 are arranged in a checkerboard pattern, the logic gate circuit includes a second inverter 18, an output end of the second inverter 18 is electrically connected to the target sub-pixels 14, an input end of the second inverter 18 is electrically connected to a second end of the target data line 13 corresponding to the target sub-pixels 14, and the sub-pixels 11 are turned in the row turning mode when the driving chip outputs a driving signal to the sub-pixels 11 through the data lines 10.
In the above embodiment, the target sub-pixels and other sub-pixels in the display panel are arranged in a checkerboard, and the second inverter is disposed between the data line and the corresponding target sub-pixel, so that the voltage polarity of the target sub-pixel and the voltage polarity of the adjacent other sub-pixels are the same along the row direction, that is, in the process that the driving chip drives each sub-pixel to turn in a column-turning driving manner, the voltage polarities of any two adjacent sub-pixel columns in the row direction are the same, which is equivalent to realizing that the display panel turns in a column-turning manner, and no voltage difference exists between the adjacent sub-pixel columns in the row direction, further solving the influence of the electric field formed by the voltage difference on the transmittance, and further improving the transmittance of the display panel.
It will be appreciated that in the above embodiment, as shown in fig. 7, each sub-pixel column corresponds to one of the data lines 10, and each sub-pixel 11 in the sub-pixel column is electrically connected to the second end of the corresponding data line 10. The other sub-pixels 11, except for the target sub-pixel 14, are not electrically connected to the corresponding data line 10 through the second inverter 18, but are directly electrically connected to the data line 10.
As shown in fig. 7, in the logic gate circuit, the number of the second inverters is plural, and the specific number is the same as the number of the target sub-pixels.
Further, the display panel further includes a display area and a non-display area surrounding the display area, the aperture ratio of the display panel is not required to be high, and the second inverter is located in the display area of the display panel.
According to still other exemplary embodiments of the present application, as shown in fig. 8, the target structure includes the driving chip, one of the sub-pixel columns is electrically connected to two of the data lines, the two of the data lines are respectively a first data line 19 and a second data line 20, each of the two adjacent sub-pixel columns forms a pixel column group along the first direction, the first data line 19 is electrically connected to the sub-pixel 11 located at an odd bit along the second direction in the corresponding sub-pixel column group, the second data line 20 is electrically connected to the sub-pixel 11 located at an even bit along the second direction in the corresponding sub-pixel column group, the first data line 19 is electrically connected to the sub-pixel 11 located at an even bit in the corresponding sub-pixel column group along the first direction, the second data line 19 is electrically connected to the sub-pixel 11 located at an even bit in the corresponding sub-pixel column group, the second data line 20 is electrically connected to the inverting terminal, the second data line is electrically connected to the inverting terminal of the third data line 21, and the inverting terminal is electrically connected to the output terminal of the driving chip, and the driving chip is electrically connected to the inverting terminal is connected to the data line 11.
Fig. 8 shows a case where the data lines are arranged in a horizontal direction and extend in a vertical direction, and the first direction may specifically be a direction from a horizontal left direction to a horizontal right direction, or may be a direction from a horizontal right direction to a horizontal left direction. The second direction may be a direction from the data line to the driving chip or a direction from the driving chip to the data line.
In the above embodiment, the adjacent sub-pixel columns are divided into two groups of pixel columns along the first direction, and in the group of pixel columns with odd columns, the sub-pixels with odd bits in the sub-pixel columns corresponding to the first data line are connected to the first data line, and in the group of pixel columns with even columns, the sub-pixels with even bits in the sub-pixel columns corresponding to the first data line are connected to the first data line, so that the sub-pixels sequentially pass through the first data line and the third inverter and are electrically connected to the driving chip, so that the voltage polarity of the sub-pixels electrically connected to the first data line is changed, and the voltage polarity of any two adjacent sub-pixels along the row direction is the same, that is, in the process that the driving chip drives each sub-pixel in a column inversion driving mode, the voltage polarity of any two adjacent sub-pixel columns in the row direction is the same, which is equivalent to realizing that the display panel is turned in a row inversion mode, and no voltage difference is generated between the adjacent sub-pixel columns in the row direction, so that the voltage difference is further solved, and the display panel has a further effect on the transmittance is caused.
In a specific embodiment, the target data line is the first data line, and the target subpixel is a subpixel electrically connected to the first data line. The first ends of the data lines except the target data line are directly electrically connected to the driving chip, and the target data line is electrically connected to the driving chip through the logic gate circuit, i.e., the third inverter. Each of the sub-pixels is directly and electrically connected to the second end of the corresponding data line.
It will be appreciated that in the above embodiment, as shown in fig. 8, each sub-pixel column corresponds to two data lines, namely, the first data line 19 and the second data line 20. In the case that the sub-pixel columns corresponding to the first data lines 19 are located in the odd-numbered column group along the first direction, the second ends of the first data lines 19 are electrically connected to the sub-pixels 11 located in the odd-numbered columns along the second direction among the corresponding sub-pixel columns; the second ends of the first data lines 19 are electrically connected to the sub-pixels 11 located in the even columns in the second direction among the corresponding sub-pixel columns in the even columns in the first direction while the first ends of the first data lines 19 are connected to the driving chip through the third inverter 21, the second ends of the second data lines 20 are electrically connected to the sub-pixels 11 located in the even columns in the second direction among the corresponding sub-pixel columns in the odd columns in the first direction while the first ends of the second data lines 20 are directly connected to the driving chip without being connected to the driving chip through the third inverter 21 while the second ends of the second data lines 20 are electrically connected to the sub-pixels 11 located in the even columns in the second direction among the corresponding sub-pixel columns in the even columns in the first direction.
As shown in fig. 8, in the case where the logic gate circuit includes the third inverter, when the S1 terminal input signal is at a high level, the output of the third inverter is at a low level so that the voltage polarity of the sub-pixel electrically connected to the first data line is low and the voltage polarity of the sub-pixel electrically connected to the second data line is high, and when the S1 terminal input signal is at a low level, the output of the third inverter is at a high level so that the voltage polarity of the sub-pixel electrically connected to the first data line is high and the voltage polarity of the sub-pixel electrically connected to the second data line is low. Through the third inverter, the polarities of the voltages of the sub-pixels on the same row are the same, so that the inversion mode of the input of the driving chip is column inversion, and the inversion mode of the display panel is row inversion, thereby realizing the function of improving the transmittance.
In an embodiment of the application, the display panel further includes a display area and a non-display area surrounding the display area, and the third inverter is located in the non-display area of the display panel. The second inverter is disposed between the data line and the sub-pixel of the display region, which is helpful to improve the overall transmittance of the display panel, but the aperture ratio of the second inverter may be affected for the display panel with high PPI. In this embodiment, the third inverter is disposed in the non-display area, so that the transmittance of the display panel is further ensured, and the aperture opening ratio of the display panel is prevented from being affected, thereby further ensuring that the overall display performance of the display panel is better.
As shown in fig. 8, in the logic gate circuit, the number of the third inverters is plural, and the specific number thereof may be the same as the number of the multiplexers.
In the practical application process, the first data lines may be arranged in one-to-one correspondence with the third inverters, or may be arranged in one-to-many correspondence. In order to improve the transmittance of the display panel and simultaneously ensure the design requirement of the display panel with narrow frame, as shown in fig. 8, in other exemplary embodiments of the present application, each pixel column group corresponds to two first data lines 19 and two second data lines 20, the first ends of all the second data lines 20 in one pixel column group are electrically connected, the first ends of the electrically connected second data lines serve as a common terminal, i.e. the first ends of the two second data lines 20 in each pixel column group are electrically connected and then serve as a common terminal, the common terminal is connected to a driving chip, the output end of one third inverter is correspondingly connected to the first ends of all the first data lines 19 in one pixel column group, that is, the first ends of the two first data lines 19 in each pixel column group are electrically connected and then electrically connected to the output end of the corresponding third inverter 21, i.e. the output end of one third inverter 21 is electrically connected to the common terminal through the input end of the driving chip. Compared with the one-to-one connection mode of the first data line and the third inverter, in this embodiment, one pixel column group corresponds to one third inverter, so that the number of the third inverters is reduced, that is, the space of the non-display area occupied by the third inverters is reduced, and thus the narrow-frame design is facilitated.
In a specific application, the subpixels in the display panel are arranged in an array, and in order to facilitate wiring, the data lines may be disposed on one side of the corresponding subpixel columns in a one-to-one correspondence manner. In a specific arrangement, the data lines may be arranged on the same side of the corresponding sub-pixel columns, or may be arranged on different sides of the corresponding sub-pixel columns. Fig. 4 to 8 exemplarily show the case where the above-described data lines are each located at the left side of the corresponding sub-pixel column. Of course, the data lines may be located on the right side of the corresponding sub-pixel columns, or some of the data lines may be located on one side of the corresponding sub-pixel columns, and the rest of the data lines may be located on the other side of the corresponding sub-pixel columns.
It should be noted that the features of the foregoing embodiments may be combined with each other, for example, in some embodiments, the logic gate circuit includes a first inverter and a second inverter, a portion of the target data line is electrically connected to the driving chip through the first inverter, and the remaining portion of the target data line is electrically connected to the target sub-pixel through the second inverter. In other embodiments, the logic gate circuit may further include at least two of a first inverter, a nand gate, and a nor gate, and so on.
The embodiment of the application also provides a display device shown in fig. 9, which comprises any one of the display panels.
Through the above embodiment, the display device includes any one of the above display panels, in which a logic gate circuit is disposed between a data line and a driving chip, or between a data line and a subpixel, and the logic gate circuit is used to change the voltage polarity of a subpixel in the middle of a subpixel array, so that the driving chip using column inversion driving as a driving mode can implement column inversion or frame inversion of the display panel, eliminating the pressure difference existing between adjacent subpixels in the column direction, solving the influence of the pressure difference between adjacent subpixels in the column inversion mode on the transmittance, and ensuring that the transmittance of the display panel is higher, thereby ensuring that the display performance of the display device is better.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:
1) According to the display panel, the logic gate circuit is arranged between the data line and the driving chip, or the logic gate circuit is arranged between the data line and the sub-pixels, and the voltage polarity of the sub-pixels in the middle of the sub-pixel array is changed through the logic gate circuit, so that the driving chip using column inversion driving as a driving mode can realize row inversion or frame inversion of the display panel, the pressure difference between the adjacent sub-pixels in the row direction is eliminated, the influence of the pressure difference between the adjacent sub-pixels in the column inversion mode on the transmittance is solved, and the higher transmittance of the display panel is ensured.
2) The display device comprises any one of the display panels, wherein a logic gate circuit is arranged between a data line and a driving chip in the display panel, or a logic gate circuit is arranged between the data line and a sub-pixel, and the voltage polarity of the sub-pixel in the middle of the sub-pixel array is changed through the logic gate circuit, so that the driving chip which takes column inversion driving as a driving mode can realize row inversion or frame inversion of the display panel, the pressure difference between adjacent sub-pixels in the row direction is eliminated, the influence of the pressure difference between the adjacent sub-pixels in the column inversion mode on the transmittance is solved, the higher transmittance of the display panel is ensured, and the display performance of the display device is ensured to be better.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (14)
1. A display panel, comprising:
The driving mode of the driving chip is column overturning driving;
The data lines are arranged at intervals along a first direction and extend along a second direction, the first direction intersects with the second direction, and first ends of the data lines are electrically connected with output ends of the driving chip;
The plurality of sub-pixels are arranged in an array along the first direction and the second direction, the sub-pixels located in the same column along the second direction form a sub-pixel column, one sub-pixel column corresponds to at least one data line, and the second end of the data line is electrically connected with at least part of the sub-pixels in the corresponding sub-pixel column;
The logic gate circuit is used for changing the polarity of the voltage transmitted to the target sub-pixels so that each sub-pixel can be turned over in a row turning mode or a frame turning mode, the target structure comprises the driving chip or the target sub-pixels, the target data line is at least one of a plurality of data lines, and the plurality of sub-pixels comprise the target sub-pixels.
2. The display panel according to claim 1, wherein the target structure includes the driving chip, the target data line is the data line corresponding to the sub-pixel column located in an even column or an odd column along the first direction, and the logic gate circuit includes:
The input end of the first inverter is electrically connected with the output end of the driving chip, the output end of the first inverter is electrically connected with the first end of the target data line, and under the condition that the driving chip outputs driving signals to the sub pixels through the data lines, the sub pixels are turned over in the frame turning mode.
3. The display panel according to claim 1, wherein the target structure includes the driving chip, the target data line is the data line corresponding to the sub-pixel column located in an even column or an odd column along the first direction, and the logic gate circuit includes:
and the first input end of the NAND gate is electrically connected with the output end of the driving chip, the second input end of the NAND gate is used for receiving a first level signal, the output end of the NAND gate is electrically connected with the first end of the target data line, and under the condition that the driving chip outputs driving signals to the sub pixels through the data lines, the sub pixels are turned over in the frame turning mode.
4. A display panel according to claim 3, wherein the first level signal comprises a high level signal.
5. The display panel according to claim 1, wherein the target structure includes the driving chip, the target data line is the data line corresponding to the sub-pixel column located in an even column or an odd column along the first direction, and the logic gate circuit includes:
And the first input end of the nor gate is electrically connected with the output end of the driving chip, the second input end of the nor gate is used for receiving a second level signal, the output end of the nor gate is electrically connected with the first end of the target data line, and under the condition that the driving chip outputs driving signals to the sub pixels through the data lines, the sub pixels are turned over in the frame turning mode.
6. The display panel of claim 5, wherein the second level signal comprises a low level signal.
7. The display panel according to claim 1, wherein the plurality of data lines are each the target data line, the target structure includes the target sub-pixel, the sub-pixels other than the target sub-pixel and the target sub-pixel are alternately arranged at intervals in the first direction and the second direction, respectively, and the logic gate circuit includes:
and the output end of the second inverter is electrically connected with the target sub-pixel, the input end of the second inverter is electrically connected with the second end of the target data line corresponding to the target sub-pixel, and under the condition that the driving chip outputs driving signals to the sub-pixels through the data lines, the sub-pixels are turned over in the row turning mode.
8. The display panel of claim 7, wherein the second inverter is located in a display area of the display panel.
9. The display panel according to claim 1, wherein the target structure includes the driving chip, one of the sub-pixel columns corresponds to two of the data lines, the two of the data lines are a first data line and a second data line, respectively, in the first direction, each adjacent two of the sub-pixel columns form a pixel column group, and are located in the pixel column group of the odd-numbered columns in the first direction, the first data line is electrically connected to the sub-pixel located in the odd-numbered bits in the second direction in the corresponding sub-pixel columns, the second data line is electrically connected to the sub-pixel located in the even-numbered bits in the second direction in the corresponding sub-pixel columns, in the pixel column group located in the even-numbered columns in the first direction, the first data line is electrically connected to the sub-pixel located in the even-numbered bits in the corresponding sub-pixel columns, the second data line is electrically connected to the sub-pixel located in the odd-numbered columns in the second direction, the target structure includes the logic gate:
And the output end of the third inverter is electrically connected with the first end of the target data line, the input end of the third inverter is electrically connected with the output end of the driving chip, and each sub-pixel is turned over in the row turning mode under the condition that the driving chip outputs driving signals to each sub-pixel through each data line.
10. The display panel according to claim 9, wherein first ends of all the second data lines in one of the pixel column groups are electrically connected, first ends of the electrically connected plurality of second data lines are used as a common terminal, an output end of one of the third inverters is correspondingly connected to the first ends of all the first data lines in one of the pixel column groups, and an input end of one of the third inverters is electrically connected to an output end of the driving chip through the corresponding common terminal.
11. The display panel of claim 9, wherein the third inverter is located in a non-display region of the display panel.
12. The display panel according to any one of claims 1 to 11, wherein first ends of the data lines other than the target data line are directly electrically connected to the driving chip.
13. The display panel according to any one of claims 1 to 11, further comprising:
the driving chip is electrically connected with the data lines through the multiple gates, and one multiple gate corresponds to at least two data lines.
14. A display device comprising the display panel according to any one of claims 1 to 13.
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| CN103901685A (en) * | 2012-12-31 | 2014-07-02 | 厦门天马微电子有限公司 | Liquid crystal display |
| CN111025710A (en) * | 2019-12-25 | 2020-04-17 | 厦门天马微电子有限公司 | Display panel and display device |
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| KR101394713B1 (en) * | 2012-09-10 | 2014-05-15 | 하이디스 테크놀로지 주식회사 | Liquid crystal display apparatus and method of driving a lcd apparatus |
| CN108181770A (en) * | 2018-02-11 | 2018-06-19 | 厦门天马微电子有限公司 | A kind of display panel and display device |
| CN110111755A (en) * | 2019-06-18 | 2019-08-09 | 厦门天马微电子有限公司 | A kind of display panel, its driving method and display device |
| CN112967698B (en) * | 2021-03-31 | 2025-04-01 | 上海天马微电子有限公司 | Liquid crystal panel and driving method thereof and holographic 3D display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103901685A (en) * | 2012-12-31 | 2014-07-02 | 厦门天马微电子有限公司 | Liquid crystal display |
| CN111025710A (en) * | 2019-12-25 | 2020-04-17 | 厦门天马微电子有限公司 | Display panel and display device |
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