CN117270264A - Array substrate, display panel and display device - Google Patents

Abstract

The invention discloses an array substrate, a display panel and a display device, wherein a plurality of scanning lines and a plurality of data lines are mutually insulated and crossed on the array substrate to define a plurality of pixel units, each pixel unit comprises a first sub-pixel unit and a second sub-pixel unit which are arranged left and right, and two pixel units adjacent left and right are a repeating unit; in the same repeating unit, a first sub-pixel unit and a second sub-pixel unit of one pixel unit are respectively connected with a data line on the left side and a data line on the right side of the repeating unit, and a first sub-pixel unit and a second sub-pixel unit of the other pixel unit are respectively connected with a data line on the right side and a data line on the left side of the repeating unit; two scanning lines are arranged between two adjacent rows of pixel units; at least one sub-pixel unit is staggered between two adjacent rows of pixel units in the row direction. The SDRRS under single-point inversion can be realized by switching the data signal once every frame, no obvious difference of brightness and darkness exists, and the driving power consumption is reduced while the display image quality is improved.

Description

Array substrate, display panel, and display device

Technical field

The present invention relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device.

Background technique

With the development of science and technology, LCD (Liquid Crystal Display) monitors have replaced bulky CRT monitors and are increasingly integrated into people's daily lives. Especially LCD monitors have small size, light weight, thin thickness, and high functionality. It has the characteristics of low power consumption and no radiation. It has developed rapidly in recent years and occupies a dominant position in the current flat panel display market. It has been widely used in various large, medium and small-sized products, covering almost all major aspects of today's information society. Electronic products, such as LCD TVs, computers, mobile phones, PDAs, GPS, vehicle displays, projection displays, video cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays and virtual displays, etc.

During the image display process, each liquid crystal pixel point in the LCD flat panel display is driven by a thin film transistor (TFT) integrated in the TFT thin film transistor array substrate, and then cooperates with the peripheral drive circuit to achieve image display. The dual-gate architecture LCD is currently a commonly used architecture because it can reduce the number of data lines and increase the aperture ratio. Figure 1 is one of the structural schematic diagrams of an array substrate in the prior art. Figure 2 is a schematic diagram corresponding to the arrangement of R/G/B color resistors on the color filter substrate in Figure 1 in the prior art. Figure 3 is a diagram corresponding to the prior art. The waveform diagram of the scanning signal and data signal in 1 is shown in Figure 1 to Figure 3. For conventional dual-gate architecture LCD products, when the SDRRS (seamless dynamic refresh rate switch, seamless dynamic switching) function is turned on, due to the charging time Transformation, the data signal will switch multiple times in each frame. When the frequency changes, the charging time will follow the transformation. The charging voltage of different sub-pixels is different, resulting in obvious differences in light and dark in some pictures. Moreover, the switching frequency of the data signal is too fast, and the driver The power consumption is usually relatively large. Figure 4 is a second structural schematic diagram of an array substrate in the prior art. Figure 5 is a schematic diagram corresponding to the arrangement of R/G/B color resistors on the color filter substrate in Figure 4 in the prior art. Figure 6 is a diagram corresponding to the prior art. One of the waveform diagrams of the scan signal and data signal during double-point inversion in 4. As shown in Figures 3 to 6, in order to avoid the problem of obvious differences in brightness and darkness when the SDRRS function is turned on, another dual-gate architecture LCD product distributes pixel electrodes of the same polarity in a staggered manner, so that the same data line Connect pixel electrodes of the same polarity. In each frame, the data signal does not need to be switched. The data signal only needs to be switched once per frame. Therefore, the switching and transformation amplitude of the data signal can be reduced. The pixels are charged evenly. When switching the driving frequency, The difference between light and dark is not obvious. However, although this structure can save power consumption when the data signal is switched once per frame, it can only achieve double-point inversion and cannot achieve true single-point inversion, and the display effect is relatively poor. Figure 7 is the second waveform schematic diagram corresponding to the scanning signal and the data signal during single-point inversion in the prior art Figure 4. As shown in Figure 7, when this structure needs to achieve single-point inversion, its data signal needs to be It switches every time a scan line is scanned, and the driving power consumption is relatively large.

Contents of the invention

In order to overcome the shortcomings and deficiencies in the prior art, the purpose of the present invention is to provide an array substrate, a display panel, and a display device, so as to solve the problem that the display in the prior art cannot simultaneously resolve the obvious difference in light and dark in the picture when the SDRRS function is turned on, and The problem of large power consumption of single-point reversal drive.

The object of the present invention is achieved through the following technical solutions:

The invention provides an array substrate. The array substrate is provided with a plurality of scan lines and a plurality of data lines. The plurality of scan lines and the plurality of data lines are insulated and intersected with each other and define a plurality of array-distributed lines. Pixel unit, each pixel unit includes two sub-pixel units arranged left and right, and the two sub-pixel units on the left and right sides of the same pixel unit are respectively a first sub-pixel unit and a second sub-pixel. unit, for each row of the pixel units, two adjacent pixel units are a repeating unit;

For the same repeating unit, the first sub-pixel unit and the second sub-pixel unit of one of the pixel units are respectively connected to the data lines on its left and right sides, and the other pixel unit The first sub-pixel unit and the second sub-pixel unit of the unit are respectively connected to the data lines on the right and left sides thereof;

Two scanning lines are provided between two adjacent rows of pixel units. In the same repeating unit, the first sub-pixel unit of one of the pixel units and the first sub-pixel unit of the other pixel unit are The second sub-pixel unit is connected to the same scan line, and the first sub-pixel unit and the second sub-pixel unit in the same pixel unit are connected to different scan lines respectively;

The pixel units in two adjacent rows are offset from each other by at least one sub-pixel unit in the row direction.

Further, the pixel units in odd-numbered rows and even-numbered rows are staggered from each other by one sub-pixel unit in the row direction, and the data lines have a zigzag structure.

Further, the pixel units in even-numbered rows are shifted to the right by one sub-pixel unit relative to the pixel units in odd-numbered rows; or, the pixel units in even-numbered rows are shifted to the left by one sub-pixel unit relative to the pixel units in odd-numbered rows. Pixel unit.

Further, the sub-pixel units in odd rows and N columns and the sub-pixel units in even rows and N+1 columns are connected to the same data line; or, the sub-pixel units in even rows and N columns are connected to the same data line. The sub-pixel units in the +1 column are connected to the same data line;

Where N is a positive integer greater than or equal to 1.

Further, two adjacent scan lines are respectively a first scan line and a second scan line. The first scan lines and the second scan lines are arranged alternately with each other. The first scan lines are located at corresponding On the upper side of one row of pixel units, the second scan line is located on the lower side of the corresponding row of pixel units;

The sub-pixel units in the same odd-numbered column are all connected to the first scan line or the second scan line, and the sub-pixel units in even-numbered columns are each connected to the first scan line and the second scan line; or , the sub-pixel units in the same even-numbered column are all connected to the first scan line or the second scan line, and the sub-pixel units in odd-numbered columns are each connected to the first scan line and the second scan line.

Further, the pixel units in the odd-numbered rows and the even-numbered rows are staggered by two sub-pixel units in the row direction, and the data line has a linear structure.

Further, two adjacent scan lines are respectively a first scan line and a second scan line. The first scan lines and the second scan lines are arranged alternately with each other. The first scan lines are located at corresponding On the upper side of one row of pixel units, the second scan line is located on the lower side of the corresponding row of pixel units;

Among the sub-pixel units in the same column, two adjacent sub-pixel units are respectively connected to the first scan line and the second scan line; or, the sub-pixel units in the same column are all connected to the first scan line. line or the second scan line.

Further, in the first pixel unit in the first row, the first sub-pixel unit and the second sub-pixel unit of the pixel unit are respectively connected to the data lines on the left and right sides thereof; Or the first sub-pixel unit and the second sub-pixel unit of the pixel unit are respectively connected to the data lines on the right and left sides thereof.

The present application provides a display panel, which includes a color filter substrate and an array substrate as described above. The color filter substrate and the array substrate are arranged oppositely, and a liquid crystal layer is provided between the color filter substrate and the array substrate. An upper polarizer is provided on the color filter substrate, and a lower polarizer is provided on the array substrate. The transmission axes of the upper polarizer and the lower polarizer are perpendicular to each other.

The present application also provides a display device, including the display panel as mentioned above.

Beneficial effects of the present invention:

By defining two adjacent pixel units on the left and right as a repeating unit, each pixel unit includes a first sub-pixel unit and a second sub-pixel unit arranged left and right; in the same repeating unit, the first sub-pixel unit of one of the pixel units The pixel unit and the second sub-pixel unit are respectively connected to the data lines on the left and right sides of the pixel unit, and the first sub-pixel unit and the second sub-pixel unit of another pixel unit are connected to the data lines on the right side and the left side of the pixel unit respectively; and The pixel units in two adjacent rows are staggered from each other by at least one sub-pixel unit in the row direction. This application adopts a special array substrate design, so that when the data signal is switched once per frame, SDRRS under single-point inversion can be achieved, and the display screen has no obvious difference between light and dark, while improving the display quality. , reduce drive power consumption.

Description of the drawings

Figure 1 is one of the structural schematic diagrams of an array substrate in the prior art;

Figure 2 is a schematic diagram corresponding to the arrangement structure of R/G/B color resistors on the color filter substrate in Figure 1 in the prior art;

Figure 3 is a schematic waveform diagram corresponding to the scanning signal and data signal in Figure 1 of the prior art;

Figure 4 is the second structural schematic diagram of an array substrate in the prior art;

Figure 5 is a schematic diagram corresponding to the arrangement structure of R/G/B color resistors on the color filter substrate in Figure 4 in the prior art;

Figure 6 is one of the waveform diagrams corresponding to the scanning signal and the data signal during double-point inversion in Figure 4 in the prior art;

FIG. 7 is one of the waveform diagrams corresponding to the scanning signal and the data signal during single-point inversion in FIG. 4 in the prior art;

Figure 8 is a schematic structural diagram of the array substrate in Embodiment 1 of the present invention;

Figure 9 is a schematic diagram of the arrangement structure of R/G/B color resistors on the color filter substrate in Embodiment 1 of the present invention;

Figure 10 is a schematic structural diagram of the display device in the black state according to Embodiment 1 of the present invention;

Figure 11 is a schematic structural diagram of the display device in the white state in Embodiment 1 of the present invention;

Figure 12 is a schematic structural diagram of the array substrate in Embodiment 2 of the present invention;

Figure 13 is a schematic structural diagram of the array substrate in Embodiment 3 of the present invention;

Figure 14 is a schematic diagram of the arrangement structure of R/G/B color resistors on the color filter substrate in Embodiment 3 of the present invention;

Figure 15 is a schematic structural diagram of the array substrate in Embodiment 4 of the present invention;

Figure 16 is a schematic structural diagram of the array substrate in Embodiment 5 of the present invention.

Detailed ways

In order to further elaborate on the technical means and effects adopted by the present invention to achieve the predetermined inventive purpose, the specific implementation modes, structures, and structures of the array substrate, display panel, and display device proposed according to the present invention are described below in conjunction with the accompanying drawings and preferred embodiments. Features and functions are detailed as follows:

[Example 1]

Figure 8 is a schematic structural diagram of an array substrate in Embodiment 1 of the present invention. As shown in Figure 8, an array substrate is provided in Embodiment 1 of the present invention. The array substrate is provided with multiple scan lines and multiple data lines 2. Multiple scan lines and data lines 2 are provided on the array substrate. The scanning lines and the plurality of data lines 2 are insulated and intersect with each other and define a plurality of pixel units P distributed in an array. Each pixel unit P includes two sub-pixel units arranged left and right. The two sub-pixel units on the left and right sides of the same pixel unit P are respectively the first sub-pixel unit P1 and the second sub-pixel unit P2, that is, the first sub-pixel unit P1 and the second sub-pixel unit P2. The pixel unit P1 is located on the left side of the second sub-pixel unit P2. For each row of pixel units P, two adjacent pixel units P are a repeating unit.

For the same repeating unit, the first sub-pixel unit P1 and the second sub-pixel unit P2 of one pixel unit P are respectively connected to the data lines 2 on its left and right sides, that is, the first sub-pixel unit of the pixel unit P P1 is connected to the data line 2 on the left side of the pixel unit P, and the second sub-pixel unit P2 of the pixel unit P is connected to the data line 2 on the right side of the pixel unit P. The first sub-pixel unit P1 and the second sub-pixel unit P2 of another pixel unit P are respectively connected to the data lines 2 on the right and left sides of the pixel unit P. That is, the first sub-pixel unit P1 of the pixel unit P is connected to the right side of the pixel unit P. The second sub-pixel unit P2 of the pixel unit P is connected to the data line 2 on the left side of the pixel unit P.

Two scanning lines are provided between two adjacent rows of pixel units P. In the same repeating unit, the first sub-pixel unit P1 of one pixel unit P is connected to the second sub-pixel unit P2 of another pixel unit P. A scan line. The first sub-pixel unit P1 and the second sub-pixel unit P2 in the same pixel unit P are respectively connected to different scanning lines. In this embodiment, a data line 2 is provided between two adjacent columns of pixel units P.

Two adjacent rows of pixel units P are offset from each other by at least one sub-pixel unit in the row direction.

Among them, the sub-pixel unit is connected to the scanning line and the data line 2, and it can be understood that its corresponding pixel electrode is electrically connected to the scanning line and the data line 2 through a thin film transistor.

As shown in FIG. 8 , the pixel units P in the odd rows and the even rows are staggered by one sub-pixel unit in the row direction, and the data line 2 has a zigzag structure.

In this embodiment, the pixel units P in the even rows are shifted to the right by one sub-pixel unit relative to the pixel units P in the odd rows. The sub-pixel units in odd-numbered rows and N columns and the sub-pixel units in even-numbered rows and N+1 columns are connected to the same data line 2. Of course, in other embodiments, the pixel units P in the even rows are shifted to the left by one sub-pixel unit relative to the pixel units P in the odd rows. The sub-pixel units in even rows and N columns and the sub-pixel units in odd rows and N+1 columns are connected to the same data line 2. Among them, N is a positive integer greater than or equal to 1.

Further, two adjacent scan lines are respectively a first scan line 11 and a second scan line 12. The first scan lines 11 and the second scan lines 12 are arranged alternately with each other. The first scan line 11 is located in a corresponding row of pixel units. On the upper side of P, the second scanning line 12 is located on the lower side of the corresponding row of pixel units P. The sub-pixel units in the same even-numbered columns are all connected to the first scan line 11 or the second scan line 12 , and the sub-pixel units in the odd-numbered columns are each connected to the first scan line 11 and the second scan line 12 . As shown in FIG. 8 , the sub-pixel units in the 2nd, 6th, 10...2+4M columns are all connected to the first scan line 11, and the sub-pixel units in the 4th, 8th, 12...4+4M columns are all connected to the second scan line 12. Among the sub-pixel units in odd-numbered columns, some of the sub-pixel units are connected to the first scanning line 11 , and another part of the sub-pixel units are connected to the second scanning line 12 . Among them, M is a positive integer greater than or equal to 0.

Further, in the first pixel unit P of the first row, the first sub-pixel unit P1 and the second sub-pixel unit P2 of the pixel unit P are respectively connected to the data lines 2 on the left and right sides thereof, that is, the first sub-pixel unit P1 of the first row The first sub-pixel unit P1 of a pixel unit P is connected to the data line 2 on the left side of the pixel unit P, and the first pixel unit P of the first row is connected to the data line 2 on the right side of the pixel unit P. Due to this design, at least one column of sub-pixel units on the left and right sides of the array substrate are invalid pixels. For example, the first column and the last column of sub-pixel units are invalid pixels. The color filter substrate does not have a color resist layer 312 in the area corresponding to the invalid pixels. Instead, it is covered by the black matrix 311, as shown in Figure 9.

FIG. 9 is a schematic structural diagram of the arrangement of R/G/B color resistors on the color filter substrate in Embodiment 1 of the present invention. FIG. 10 is a schematic structural diagram of the display device in the black state in Embodiment 1 of the present invention. Figure 11 is a schematic structural diagram of the display device in the white state in Embodiment 1 of the present invention. As shown in Figures 9 to 11, the present invention also provides a display device, including a display panel 30 and a backlight module 40. The backlight module 40 Located below the display panel 30 , it is used to provide a backlight source for the display panel 30 .

The backlight module 40 may be an edge-type backlight module or a direct-type backlight module. Preferably, the backlight module 40 adopts a collimated backlight (CBL) mode, which can collect light to ensure the display effect.

The backlight module 40 includes a backlight source 41 and a privacy layer 43 . The privacy layer 43 is used to reduce the range of light emission angles. A brightness enhancement film 42 is also provided between the backlight source 41 and the privacy layer 43 . The brightness enhancement film 42 increases the brightness of the backlight module 40 . Among them, the privacy-preventing layer 43 is equivalent to a miniature blind structure, which can block light with a larger incident angle and allow light with a smaller incident angle to pass through, thereby reducing the angle range of the light passing through the privacy-preventing layer 43 . The anti-privacy layer 43 includes a plurality of photoresist walls arranged in parallel and a light-transmitting hole located between two adjacent photoresist walls. Light-absorbing materials are provided on both sides of the photoresist wall. Of course, the backlight 41 can also be a light-concentrating backlight, so that there is no need to provide the privacy layer 43 , but the light-concentrating backlight is more expensive than a conventional backlight.

The present application also provides a display panel 30 for use in the display device as described above. As shown in FIGS. 9 to 11 , the display panel 30 includes a color filter substrate 31 and an array substrate 32 as described above. The color filter substrate 31 and the array substrate 32 are arranged opposite to each other. A liquid crystal is disposed between the color filter substrate 31 and the array substrate 32 . Layer 33. The liquid crystal layer 33 preferably uses positive liquid crystal molecules, that is, liquid crystal molecules with positive dielectric anisotropy. In the initial state, the positive liquid crystal molecules in the liquid crystal layer 33 are aligned parallel to the color filter substrate 31 and the array substrate 32. The positive liquid crystal molecules on the side close to the color filter substrate 31 are aligned with the positive liquid crystal molecules on the side close to the array substrate 32. The molecules are aligned in parallel or antiparallel directions. Of course, in other embodiments, the liquid crystal layer 33 can also use negative liquid crystal molecules. The negative liquid crystal molecules in the liquid crystal layer 33 can be aligned perpendicularly to the color filter substrate 31 and the array substrate 32 , that is, the alignment is similar to the VA display mode. Way.

The color filter substrate 31 is provided with a color resist layer 312 arranged in an array and a black matrix 311 that separates the color resist layers 312. The color resist layer 312 includes three colors: red (R), green (G), and blue (B). Color resist material, and correspondingly form sub-pixel units of three colors: red (R), green (G), and blue (B). As shown in Figure 9, the color resistors on the color filter substrate 31 are arranged in a conventional arrangement of red (R), green (G), and blue (B), that is, one column of red (R) color resistors and one column of green (G) color resistors. The color resistors and a row of blue (B) color resistors form a repeating cycle and are arranged sequentially on the color filter substrate 31 .

In this embodiment, a common electrode 321 is also provided on the side of the array substrate 32 facing the liquid crystal layer 33. The common electrode 321 and the pixel electrode 322 are located on different layers and are insulated and isolated by an insulating layer. The common electrode 321 may be located above or below the pixel electrode 322 (shown in FIG. 10 is that the common electrode 321 is located below the pixel electrode 322). Preferably, the common electrode 321 is a planar electrode provided over the entire surface, and the pixel electrode 322 is a block electrode provided entirely within each pixel unit or a slit electrode with multiple electrode strips to form a fringe field switching mode ( Fringe Field Switching (FFS). Of course, in other embodiments, the pixel electrode 322 and the common electrode 321 may be located on the same layer, but they are insulated from each other. Each of the pixel electrode 322 and the common electrode 321 may include multiple electrode strips. The electrode strips of the pixel electrode 322 The electrode strips of the common electrode 321 are alternately arranged to form an in-plane switching mode (IPS); or, in other embodiments, the array substrate 32 is provided with a pixel electrode 322 on the side facing the liquid crystal layer 33 , the color filter substrate 31 is provided with a common electrode 321 on the side facing the liquid crystal layer 33 to form a TN mode or a VA mode.

The color filter substrate 31 is provided with an upper polarizer 51 , and the array substrate 32 is provided with a lower polarizer 52 . The transmission axes of the upper polarizer 51 and the lower polarizer 52 are perpendicular to each other.

Among them, the color filter substrate 31 and the array substrate 32 can be made of glass, acrylic, polycarbonate and other materials. The common electrode 321 and the pixel electrode 322 may be made of indium tin oxide (ITO) or indium zinc oxide (IZO).

[Example 2]

Figure 12 is a schematic structural diagram of an array substrate in Embodiment 2 of the present invention. As shown in Figure 12, the array substrate, display panel, display device provided in Embodiment 2 of the present invention are the same as the array in Embodiment 1 (Figures 8 to 11). The substrate, display panel, and display device are basically the same, except that in this embodiment:

The sub-pixel units in the same odd-numbered columns are all connected to the first scan line 11 or the second scan line 12 , and the sub-pixel units in the even-numbered columns are each connected to the first scan line 11 and the second scan line 12 . As shown in Figure 12, the sub-pixel units in the 3rd, 7th, 11...3+4M columns are all connected to the first scan line 11, and the sub-pixel units in the 5th, 9th, 13...5+4M columns are all connected to the second scan line 12. Among the sub-pixel units in the even columns, some of the sub-pixel units are connected to the first scanning line 11 , and another part of the sub-pixel units are connected to the second scanning line 12 . Among them, is a positive integer greater than or equal to 0. Through such an array substrate design, the structure of the pixels is more regular, which facilitates the design of the mask for manufacturing the array substrate.

Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1, and will not be described again here.

[Embodiment 3]

Figure 13 is a schematic structural diagram of the array substrate in the third embodiment of the present invention. Figure 14 is a schematic structural diagram of the arrangement of R/G/B color resistors on the color filter substrate in the third embodiment of the present invention, as shown in Figures 13 and 14. The array substrate, display panel, and display device provided in the third embodiment of the present invention are basically the same as the array substrate, display panel, and display device in the first embodiment (Fig. 8 to Fig. 11) and the second embodiment (Fig. 12). The differences are That is, in this embodiment:

In the first pixel unit P in the first row, the first sub-pixel unit P1 and the second sub-pixel unit P2 of the pixel unit P are respectively connected to the data lines 2 on the right and left sides thereof, that is, the first pixel in the first row. The first sub-pixel unit P1 of the unit P is connected to the data line 2 on the right side of the pixel unit P, and the first pixel unit P in the first row is connected to the data line 2 on the left side of the pixel unit P. Through such an array substrate design, the number of invalid images can be reduced and the utilization rate of pixels can be improved.

Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1 and Embodiment 2, and will not be described again here.

[Embodiment 4]

Figure 15 is a schematic structural diagram of an array substrate in Embodiment 4 of the present invention. As shown in Figure 15, the array substrate, display panel, display device provided in Embodiment 4 of the present invention are the same as the array in Embodiment 1 (Figures 8 to 11). The substrate, display panel, and display device are basically the same, except that in this embodiment:

The pixel units P in the odd rows and the even rows are offset from each other by two sub-pixel units in the row direction, that is, they are offset by one pixel unit P. Data line 2 has a linear structure. For example, the first sub-pixel unit P1 of the first pixel unit P in the first row is connected to the data line 2 on the left side of the pixel unit P, and the second sub-pixel unit P2 of the pixel unit P is connected to the data line on the right side of the pixel unit P. 2; Since the pixel units P in the odd rows and the even rows are staggered by two sub-pixel units in the row direction, the first sub-pixel unit P1 of the second pixel unit P in the second row is connected to the data line on the left side of the pixel unit P. 2. The second sub-pixel unit P2 of the pixel unit P is connected to the data line 2 on the right side of the pixel unit P.

Further, two adjacent scan lines are respectively a first scan line 11 and a second scan line 12. The first scan lines 11 and the second scan lines 12 are arranged alternately with each other. The first scan line 11 is located in a corresponding row of pixel units. On the upper side of P, the second scanning line 12 is located on the lower side of the corresponding row of pixel units P.

In this embodiment, in the same column of sub-pixel units, two adjacent sub-pixel units are connected to the first scan line 11 and the second scan line 12 respectively. That is, in the same column of sub-pixel units, some sub-pixel units are connected to the first scan line 11, and the other two sub-pixel units are connected to the first scan line 11 and the second scan line 12. A part of the sub-pixel units are connected to the second scan line 12 . Of course, in other embodiments, the sub-pixel units in the same column may also be connected to the first scan line 11 or the second scan line 12 .

Compared with Embodiment 1, the array substrate design of this embodiment can reduce the resistance and manufacturing difficulty of the data line 2, reduce the number of invalid images, and improve the utilization rate of pixels.

Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1, and will not be described again here.

[Embodiment 5]

Figure 16 is a schematic structural diagram of the array substrate in Embodiment 5 of the present invention. As shown in Figure 16, the array substrate, display panel, and display device provided in Embodiment 5 of the present invention are basically the same as the array substrate, display panel, and display device in Embodiment 4 (Figure 15). The difference is that in this embodiment Example:

In the first pixel unit P in the first row, the first sub-pixel unit P1 and the second sub-pixel unit P2 of the pixel unit P are respectively connected to the data lines 2 on the right and left sides thereof, that is, the first pixel in the first row. The first sub-pixel unit P1 of the unit P is connected to the data line 2 on the right side of the pixel unit P, and the first pixel unit P in the first row is connected to the data line 2 on the left side of the pixel unit P.

Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 4, and will not be described again here.

In this article, the locative terms such as up, down, left, right, front, and back are defined based on the positions of the structures in the drawings and the positions of the structures relative to each other. They are only for the purpose of expressing the technical solution. Clear and convenient. It should be understood that the use of the locative words shall not limit the scope of protection claimed in this application. It should also be understood that the terms “first”, “second”, etc. used herein are only used for distinction in name and are not used to limit the number or order.

The above are only preferred embodiments of the present invention, and do not limit the present invention in any form. Although the present invention has been disclosed above in preferred embodiments, they are not intended to limit the present invention. Anyone familiar with this field will Skilled personnel, without departing from the scope of the technical solution of the present invention, can use the technical content disclosed above to make some changes or modifications, which are equivalent embodiments of equivalent changes. However, without departing from the technical solution content of the present invention, according to the present invention Technical Essence of the Invention Any simple modifications, equivalent changes and modifications made to the above embodiments still fall within the protection scope of the technical solution of the invention.

Claims (10)

1. The array substrate is characterized in that a plurality of scanning lines and a plurality of data lines (2) are arranged on the array substrate, the scanning lines and the data lines (2) are mutually insulated and crossed to define a plurality of pixel units (P) distributed in an array, each pixel unit (P) comprises two sub-pixel units which are arranged left and right, the two sub-pixel units on the left side and the right side in the same pixel unit (P) are respectively a first sub-pixel unit (P1) and a second sub-pixel unit (P2), and in each row of pixel units (P), two adjacent pixel units (P) are one repeating unit;

for the same repeating unit, the first sub-pixel unit (P1) and the second sub-pixel unit (P2) of one of the pixel units (P) are respectively connected to the data lines (2) on the left and right sides thereof, and the first sub-pixel unit (P1) and the second sub-pixel unit (P2) of the other pixel unit (P) are respectively connected to the data lines (2) on the right and left sides thereof;

two scanning lines are arranged between two adjacent rows of pixel units (P), and for the same repeating unit, the first sub-pixel unit (P1) of one pixel unit (P) and the second sub-pixel unit (P2) of the other pixel unit (P) are connected with the same scanning line, and the first sub-pixel unit (P1) and the second sub-pixel unit (P2) in the same pixel unit (P) are respectively connected with different scanning lines;

at least one sub-pixel unit is staggered between two adjacent rows of pixel units (P) in the row direction.

2. The array substrate according to claim 1, wherein the pixel units (P) in the odd-numbered rows and the even-numbered rows are staggered with each other by one sub-pixel unit in the row direction, and the data line (2) has a zigzag structure.

3. The array substrate according to claim 2, wherein the pixel units (P) of even rows are staggered one sub-pixel unit to the right with respect to the pixel units (P) of odd rows; alternatively, the pixel units (P) of the even-numbered rows are staggered one sub-pixel unit to the left with respect to the pixel units (P) of the odd-numbered rows.

4. The array substrate according to claim 2, wherein the sub-pixel units of odd-numbered rows and N columns are connected to the same data line (2) as the sub-pixel units of even-numbered rows and n+1 columns; or the sub-pixel units of the even-numbered rows and the N columns and the sub-pixel units of the odd-numbered rows and the N+1 columns are connected with the same data line (2);

wherein N is a positive integer greater than or equal to 1.

5. The array substrate according to claim 2, wherein two adjacent scanning lines are a first scanning line (11) and a second scanning line (12), respectively, the first scanning line (11) and the second scanning line (12) are alternately arranged with each other, the first scanning line (11) is located at an upper side of a corresponding row of the pixel units (P), and the second scanning line (12) is located at a lower side of the corresponding row of the pixel units (P);

the sub-pixel units of the same odd columns are connected with the first scanning line (11) or the second scanning line (12), and the sub-pixel units of the even columns are respectively connected with the first scanning line (11) and the second scanning line (12); or the same even number column of the sub-pixel units are connected with the first scanning line (11) or the second scanning line (12), and the odd number column of the sub-pixel units are respectively connected with the first scanning line (11) and the second scanning line (12).

6. The array substrate according to claim 1, wherein the pixel units (P) in the odd-numbered rows and the even-numbered rows are staggered with each other in the row direction by two sub-pixel units, and the data lines (2) are of a linear structure.

7. The array substrate according to claim 6, wherein two adjacent scanning lines are a first scanning line (11) and a second scanning line (12), respectively, the first scanning line (11) and the second scanning line (12) are alternately arranged with each other, the first scanning line (11) is located at an upper side of a corresponding row of the pixel units (P), and the second scanning line (12) is located at a lower side of the corresponding row of the pixel units (P);

in the same column of the sub-pixel units, two adjacent sub-pixel units are respectively connected with the first scanning line (11) and the second scanning line (12); or the sub-pixel units in the same column are connected with the first scanning line (11) or the second scanning line (12).

8. The array substrate according to any one of claims 1 to 7, wherein in a first one of the pixel units (P) of a first row, the first and second sub-pixel units (P1, P2) of the pixel unit (P) are connected to the data lines (2) on the left and right sides thereof, respectively; or the first sub-pixel unit (P1) and the second sub-pixel unit (P2) of the pixel unit (P) are respectively connected with the right and left data lines (2) thereof.

9. A display panel, characterized by, including various membrane base plate (31) and array substrate (32) according to any one of claims 1-8, various membrane base plate (31) with array substrate (32) set up relatively, various membrane base plate (31) with be equipped with liquid crystal layer (33) between array substrate (32), be equipped with on various membrane base plate (31) polarizer (51), be equipped with on array substrate (32) lower polarizer (52), go up polarizer (51) with the printing opacity axle mutually perpendicular of lower polarizer (52).

10. A display device comprising a display panel (30) as claimed in claim 9.