CN115656788B - Chip testing system, method, equipment and storage medium - Google Patents

Abstract

The present disclosure provides a chip testing system, method, device and storage medium, the system includes: an ATE controller for writing a test command into a chip to be tested by an ATE machine; and an ATE controller for sending a test command queue to The CPU corresponding to each test command; the CPU is used to execute the test command and write the execution result into the return result queue of the ATE controller after the test command is executed; the fingerprint engine of the chip to be tested is used to generate and test according to the access information of the CPU The fingerprint information corresponding to the command and write the fingerprint information into the return result queue of the ATE controller; the ATE machine is also used to read the execution result and fingerprint information corresponding to each test command in the ATE controller, and write the execution result and fingerprint information separately The preset execution result corresponding to each test command is compared with the preset fingerprint information to determine whether the test command passes the test. The system improves the test speed and reduces the test cost.

Description

A chip test system, method, equipment and storage medium

technical field

The present disclosure relates to the field of chip technology, and in particular to a chip testing system, method, device and storage medium.

Background technique

SoC (System-on-a-Chip, single-chip system) chips usually need to be tested before they are put into use, and they will be put into use only when there is no problem in the test. The commonly used test method for chips is SCAN (scanning) test method. SCAN is a purely digital logic test method. For chips with analog circuit modules, the test cannot usually be completed by the SCAN test method.

At present, the structure of the chip is becoming more and more complex, and the chip may contain analog circuit modules and digital-analog hybrid circuit modules. When testing such complex chips, these circuit modules of the chip cannot pass pure digital circuits such as SCAN To test with a logical method, you must send a response through the ATE (Automatic Test Equipment, automated test equipment) machine, and let the chip run the response to test. Because in the way of chip testing through ATE machine, the tests can only be run one by one, and each test needs to send a response to the chip through the interface of the ATE machine, and read the running data of the chip to judge whether the test is completed correctly , which leads to too long test time of the chip and high test cost. In addition, for some non-volatile memory inside complex chips, it is impossible to use the general ATE machine test method for testing, and usually requires special ATE test development for non-volatile memory, which also leads to long test time and test cost high.

Therefore, how to reduce the chip testing time and save the chip testing cost has become an urgent problem to be solved.

Contents of the invention

The present disclosure provides a chip testing system, method, device and storage medium to at least solve the above technical problems existing in the prior art.

According to a first aspect of the present disclosure, a chip testing system is provided, the system comprising:

Automatic test equipment ATE machine, used to write test commands into the ATE controller of the chip to be tested;

The ATE controller is configured to read the test command written by the ATE machine, and send the test command queue to each CPU corresponding to each test command; wherein, the test command queue includes a plurality of test commands, each A test command corresponds to a CPU of the chip to be tested;

Each CPU of the chip to be tested is used to read the test command corresponding to itself in the test command queue, execute the test command, and write the execution result into the ATE controller after executing the test command The return result queue;

The fingerprint engine of the chip to be tested is used to obtain the access information of each CPU during the execution of the test command by each CPU, and generate fingerprint information corresponding to the test command according to the access information, and perform After the test command is executed, write the fingerprint information into the return result queue of the ATE controller; wherein, the access information of the CPU includes the access address, access data and control signal of the CPU;

The ATE machine is also used to read the execution result and fingerprint information corresponding to each test command in the return result queue of the ATE controller, and determine the preset execution result and preset execution result corresponding to each test command based on the ID of the test command. Fingerprint information, and compare the execution result and fingerprint information of each test command with the preset execution result and preset fingerprint information corresponding to each test command, if the execution result and fingerprint information of each test command are respectively corresponding to the test command If the preset execution result is consistent with the preset fingerprint information, the test command passes the test; otherwise, the test result is determined as the test command fails the test.

In a possible implementation manner, the ATE controller is specifically configured to read the test command written by the ATE machine, and send the interrupt signal for the test command queue to the interrupt control of each CPU corresponding to each test command device, and after each CPU has read the test command corresponding to itself in the test command queue based on the interrupt signal received by the interrupt controller, release the space occupied by the test command in the test command queue;

The ATE machine is also used to detect whether there is freed space in the test command queue, and if so, write a new test command to the ATE controller.

In a possible implementation manner, the ATE machine is specifically used for

Read the return result queue status of the ATE controller, judge whether there is an operation result in the return result queue of the ATE controller, if yes, read the execution corresponding to each test command in the return result queue of the ATE controller The result and fingerprint information, so that the ATE controller releases the space occupied by the read execution result and fingerprint information in the return result queue of the ATE controller.

In a possible implementation manner, the test function for executing the test command in the chip to be tested is solidified in the ROM memory of the chip to be tested or the SRAM memory of the chip to be tested;

Each of the CPUs is specifically configured to read the test command corresponding to itself in the test command queue, jump to the target memory storing the test function according to the test command, and use the test function in the target memory Execute the test command, and write the execution result into the return result queue of the ATE controller after the test command is executed.

In a possible implementation manner, the fingerprint engine of the chip to be tested is also used to store fingerprint information corresponding to each key test node of each test command in the SRAM memory in the chip to be tested;

The ATE machine is also used to call the fingerprint information corresponding to each key test node of the test command stored in the SRAM memory when the fingerprint information of the test command is inconsistent with the preset fingerprint information corresponding to the test command Compared with the preset fingerprint information, abnormal test nodes are determined.

In a possible implementation manner, the ATE controller is also used for each test command queue to determine whether all test commands in the test command queue return corresponding execution results within a preset time period, and if not, determine The execution of the test command in the test command queue is abnormal.

According to a second aspect of the present disclosure, a chip testing method is provided, the method is applied to a chip to be tested in a chip testing system, the chip to be tested includes an ATE controller, at least one CPU, and a fingerprint engine, and the method includes :

The ATE controller reads the test command written by the ATE machine of the chip test system, and sends the test command queue to the CPU corresponding to each test command; wherein the test command queue includes a plurality of test commands, Each test command corresponds to a CPU of the chip to be tested;

Each of the CPUs reads the test command corresponding to itself in the test command queue, executes the test command, and writes the execution result into the return result queue of the ATE controller after executing the test command ;

The fingerprint engine obtains the access information of each CPU during the execution of the test command by each CPU, and generates fingerprint information corresponding to the test command according to the access information, and generates the fingerprint information corresponding to the test command when the test command is executed. Then write the fingerprint information into the return result queue of the ATE controller, so that the ATE machine performs the following steps:

Read the execution result and fingerprint information corresponding to each test command in the return result queue of the ATE controller, determine the preset execution result and preset fingerprint information corresponding to each test command based on the ID of the test command, and store the corresponding test results of each test command The execution result and fingerprint information are compared with the preset execution result and preset fingerprint information corresponding to each test command, if the execution result and fingerprint information of each test command are respectively compared with the preset execution result and preset fingerprint information corresponding to the test command If they are consistent, it is determined that the test result is that the test command passes the test; otherwise, it is determined that the test result is that the test command fails the test; wherein, the access information of the CPU includes the access address, access data and control signals of the CPU.

In a possible implementation manner, the reading of the test command written by the ATE machine of the chip test system, and sending the test command queue to the corresponding CPU of each test command includes:

Read the test command written by the ATE machine, and send the interrupt signal for the test command queue to the interrupt controller of each CPU corresponding to each test command;

After each CPU reads the test command corresponding to itself in the test command queue based on the interrupt signal received by the interrupt controller, the space occupied by the test command in the test command queue is released, so that: The ATE machine detects whether there is released space in the test command queue, and if so, writes a new test command to the ATE controller.

In a possible implementation manner, the test function for executing the test command in the chip to be tested is solidified in the ROM memory of the chip to be tested or the SRAM memory of the chip to be tested;

The reading the test command corresponding to itself in the test command queue, executing the test command, and writing the execution result into the return result queue of the ATE controller after executing the test command, including:

Read the test command corresponding to itself in the test command queue;

Jumping to the target memory storing the test function according to the test command;

Execute the test command by using the test function in the target memory, and write the execution result into the return result queue of the ATE controller after the test command is executed.

In one possible embodiment, the method also includes:

The fingerprint engine stores the fingerprint information corresponding to each key test node of each test command in the SRAM memory in the chip to be tested; so that: the ATE machine, when the fingerprint information of the test command exists and the test When the preset fingerprint information corresponding to the command is inconsistent, the fingerprint information corresponding to each key test node of the test command stored in the SRAM memory is called to compare with the preset fingerprint information, and the abnormal test node is determined.

In one possible embodiment, the method also includes:

The ATE controller, for each test command queue, determines whether all test commands in the test command queue return corresponding execution results within a preset time period, and if not, determines that the test command execution of the test command queue is abnormal.

According to a third aspect of the present disclosure, a chip testing method is provided, the method is applied to an ATE machine of a chip testing system, and the method includes:

The test command is written into the ATE controller of the chip to be tested, so that: the ATE controller sends the test command queue to each CPU corresponding to each test command; each CPU of the chip to be tested reads the test command queue The test command corresponding to itself, and execute the test command, and write the execution result into the return result queue of the ATE controller after executing the test command; the fingerprint engine of the chip to be tested is in each CPU Obtain the access information of each CPU during the process of executing the test command, and generate fingerprint information corresponding to the test command according to the access information, and write the fingerprint information into the return result queue of the ATE controller; Wherein, the test command queue includes a plurality of test commands, each test command corresponds to a CPU of the chip to be tested, and the access information of the CPU includes the access address, access data and control signals of the CPU;

Read execution results and fingerprint information corresponding to each test command in the return result queue of the ATE controller;

Determine the preset execution result and preset fingerprint information corresponding to each test command based on the ID of the test command, and compare the execution result and fingerprint information of each test command with the preset execution result and preset fingerprint information corresponding to each test command ;

If the execution result and fingerprint information of each test command are consistent with the preset execution result and preset fingerprint information corresponding to the test command, the test result is determined to be that the test command passes the test; otherwise, the test result is determined to be that the test command fails the test .

According to a fourth aspect of the present disclosure, an electronic device is provided, including:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,

The memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor, to enable the at least one processor to perform the methods described in the present disclosure.

According to a fourth aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute the method described in the present disclosure.

In the chip testing system, method, equipment and storage medium of the present disclosure, the ATE machine no longer needs to write test programs and read test data to the chip one by one, but only needs to send a test command to the chip to be tested, and then can use the chip to be tested. Multiple CPUs execute each test command in the test command queue. Since the operating speed of the CPU is much higher than the transmission speed of the ATE interface, using the CPU of the chip to be tested to execute the test program can increase the test speed exponentially, thus reducing the test time. time, reducing the cost of testing. Moreover, the result of the chip to be tested returned to the ATE machine is automatically generated by the fingerprint engine of the chip to be tested, and the ATE machine does not need to spend extra time to read the results for comparison, that is, the ATE machine only needs to The ATE interface of the chip to be tested sends the test command and reads the test result to determine whether the test command passes the test, which greatly reduces the amount of data transmitted between the ATE machine and the ATE interface of the chip to be tested, thus greatly improving the test speed. The test time is further reduced and the test cost is reduced.

It should be understood that what is described in this section is not intended to identify key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will be readily understood through the following description.

Description of drawings

The above and other objects, features and advantages of exemplary embodiments of the present disclosure will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the present disclosure are shown by way of illustration and not limitation, in which:

In the drawings, the same or corresponding reference numerals denote the same or corresponding parts.

FIG. 1 shows a schematic structural diagram of a chip testing system provided by an embodiment of the present disclosure;

FIG. 2 shows a schematic diagram of a chip testing system provided by an embodiment of the present disclosure;

FIG. 3 shows another schematic diagram of a chip testing system provided by an embodiment of the present disclosure;

FIG. 4 shows another schematic diagram of a chip testing system provided by an embodiment of the present disclosure;

FIG. 5 shows a schematic flowchart of a chip testing method applied to a chip provided by an embodiment of the present disclosure;

FIG. 6 shows a schematic flowchart of a chip testing method applied to an ATE machine provided by an embodiment of the present disclosure;

FIG. 7 shows a schematic diagram of the composition and structure of an electronic device according to an embodiment of the present disclosure.

Detailed ways

In order to make the purpose, features, and advantages of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described The embodiments are only some of the embodiments of the present disclosure, but not all of them. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative efforts belong to the protection scope of the present disclosure.

Because the current method for testing chips takes too long and the testing cost is too high, therefore, in order to reduce the chip testing time and save the chip testing cost, the present disclosure provides a chip testing system, method, device and storage medium.

The technical solutions of the embodiments of the present disclosure will be described below with reference to the drawings in the embodiments of the present disclosure.

Fig. 1 shows a schematic structural diagram of a chip testing system provided by an embodiment of the present disclosure. As shown in Fig. 1, the system includes:

Automated testing equipment ATE machine 101, for writing test commands into the ATE controller of the chip to be tested;

The ATE controller 102 is configured to read the test command written by the ATE machine, and send the test command queue to each CPU corresponding to each test command; wherein, the test command queue includes a plurality of test commands, Each test command corresponds to a CPU of the chip to be tested;

Each CPU103 of the chip to be tested is used to read the test command corresponding to itself in the test command queue, execute the test command, and write the execution result into the ATE controller after executing the test command The return result queue;

The fingerprint engine 104 of the chip to be tested is used to obtain the access information of each CPU during the execution of the test command by each CPU, and generate fingerprint information corresponding to the test command according to the access information, and perform After the execution of the test command is completed, the fingerprint information is written into the return result queue of the ATE controller; wherein, the access information of the CPU includes the access address, access data and control signal of the CPU;

The ATE machine 101 is also used to read the execution result and fingerprint information corresponding to each test command in the return result queue of the ATE controller, and determine the preset execution result and preset execution result corresponding to each test command based on the ID of the test command. Set fingerprint information, and compare the execution results and fingerprint information of each test command with the preset execution results and preset fingerprint information corresponding to each test command, if the execution results and fingerprint information of each test command correspond to the test command If the preset execution result is consistent with the preset fingerprint information, the test result is determined to be that the test command passes the test; otherwise, the test result is determined to be that the test command fails the test.

With the chip test system of the present disclosure, the ATE machine no longer needs to write test programs and read test data to the chip one by one, but only needs to send test commands to the chip to be tested, and then can use multiple CPUs in the chip to be tested to perform the test For each test command in the command queue, since the running speed of the CPU is much higher than the transmission speed of the ATE interface, using the CPU of the chip to be tested to execute the test program can increase the test speed exponentially, thereby reducing the test time and cost. . Moreover, the result of the chip to be tested returned to the ATE machine is automatically generated by the fingerprint engine of the chip to be tested, and the ATE machine does not need to spend extra time to read the results for comparison, that is, the ATE machine only needs to The ATE interface of the chip to be tested sends the test command and reads the test result to determine whether the test command passes the test, which greatly reduces the amount of data transmitted between the ATE machine and the ATE interface of the chip to be tested, thus greatly improving the test speed. The test time is further reduced and the test cost is reduced.

In the present disclosure, the test command includes not only the test command ID but also the ID of the CPU corresponding to the test command, and the ATE controller can send the test command to the CPU corresponding to the CPU ID according to the CPU ID contained in the test command, so that the CPU Execute the test command. Before the ATE machine writes the test command into the ATE controller of the chip to be tested, it can assign the ID of the idle CPU to the test command, so that the ATE controller sends the test command to the idle CPU, and utilizes the idle CPU The CPU executes the test command to increase the utilization rate of the CPU when performing chip testing. Based on this, in a possible implementation manner, the ATE controller is specifically configured to read the test command written by the ATE machine, and send an interrupt signal for the test command queue to each CPU corresponding to each test command interrupt controller, and after each CPU has read the test command corresponding to itself in the test command queue based on the interrupt signal received by the interrupt controller, release the test command occupied by the test command queue space;

The ATE machine is also used to detect whether there is freed space in the test command queue, and if so, write a new test command to the ATE controller.

Specifically, the internal command queue of the ATE controller can receive the test command written by the ATE machine, and send an interrupt signal to the interrupt controller of each CPU corresponding to the test command, and each CPU receives the test command based on the interrupt controller. After the interrupt signal reads the test command corresponding to itself, the ATE controller can release the space occupied by the read test command in the test command queue.

In a possible implementation manner, the ATE machine is specifically used to read the return result queue status of the ATE controller, determine whether there is an operation result in the return result queue of the ATE controller, and if so, read Execution results and fingerprint information corresponding to each test command in the return result queue of the ATE controller, so that the ATE controller releases the read execution results and fingerprint information in the return result queue of the ATE controller. space.

In a possible implementation manner, the test function used to execute the test command in the chip to be tested is solidified in the ROM memory of the chip to be tested or the SRAM memory of the chip to be tested;

Each of the CPUs is specifically configured to read the test command corresponding to itself in the test command queue, jump to the target memory storing the test function according to the test command, and use the test function in the target memory Execute the test command, and write the execution result into the return result queue of the ATE controller after the test command is executed.

In this embodiment, the ATE machine can download the test function for executing the test command to the SRAM or ROM inside the chip to be tested before the test starts. The parameter of the test command may point the CPU to the target memory storing the test function. If the target memory is the ROM memory of the chip to be tested, it means that the test function is stored in the ROM memory of the chip to be tested, then the parameter of the test command can point to the address of the test function in the ROM memory for the CPU, so that the CPU can use the test function in the ROM memory. Function executes described test command; If the target memory is the SRAM memory of the chip to be tested, it means that the test function is stored in the SRAM memory of the chip to be tested, then the parameter of the test command can point to the address of the test function in the SRAM memory for the CPU, so that The CPU executes the test command using the test function in the SRAM memory.

In a possible implementation manner, the node fingerprint information storage parameter of the test command can indicate whether the fingerprint engine of the chip to be tested stores the fingerprint information corresponding to each key test node, when the node fingerprint information storage parameter indicates that the fingerprint engine of the chip to be tested When storing the state of the fingerprint information corresponding to each key test node, the fingerprint engine of the chip to be tested can also be used to store the fingerprint information corresponding to each key test node of each test command in the chip to be tested In SRAM memory;

The ATE machine is also used to call the fingerprint information corresponding to each key test node of the test command stored in the SRAM memory when the fingerprint information of the test command is inconsistent with the preset fingerprint information corresponding to the test command Compared with the preset fingerprint information, abnormal test nodes are determined.

In a possible implementation manner, the ATE controller is also used for each test command queue to determine whether all test commands in the test command queue return corresponding execution results within a preset time period, and if not, determine The execution of the test command in the test command queue is abnormal.

In a possible implementation manner, the fingerprint engine of the chip to be tested is also used to store fingerprint information corresponding to each key test node of each test command in the SRAM memory in the chip to be tested;

The ATE machine is also used to call the fingerprint information corresponding to each key test node of the test command stored in the SRAM memory when the fingerprint information of the test command is inconsistent with the preset fingerprint information corresponding to the test command Compared with the preset fingerprint information, abnormal test nodes are determined.

With the chip test system of the present disclosure, the ATE machine no longer needs to write test programs and read test data to the chip one by one, but only needs to send test commands to the chip to be tested, and then can use multiple CPUs in the chip to be tested to perform the test For each test command in the command queue, since the running speed of the CPU is much higher than the transmission speed of the ATE interface, using the CPU of the chip to be tested to execute the test program can increase the test speed exponentially, thereby reducing the test time and cost. . Moreover, the result of the chip to be tested returned to the ATE machine is automatically generated by the fingerprint engine of the chip to be tested, and the ATE machine does not need to spend extra time to read the results for comparison, that is, the ATE machine only needs to The ATE interface of the chip to be tested sends the test command and reads the test result to determine whether the test command passes the test, which greatly reduces the amount of data transmitted between the ATE machine and the ATE interface of the chip to be tested, thus greatly improving the test speed. The test time is further reduced and the test cost is reduced.

In a possible implementation manner, FIG. 2 shows a schematic diagram of a chip testing system provided by an embodiment of the present disclosure. As shown in Figure 2, ATE Tester is the ATE machine; SoC is the chip to be tested; ATE test is the test command; ATE CTRL is the ATE controller of the chip to be tested, and ATE test pattern structure in ATE CTRL is the test command queue ;SRAM is the SRAM memory of the chip to be tested. The ATE programs in the SRAM refer to the test programs written into the SRAM by the ATE machine. The Signature Dump area in the SRAM is used to store the keys of each test command written by the fingerprint engine in the SRAM. The fingerprint information area corresponding to the test node; CPU0 and CPU1 are the CPU of the chip to be tested; SignatureEngine is the fingerprint engine of the chip to be tested; Interrupt Controller is the interrupt controller of the CPU; ATE functions refer to the functions stored in ROM for executing test commands; NV memories refer to some non-volatile memories inside the chip to be tested; Analog IPs refers to analog chips, MixSignal IPs refers to mixed signals; Test ID refers to The ID of the test command, Signature refers to the fingerprint information corresponding to the test command, and Results refers to the execution result corresponding to the test command. Pattern0 and Pattern1 refer to multiple sets of test commands written by the ATE machine to the ATE controller.

Taking Figure 2 as an example, the ATE Tester can write the test command into the ATE CTRL of the chip to be tested; the ATE CTRL can read the written test command and send the interrupt signal for the ATE test pattern structure containing the test command ID to each The interrupt controller Interrupt Controller of each CPU corresponding to the test command, and after the CPU reads the corresponding test command based on the interrupt signal received by the interrupt controller, releases the space occupied by the test command in the test command queue, so that ATE CTRL can continue to write Enter a new test command. Each CPU of the chip to be tested can read the test command written by the interrupt controller Interrupt Controller, and use the function ATE functions for executing the test command stored in the ROM to execute the test command. If the function executing the test command cannot call the test program in the ROM memory, the ATE Tester can write the test program to the ATE programs in the SRAM, and send a jump command to the CPU to make the CPU jump to the ATE programs in the SRAM, using The test program in the ATE programs in the SRAM executes the test command, and the CPU writes the execution result Results into the return result queue of ATE CTRL after executing the test command;

The fingerprint engine Signature Engine of the chip to be tested can obtain the access information of each CPU during the execution of the test command by each CPU, and generate the fingerprint information Signature corresponding to the test command according to the access information, and send the fingerprint information to the test command after the test command is executed Signature is written into the return result queue of ATE CTRL; the return result queue of ATE CTRL also includes the ID of each test command, that is, Test ID;

Then ATE CTRL can return the Test ID, fingerprint information Signature and execution result Results corresponding to the test command to ATE Tester for each test command, and then ATE Tester can read the Test ID, fingerprint information Signature and execution result corresponding to each test command Results, and determine the preset execution results and preset fingerprint information corresponding to each test command based on the Test ID, and compare the execution results and fingerprint information of each test command with the preset execution results and preset fingerprint information corresponding to each test command Comparison, if the execution result and fingerprint information of each test command are consistent with the preset execution result and preset fingerprint information corresponding to the test command, it is determined that the test result is that the test command passes the test; otherwise, it is determined that the test result is that the test command does not Passed the test.

In a possible implementation manner, FIG. 3 shows another schematic diagram of a chip testing system provided by an embodiment of the present disclosure. As shown in Figure 3, Results Fifo refers to the return result queue of the ATE controller, Test FIFO refers to the test command queue, and CPU0 to CPUn are the CPUs of the chip SoC to be tested. As shown in Figure 3, in this disclosure, ATE CTRL can send the test command queue to multiple CPUs, multiple CPUs can execute their corresponding test commands in parallel, and ATE CTRL can send the Test ID, fingerprint information Signature and execution of each CPU The information queue formed by Results constitutes the return result queue, which is returned to ATE Tester for ATE Tester to read and compare the results. The parallel execution of test commands by multiple CPUs can further improve test efficiency.

In a possible implementation manner, FIG. 4 shows another schematic diagram of a chip testing system provided by an embodiment of the present disclosure. As shown in Figure 4, for each test command, it is also possible to judge whether the test result is normal according to the execution time of the test command. If the execution time of the test command is within a reasonable time range, it is judged that the execution result of the test command is normal. When the test When the execution time of the command exceeds the reasonable time range, it is judged that the execution result of the test command is abnormal. If the test command does not return a test result for a long time, it can be judged that the test command timeout (timeout), indicating that the execution result of the test command is abnormal.

By adopting the chip test system provided by the embodiment of the present disclosure, multiple test commands can be executed in parallel on the SoC chip to realize pipeline operation, and the returned results corresponding to the test commands do not need to be consistent with the order of each test command in the test command queue, and can be out of order. Return, and then search for the corresponding preset execution result according to the ID of the test command and compare it with the preset fingerprint information, which greatly improves the test efficiency. Moreover, the chip testing system provided by the embodiments of the present disclosure can use multiple CPUs and hardware resources inside the chip to be tested for testing, without the need for an ATE machine to execute the test program, and the results returned each time are automatically generated by the fingerprint engine Yes, the ATE machine only needs to send a test command through the SoC ATE interface to read the test result, and then judge whether the test command is executed normally, which greatly reduces the amount of data transmitted between the ATE machine and the chip to be tested, thereby greatly improving The speed of the test improves the test efficiency, and also reduces the demand for ATE machines, thereby reducing the test cost.

Based on the same inventive concept, according to the chip testing system provided by the above-mentioned embodiments of the present disclosure, another embodiment of the present disclosure also provides a chip testing method applied to the chip testing system. 5 shows a schematic flow chart of a chip testing method applied to a chip provided by an embodiment of the present disclosure. The method is applied to a chip to be tested in a chip testing system, and the chip to be tested includes an ATE controller and at least one CPU. And fingerprint engine, as shown in Figure 5, described method comprises:

S501. The ATE controller reads test commands written by the ATE machine of the chip testing system, and sends a test command queue to a CPU corresponding to each test command.

In the present disclosure, the ATE machine can write multiple test commands into the pattern structure queue of the ATE controller, and the pattern structure queue after writing the multiple test commands can be used as a test command queue. The information contained in each test command queue includes but is not limited to: the ID of each test command, the ID of the CPU corresponding to each test command, the start address of each test command, the corresponding test data length of each test command, whether to dump (transfer storage) data, the start address of the test program corresponding to each test command, etc.

In the present disclosure, the test command queue may include multiple test commands, each test command corresponds to a CPU of the chip to be tested, and the CPU corresponding to each test command is the CPU for executing the test command. The test command includes not only the test command ID but also the ID of the CPU corresponding to the test command, and the ATE controller can send the test command to the CPU corresponding to the CPU ID according to the CPU ID contained in the test command, so that the CPU executes the test command . Before the ATE machine writes the test command into the ATE controller of the chip to be tested, it can assign the ID of the idle CPU to the test command, so that the ATE controller sends the test command to the idle CPU, and utilizes the idle CPU The CPU executes the test command to increase the utilization rate of the CPU when performing chip testing. Based on this, after the ATE controller reads the multiple test commands written by the ATE machine, it can send the test command queues respectively according to the ID of the CPU corresponding to each test command in the test command queue in the form of Give each test command the corresponding CPU.

In a possible implementation manner, the specific implementation of S501 may include the following steps A1-A2:

Step A1, read the test command written by the ATE machine, and send the interrupt signal for the test command queue to the interrupt controller of each CPU corresponding to each test command.

Step A2, after each CPU reads the test command corresponding to itself in the test command queue based on the interrupt signal received by the interrupt controller, release the space occupied by the test command in the test command queue, so that : The ATE machine detects whether there is freed space in the test command queue, and if so, writes a new test command to the ATE controller.

In the present disclosure, each test command occupies space in the test command queue. The internal command queue of the ATE controller of the chip to be tested can receive the test command written by the ATE machine. After the ATE controller reads the test command written by the ATE machine, it can send the test command queue to each test The interrupt controller of each CPU corresponding to the command. The CPU of the chip to be tested can read the corresponding test command from its own interrupt controller and execute the test command, and the process of the CPU executing the test command is the access sequence of the CPU to the chip to be tested.

After the CPU of the chip to be tested reads the corresponding test command from its own interrupt controller, the ATE controller can release the space of the test command queue occupied by the test command.

The ATE machine can detect whether there is freed space in the test command queue every preset time period, and if it detects that there is freed space in the test command queue, it can write a new test command to the ATE controller. Or, after the ATE controller can release the space of the test command queue occupied by the test command, the ATE controller can also send the information that there is free space in the test command queue to the ATE machine, and the ATE machine can After receiving the information of the free space, a new test command can be written to the ATE controller.

S502, each of the CPUs reads the test command corresponding to itself in the test command queue, executes the test command, and writes the execution result into the return of the ATE controller after executing the test command result queue.

In a possible implementation manner, the function for executing the test command in the chip to be tested is solidified in the ROM memory of the chip to be tested or the SRAM memory of the chip to be tested. The step of reading the test command corresponding to itself in the test command queue, executing the test command, and writing the execution result into the return result queue of the ATE controller after executing the test command, Specifically, the following steps B1-B3 may be included:

Step B1, read the test command corresponding to itself in the test command queue.

Each CPU of the chip to be tested can read the test command corresponding to itself in the test command queue.

Step B2, jumping to the target memory storing the test function according to the test command.

In the present disclosure, the ATE machine can download the test function for executing the test command into the SRAM or ROM inside the chip to be tested before the test starts. The parameter of the test command may be that the CPU points to the target memory storing the test function. If the target memory is the ROM memory of the chip to be tested, it means that the test function is stored in the ROM memory of the chip to be tested, then the parameter of the test command can point to the address of the test function in the ROM memory for the CPU, so that the CPU can use the test function in the ROM memory. Function executes described test command; If the target memory is the SRAM memory of the chip to be tested, it means that the test function is stored in the SRAM memory of the chip to be tested, then the parameter of the test command can point to the address of the test function in the SRAM memory for the CPU, so that The CPU executes the test command using the test function in the SRAM memory.

Step B3, using the test function in the target memory to execute the test command, and write the execution result into the return result queue of the ATE controller after the test command is executed.

After the CPU receives the test command, if the target memory is the ROM memory of the chip to be tested, it means that the test function is stored in the ROM memory of the chip to be tested, then the parameter of the test command can point to the address of the test function in the ROM memory for the CPU, and the CPU Can utilize the test function in the ROM memory to carry out described test command; If the target memory is the SRAM memory of the chip to be tested, it means that the test function is stored in the SRAM memory of the chip to be tested, then the parameter of the test command can point to the SRAM memory for the CPU The address of the test function, the CPU can use the test function in the SRAM memory to execute the test command. And write the execution result into the return result queue of the ATE controller after executing the test command.

S503, the fingerprint engine acquires the access information of each CPU during the execution of the test command by each CPU, and generates fingerprint information corresponding to the test command according to the access information, and executes the test command After the execution is completed, the fingerprint information is written into the return result queue of the ATE controller, so that the ATE machine performs the information comparison step.

Wherein, the step of comparing the execution information of the ATE machine includes: reading the execution results and fingerprint information corresponding to each test command in the return result queue of the ATE controller, and determining the preset execution corresponding to each test command based on the ID of the test command result and preset fingerprint information, and compare the execution result and fingerprint information of each test command with the preset execution result and preset fingerprint information corresponding to each test command, if the execution result and fingerprint information of each test command are respectively compared with the The preset execution result corresponding to the test command is consistent with the preset fingerprint information, and the test result is determined as the test command passed the test; otherwise, the test result is determined as the test command failed the test.

Wherein, the CPU access information includes CPU access address, access data and control signals.

The preset execution result is the theoretically corresponding execution result of the test command, and the preset fingerprint information is the fingerprint information that can be theoretically generated during the process of executing the test command.

The fingerprint engine is a fully automatic hardware unit in the chip to be tested. The fingerprint engine can continuously detect the access information of the CPU during the execution of the test command by the CPU, and generate corresponding fingerprints from the access information of the CPU each time it accesses the chip. information. Therefore, the fingerprint information corresponding to the test command generated by the fingerprint engine according to the access information of the CPU is actually a fingerprint information sequence, and the fingerprint information sequence includes the fingerprint information corresponding to the access information generated by the CPU after each access to the chip. After the fingerprint engine generates the fingerprint information, it can write the fingerprint information into the ATE controller. In the present disclosure, the fingerprint engine may use a fingerprint generation algorithm to generate corresponding fingerprint information using the access information. Specifically, the fingerprint generation algorithm may be a compression function algorithm, a hash algorithm, or a CRC32 (cyclic redundancy check) algorithm or the like. For example, the fingerprint engine can use the CRC32 algorithm to generate 32-bit fingerprint information through input data of any length.

Use the actual operation cycle coding CRC32 or hash algorithm, etc., and use the access information to generate the corresponding fingerprint information.

When the CPU finishes executing, the CPU can write the execution result, fingerprint information and test command ID of the test command to the ATE controller, and the ATE controller will return the execution result, fingerprint information and test command ID to the ATE machine. After receiving the information returned by the ATE controller, the ATE machine can read the fingerprint information, execution result and test command ID, and then according to the test command ID, the preset execution result corresponding to the test command ID and the returned execution result Compare, and compare the preset fingerprint information corresponding to the test command ID with the returned fingerprint information, if the execution result and fingerprint information of each test command for the chip are respectively the preset execution result and the preset execution result corresponding to the test command Assuming that the fingerprint information is consistent, it can be determined that the test command passes the test as a result of the test; otherwise, it is determined that the test command fails the test.

For a test command queue, this disclosure can judge whether the test command has passed the test by comparing the fingerprint information returned by the ATE controller to the ATE machine, because any execution error in the process of executing the test command by the CPU will cause the returned fingerprint information to be different from the expected one. Let the fingerprint information be different. Therefore, the ATE machine only needs to compare the execution result of the test command with the preset execution result, and compare the fingerprint information with the preset fingerprint information, and does not need to participate in the process of executing the test command by the CPU inside the chip.

And, in the present disclosure, since the execution result of each test command, the fingerprint information and the ID of the test command are also a queue, the order of the queue does not need to correspond to the order of each test command in the test command queue, and the ATE controller returns each The information queue formed by the execution result of each test command, the fingerprint information and the ID of the test command does not need to follow the order of each test command in the test command queue. For example, if the sequence of each test command in the test command queue is: test command D1, test command D2 and test command D3. When the CPU finishes executing the test command D2 first, and generates an information queue corresponding to the execution result of the test command D2, the fingerprint information, and the ID of the test command D2. Then the ATE controller may not follow the order of each test command in the test command queue, and first return the execution result of the test command D2, the fingerprint information and the information queue corresponding to the ID of the test command D2 to the ATE machine, and the ATE machine can return it according to the The ID of the test command D2 in the information queue directly searches for the preset execution result and preset fingerprint information corresponding to the test command D2, which is used for comparison with the returned execution result and fingerprint information of the test command D2.

With the chip testing method of the present disclosure, the ATE machine no longer needs to write test programs and read test data to the chip one by one, but only needs to send test commands to the chip to be tested, and then can use multiple CPUs in the chip to be tested to perform the test For each test command in the command queue, since the running speed of the CPU is much higher than the transmission speed of the ATE interface, using the CPU of the chip to be tested to execute the test program can increase the test speed exponentially, thereby reducing the test time and cost. . Moreover, the result of the chip to be tested returned to the ATE machine is automatically generated by the fingerprint engine of the chip to be tested, and the ATE machine does not need to spend extra time to read the results for comparison, that is, the ATE machine only needs to The ATE interface of the chip to be tested sends the test command and reads the test result to determine whether the test command passes the test, which greatly reduces the amount of data transmitted between the ATE machine and the ATE interface of the chip to be tested, thus greatly improving the test speed. The test time is further reduced and the test cost is reduced.

In a possible implementation manner, the fingerprint engine stores the fingerprint information corresponding to each key test node of each test command in the SRAM memory in the chip to be tested; so that: the ATE machine, in the existence test When the fingerprint information of the command is inconsistent with the preset fingerprint information corresponding to the test command, the fingerprint information corresponding to each key test node of the test command stored in the SRAM memory is called and compared with the preset fingerprint information to determine Unusual test node.

In this embodiment, when the ATE machine compares the execution result and fingerprint information of each test command with the preset execution result and preset fingerprint information corresponding to each test command, if there is an execution result of the test command and If the preset execution results are inconsistent, and/or, the fingerprint information of the test command is inconsistent with the preset fingerprint information, the ATE machine can locate the abnormal test node by debugging the execution result and/or fingerprint information. In order to locate abnormal test nodes through debugging, in this embodiment, the fingerprint engine may store fingerprint information corresponding to each key test node of each test command in the SRAM memory in the chip to be tested. Then the ATE machine can compare the fingerprint information corresponding to each key test node stored in the SRAM memory with the preset fingerprint information, so as to locate the abnormal test node.

When there is no hardware that can be used to store the fingerprint information corresponding to each key test node of each test command, the disclosure can also dump the fingerprint information corresponding to each key test node of each test command through the CPU. Results for fingerprint information will also vary.

In the present disclosure, since it takes time and storage space to open the information stored in the SRAM, the fingerprint engine stores the fingerprint information corresponding to each key test node of each test command in the SRAM in the chip to be tested After the memory, the ATE machine can choose whether to open the fingerprint information corresponding to each key test node of the test command stored in the SRAM memory according to the time and storage space.

In a possible implementation manner, the ATE controller can also, for each test command queue, determine whether all test commands in the test command queue return corresponding execution results within a preset time period, and if not, determine the The execution of the test command of the test command queue is abnormal.

Wherein, the preset time period is the theoretical time period for all test commands in the test command queue to be executed, and the preset time period can be set according to a specific test scenario, and is not specifically limited here.

In this disclosure, the ATE controller can send the test command queue to multiple CPUs, and the multiple CPUs can execute their corresponding test commands in parallel. The queue forms the return result queue, which is returned to the ATE machine for the ATE machine to read and compare the results.

That is to say, the chip testing method provided by the present disclosure supports the parallelism of multiple test commands of multiple CPUs, which improves the efficiency of chip testing.

By adopting the chip testing method provided by the embodiments of the present disclosure, multiple test commands can be executed in parallel on the chip to be tested to realize pipeline operation, and the returned results corresponding to the test commands do not need to be consistent with the order of each test command in the test command queue, and can be Return out of order, and then compare the corresponding preset execution result with the preset fingerprint information according to the ID of the test command, which greatly improves the test efficiency. Moreover, the chip testing system provided by the embodiments of the present disclosure can use multiple CPUs and hardware resources inside the chip to be tested for testing, without the need for an ATE machine to execute the test program, and the results returned each time are automatically generated by the fingerprint engine Yes, the ATE machine only needs to send a test command through the SoC ATE interface to read the test result to judge whether the test command is executed normally, which greatly reduces the amount of data transmitted between the ATE machine and the chip to be tested, thereby greatly improving The speed of the test improves the test efficiency, and also reduces the demand for ATE machines, thereby reducing the test cost.

Based on the same inventive concept, according to the chip testing system provided by the above-mentioned embodiments of the present disclosure, correspondingly, another embodiment of the present disclosure also provides a chip testing method applied to an ATE machine of the chip testing system. FIG. 6 shows a schematic flowchart of a chip testing method applied to an ATE machine provided by an embodiment of the present disclosure. As shown in FIG. 6, the method includes:

S601, write the test command into the ATE controller of the chip to be tested, so that: the ATE controller sends the test command queue to each CPU corresponding to each test command; each CPU of the chip to be tested reads the test command The test command corresponding to itself in the queue, and execute the test command, and write the execution result into the return result queue of the ATE controller after executing the test command; the fingerprint engine of the chip to be tested, in the Obtain the access information of each CPU during the execution of the test command by each CPU, generate fingerprint information corresponding to the test command according to the access information, and write the fingerprint information into the return result of the ATE controller queue.

Wherein, the test command queue includes a plurality of test commands, each test command corresponds to a CPU of the chip to be tested, and the CPU access information includes CPU access address, access data and control signals.

S602. Read the execution results and fingerprint information corresponding to each test command in the return result queue of the ATE controller.

S603, determine the preset execution result and preset fingerprint information corresponding to each test command based on the ID of the test command, and respectively associate the execution result and fingerprint information of each test command with the preset execution result and preset fingerprint information corresponding to each test command Compare.

S604, if the execution result and fingerprint information of each test command are consistent with the preset execution result and preset fingerprint information corresponding to the test command, determine that the test result is that the test command passes the test; otherwise, determine that the test result is that the test command does not Passed the test.

With the chip testing method of the present disclosure, the ATE machine no longer needs to write test programs and read test data to the chip one by one, but only needs to send test commands to the chip to be tested, and then can use multiple CPUs in the chip to be tested to perform the test For each test command in the command queue, since the running speed of the CPU is much higher than the transmission speed of the ATE interface, using the CPU of the chip to be tested to execute the test program can increase the test speed exponentially, thereby reducing the test time and cost. . Moreover, the result of the chip to be tested returned to the ATE machine is automatically generated by the fingerprint engine of the chip to be tested, and the ATE machine does not need to spend extra time to read the results for comparison, that is, the ATE machine only needs to The ATE interface of the chip to be tested sends the test command and reads the test result to determine whether the test command passes the test, which greatly reduces the amount of data transmitted between the ATE machine and the ATE interface of the chip to be tested, thus greatly improving the test speed. The test time is further reduced and the test cost is reduced.

According to the embodiments of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.

FIG. 7 shows a schematic block diagram of an example electronic device 700 that may be used to implement embodiments of the present disclosure. Electronic device is intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other suitable computers. Electronic devices may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are by way of example only, and are not intended to limit implementations of the disclosure described and/or claimed herein.

As shown in FIG. 7 , the device 700 includes a computing unit 701 that can execute according to a computer program stored in a read-only memory (ROM) 702 or loaded from a storage unit 708 into a random-access memory (RAM) 703 Various appropriate actions and treatments. In the RAM 703, various programs and data necessary for the operation of the device 700 can also be stored. The computing unit 701 , ROM 702 , and RAM 703 are connected to each other through a bus 704 . An input/output (I/O) interface 705 is also connected to the bus 704 .

Multiple components in the device 700 are connected to the I/O interface 705, including: an input unit 706, such as a keyboard, a mouse, etc.; an output unit 707, such as various types of displays, speakers, etc.; a storage unit 708, such as a magnetic disk, an optical disk, etc. ; and a communication unit 709, such as a network card, a modem, a wireless communication transceiver, and the like. The communication unit 709 allows the device 700 to exchange information/data with other devices over a computer network such as the Internet and/or various telecommunication networks.

The computing unit 701 may be various general-purpose and/or special-purpose processing components having processing and computing capabilities. Some examples of computing units 701 include, but are not limited to, central processing units (CPUs), graphics processing units (GPUs), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processing processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 701 executes various methods and processes described above, such as chip testing methods. For example, in some embodiments, the chip testing method may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as storage unit 708 . In some embodiments, part or all of the computer program may be loaded and/or installed on the device 700 via the ROM 702 and/or the communication unit 709 . When the computer program is loaded into the RAM 703 and executed by the computing unit 701, one or more steps of the chip testing method described above can be performed. Alternatively, in other embodiments, the computing unit 701 may be configured to execute a chip testing method in any other suitable manner (for example, by means of firmware).

Various implementations of the systems and techniques described above herein may be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip ( SoC), Complex Programmable Logic Device (CPLD), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include being implemented in one or more computer programs executable and/or interpreted on a programmable system including at least one programmable processor, the programmable processor Can be special-purpose or general-purpose programmable processor, can receive data and instruction from storage system, at least one input device, and at least one output device, and transmit data and instruction to this storage system, this at least one input device, and this at least one output device an output device.

Program codes for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special purpose computer, or other programmable data processing devices, so that the program codes, when executed by the processor or controller, make the functions/functions specified in the flow diagrams and/or block diagrams Action is implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media would include one or more wire-based electrical connections, portable computer disks, hard disks, Random Access Memory (RAM), Read Only Memory (ROM), Erasable Programmable Read Only Memory (EPROM or flash memory), fiber optics, compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

To provide for interaction with the user, the systems and techniques described herein can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user ); and a keyboard and pointing device (eg, a mouse or a trackball) through which the user can provide input to the computer. Other kinds of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and may be in any form (including Acoustic input, speech input, or, tactile input) to receive input from the user.

The systems and techniques described herein can be implemented on a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or web browser through which a user can interact with embodiments of the systems and techniques described herein), or including such backend components, middleware components, Or any combination of front-end components in a computing system. The components of the system can be interconnected by any form or medium of digital data communication (eg, a communication network). Examples of communication networks include: Local Area Networks (LANs), Wide Area Networks (WANs), and the Internet.

A computer system may include clients and servers. Clients and servers are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, a server of a distributed system, or a server combined with a blockchain.

It should be understood that steps may be reordered, added or deleted using the various forms of flow shown above. For example, each step described in the present disclosure may be executed in parallel, sequentially, or in a different order, as long as the desired result of the technical solution disclosed in the present disclosure can be achieved, no limitation is imposed herein.

In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In the description of the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

The above is only a specific implementation of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope of the present disclosure. should fall within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be determined by the protection scope of the claims.

Claims (14)

1. A chip test system, the system comprising:

the automatic test equipment ATE machine is used for writing a test command into an ATE controller of a chip to be tested;

the ATE controller is used for reading the test commands written by the ATE machine and sending the test command queues to the CPUs corresponding to the test commands; the test command queue comprises a plurality of test commands, and each test command corresponds to a CPU of a chip to be tested;

each CPU of the chip to be tested is used for reading the test command corresponding to the CPU in the test command queue, executing the test command and writing an execution result into a return result queue of the ATE controller after the test command is executed;

the fingerprint engine of the chip to be tested is used for acquiring access information of each CPU in the process of executing the test command by each CPU, generating fingerprint information corresponding to the test command according to the access information, and writing the fingerprint information into a return result queue of the ATE controller after the test command is executed; the access information of the CPU comprises an access address, access data and a control signal of the CPU;

the ATE machine is further configured to read an execution result and fingerprint information corresponding to each test command in a returned result queue of the ATE controller, determine a preset execution result and preset fingerprint information corresponding to each test command based on the ID of the test command, compare the execution result and the fingerprint information of each test command with the preset execution result and the preset fingerprint information corresponding to each test command, determine that the test result is that the test command passes the test if the execution result and the fingerprint information of each test command are consistent with the preset execution result and the preset fingerprint information corresponding to the test command, and determine that the test result is that the test command does not pass the test if the execution result and the fingerprint information of each test command are not consistent with the preset execution result and the preset fingerprint information corresponding to the test command.

2. The system according to claim 1, wherein the ATE controller is specifically configured to read a test command written by the ATE machine, send an interrupt signal for the test command queue to the interrupt controller of each CPU corresponding to each test command, and release a space occupied by the test command in the test command queue after each CPU reads the test command corresponding to itself in the test command queue based on the interrupt signal received by the interrupt controller;

and the ATE machine is also used for detecting whether the released space exists in the test command queue, and if so, writing a new test command into the ATE controller.

3. The system of claim 1, wherein the ATE bench is specifically configured to

And reading the state of a return result queue of the ATE controller, judging whether an operation result exists in the return result queue of the ATE controller, and if so, reading an execution result and fingerprint information corresponding to each test command in the return result queue of the ATE controller so as to enable the ATE controller to release the space occupied by the read execution result and fingerprint information in the return result queue of the ATE controller.

4. The system of claim 1, wherein the test function for executing the test command in the chip to be tested is fixed in the ROM memory of the chip to be tested or the SRAM memory of the chip to be tested;

each CPU is specifically configured to read a test command corresponding to the CPU in the test command queue, jump to a target memory in which the test function is stored according to the test command, execute the test command using the test function in the target memory, and write an execution result into a return result queue of the ATE controller after the test command is executed.

5. The system of claim 1, wherein the fingerprint engine of the chip to be tested is further configured to store fingerprint information corresponding to each key test node of each test command in an SRAM memory of the chip to be tested;

and the ATE machine is also used for calling the fingerprint information corresponding to each key test node of the test command stored in the SRAM memory to compare with the preset fingerprint information when the fingerprint information of the test command is inconsistent with the preset fingerprint information corresponding to the test command, so as to determine the abnormal test node.

6. The system of claim 1, wherein the ATE controller is further configured to determine, for each test command queue, whether all test commands in the test command queue return corresponding execution results within a preset time period, and if not, determine that the test command execution of the test command queue is abnormal.

7. A chip testing method is applied to a chip to be tested of a chip testing system, wherein the chip to be tested comprises an ATE controller, a plurality of CPUs and a fingerprint engine, and the method comprises the following steps:

the ATE controller reads the test commands written by the ATE machine of the chip test system and sends the test command queues to the CPUs corresponding to the test commands; the test command queue comprises a plurality of test commands, and each test command corresponds to a CPU of a chip to be tested;

each CPU reads the test command corresponding to the CPU in the test command queue, executes the test command, and writes an execution result into a return result queue of the ATE controller after the test command is executed;

the fingerprint engine acquires access information of each CPU in the process of executing the test command by each CPU, generates fingerprint information corresponding to the test command according to the access information, and writes the fingerprint information into a return result queue of the ATE controller after the test command is executed, so that the ATE machine station executes the following steps:

reading an execution result and fingerprint information corresponding to each test command in a returned result queue of the ATE, determining a preset execution result and preset fingerprint information corresponding to each test command based on the ID of the test command, comparing the execution result and the fingerprint information of each test command with the preset execution result and the preset fingerprint information corresponding to each test command respectively, and determining that the test result is that the test command passes the test if the execution result and the fingerprint information of each test command are consistent with the preset execution result and the preset fingerprint information corresponding to the test command respectively, or determining that the test result is that the test command does not pass the test; the access information of the CPU comprises an access address, access data and a control signal of the CPU.

8. The method of claim 7, wherein reading the test commands written by the ATE tool of the chip test system and sending a queue of test commands to the CPU corresponding to each test command comprises:

reading the test commands written by the ATE machine, and sending interrupt signals aiming at the test command queue to the interrupt controller of each CPU corresponding to each test command;

after each CPU reads the test command corresponding to itself in the test command queue based on the interrupt signal received by the interrupt controller, the space occupied by the test command in the test command queue is released, so that: and the ATE machine station detects whether the released space exists in the test command queue, and if so, writes a new test command into the ATE controller.

9. The method of claim 7, wherein the test function for executing the test command in the chip to be tested is fixed in the ROM memory of the chip to be tested or the SRAM memory of the chip to be tested;

the reading of the test command corresponding to the test command queue, the execution of the test command, and the writing of the execution result into the return result queue of the ATE controller after the execution of the test command include:

reading the test command corresponding to the test command queue;

jumping to a target memory storing the test function according to a test command;

and executing the test command by utilizing the test function in the target memory, and writing an execution result into a return result queue of the ATE controller after the test command is executed.

10. The method of claim 7, further comprising:

the fingerprint engine stores the fingerprint information corresponding to each key test node of each test command in an SRAM memory of the chip to be tested; so that: and when the fingerprint information of the test command is inconsistent with the preset fingerprint information corresponding to the test command, the ATE board calls the fingerprint information corresponding to each key test node of the test command stored in the SRAM memory to compare with the preset fingerprint information, and determines the abnormal test node.

11. The method of claim 7, further comprising:

and the ATE controller determines whether all the test commands in the test command queue return corresponding execution results within a preset time period or not for each test command queue, and if not, determines that the test commands in the test command queue are abnormally executed.

12. A chip testing method is applied to an ATE machine table of a chip testing system, and comprises the following steps:

writing a test command to an ATE controller of a chip to be tested such that: the ATE controller sends the test command queue to each CPU corresponding to each test command; each CPU of the chip to be tested reads the corresponding test command in the test command queue, executes the test command, and writes the execution result into a return result queue of the ATE controller after the test command is executed; the fingerprint engine of the chip to be tested acquires access information of each CPU in the process that each CPU executes the test command, generates fingerprint information corresponding to the test command according to the access information, and writes the fingerprint information into a return result queue of the ATE controller; the test command queue comprises a plurality of test commands, each test command corresponds to a CPU of a chip to be tested, and the access information of the CPU comprises the access address, the access data and the control signal of the CPU;

reading an execution result and fingerprint information corresponding to each test command in a return result queue of the ATE controller;

determining a preset execution result and preset fingerprint information corresponding to each test command based on the ID of the test command, and comparing the execution result and the fingerprint information of each test command with the preset execution result and the preset fingerprint information corresponding to each test command respectively;

and if the execution result and the fingerprint information of each test command are respectively consistent with the preset execution result and the preset fingerprint information corresponding to the test command, determining that the test result is that the test command passes the test, otherwise, determining that the test result is that the test command does not pass the test.

13. An electronic device, comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 7-11 or 12.

14. A non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method of any one of claims 7-11 or 12.

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