CN111049520A

CN111049520A - Digital-to-analog converter device and correction method

Info

Publication number: CN111049520A
Application number: CN201811184283.4A
Authority: CN
Inventors: 杨智杰; 黄诗雄; 雷良焕
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2018-10-11
Filing date: 2018-10-11
Publication date: 2020-04-21
Anticipated expiration: 2038-10-11
Also published as: CN111049520B

Abstract

The application discloses a digital-to-analog converter device and a correction method. The digital-to-analog converter device comprises a digital-to-analog converter circuit system and a correction circuit system. The digital-to-analog converter circuit system generates a first signal and a second signal according to an input signal. The correction circuitry compares the first signal and the second signal to generate a correction signal to correct the digital-to-analog converter circuitry based on the correction signal. The correction circuit system repeatedly compares the first signal and the second signal to generate a plurality of comparison results when determining at least one bit of a plurality of bits of the correction signal, and performs a statistical operation to adjust the at least one bit according to the comparison results, wherein the number of the at least one bit is less than that of the plurality of bits.

Description

Digital-to-analog converter device and correction method

Technical Field

The present application relates to digital-to-analog converter devices, and more particularly, to current-steering digital-to-analog converters using statistical operations.

Background

Digital-to-analog converters are commonly found in a variety of electronic devices. In the related art, as the number of bits to be processed increases, the number of circuits to be used increases, and the operation time required for the circuits also becomes significantly longer.

Disclosure of Invention

In order to solve the above problems, some embodiments of the present application provide a digital-to-analog converter (DAC) device including DAC circuitry and correction circuitry. The DAC circuitry generates a first signal based on a plurality of least significant bits of the input signal and generates a second signal based on a plurality of most significant bits of the input signal. The correction circuitry compares the first signal and the second signal to generate a correction signal to correct the DAC circuitry based on the correction signal. The correction circuit system repeatedly compares the first signal and the second signal to generate a plurality of comparison results when determining at least one bit of the plurality of bits, and performs a statistical operation to adjust at least one bit according to the plurality of comparison results, wherein the number of the at least one bit is less than the number of the plurality of bits.

Some embodiments of the present application provide a calibration method, comprising the operations of: generating a first signal according to a plurality of least significant bits of an input signal and generating a second signal according to a plurality of most significant bits of the input signal by using a DAC circuit system; comparing the first signal with the second signal to generate a correction signal to correct the DAC circuitry according to the correction signal; and when at least one bit of the plurality of bits of the correction signal is determined, repeatedly comparing the first signal with the second signal to generate a plurality of comparison results, and performing a statistical operation according to the plurality of comparison results to adjust the at least one bit, wherein the number of the at least one bit is less than the number of the plurality of bits.

In summary, the DAC apparatus and the calibration method provided by the present application may adjust part of the bits by using statistical operations. Therefore, the operation time of the correction process can be saved, and the correction accuracy is improved to improve the output resolution of the DAC device.

Drawings

Fig. 1 is a schematic diagram of a digital-to-analog converter (DAC) device according to some embodiments;

FIG. 2 illustrates a schematic diagram of an arrangement of current source circuits in the plurality of DAC circuits of FIG. 1, according to some embodiments;

FIG. 3 is a flow chart of a calibration method according to some embodiments;

FIG. 4 is a diagram illustrating an operation of FIG. 3 according to some embodiments;

FIG. 5 is a schematic diagram illustrating the execution of a majority operation according to some embodiments; and

fig. 6 is a schematic diagram illustrating performing a weight operation according to some embodiments.

Detailed Description

As used herein, the term "circuit system" generally refers to a single system comprising one or more circuits (circuits). The term "circuit" broadly refers to an object that is connected in some manner by one or more transistors and/or one or more active and passive components to process signals.

For ease of understanding, like elements in the various drawings will be designated with the same reference numerals.

Fig. 1 is a schematic diagram of a digital-to-analog converter (DAC) device 100 according to some embodiments.

The DAC device 100 includes multiplexer circuitry 110, DAC circuitry 120, and correction circuitry 130. The multiplexer circuitry 110 outputs one of the data signal DIN or the test signal DT as the input signal SIN according to the mode control signal CAL. For example, when the mode control signal CAL has a logic value of 0, the DAC apparatus 100 operates in the normal mode, and the multiplexer circuitry 110 outputs the data signal DIN as the input signal SIN. Alternatively, when the mode control signal CAL has a logic value of 1, the DAC apparatus 100 operates in the calibration mode, and the multiplexer circuitry 110 outputs the test signal DT as the input signal SIN.

The DAC circuitry 120 is coupled to the input circuitry 110 to receive an input signal SIN. The DAC circuit system 120 includes a plurality of

DAC circuits

121 and 122 and resistors RO 1-RO 2. The DAC circuit 121 generates a signal AO1 according to N Least Significant Bits (LSB) of the input signal SIN. DAC circuit 122 generates signal AO2 based on the M Most Significant Bits (MSBs) of input signal SIN.

In some embodiments, DAC circuitry 120 may be implemented by current-steering DAC circuitry. The current-steering DAC circuit may be implemented by a plurality of current source circuits, which are enabled according to the input signal SIN to output corresponding current signals as the signals AO1 or AO 2. The resistors RO1 to RO2 are respectively coupled to the output terminals OP and ON of the

DAC circuits

121 and 122 to convert the sum of the signals AO1 and AO2 into an analog output SOUT in the form of a voltage.

In some embodiments, the DAC device 100 further includes a plurality of switches SW 1-SW 2. The switches SW1 and SW2 are coupled to the plurality of outputs of the DAC circuit system 120 and the resistors RO 1-RO 2, respectively. When operating in the calibration mode, the switches SW 1-SW 2 are non-conductive in response to a mode control signal CAL', which is a complementary signal to the mode control signal CAL. Thus, in the calibration mode, the signals AO1 and AO2 can be correctly transmitted to the detection circuit 131. Alternatively, when operating in the normal mode, the switches SW 1-SW 2 are turned on in response to the mode control signal CAL'. Thus, in the normal mode, the signals AO 1-AO 2 can be transmitted to the resistors RO 1-RO 2.

In some embodiments, the calibration circuitry 130 is coupled to the DAC circuitry 120 and calibrates the DAC circuit 122 based on the signals AO1 and AO2 during the calibration mode. In some embodiments, the calibration circuitry 130 includes a detection circuit 131, a digital controller circuit 132, and a DAC circuit 133.

The detection circuit 131 is coupled to the output terminals OP and ON of the DAC circuits 121-122 for receiving the signals AO1 and AO 2. In some embodiments, the detecting circuit 131 is configured to compare the signal AO1 with the signal AO2 to generate the detecting signal SD. The detection signal SD is used to indicate the comparison result between the signal AO1 and the signal AO 2. In some embodiments, the detecting circuit 131 may be implemented by a current comparator, a quantizer, or the like, but the present application is not limited thereto.

The digital controller circuit 132 is coupled to the multiplexer circuit system 110 and the detection circuit 131. In some embodiments, the digital controller circuit 132 is provided with a memory (not shown) for storing a predetermined test signal DT (and/or a predetermined time value TH mentioned later) to provide the test signal DT to the multiplexer circuitry 110 in the operation mode. In some embodiments, the digital controller circuit 132 further performs a calibration operation in response to the detection signal SD to generate the calibration signal S1.

For example, the digital controller circuit 132 may perform a successive approximation method according to the detection signal SD to determine the bits B1 BN of the correction signal S1. In some embodiments, when determining the last K bits of the calibration signal S1, the digital controller circuit 132 further controls the detection circuit 131 to repeatedly compare the signals AO1 and AO2 to generate a plurality of comparison results, and perform a statistical operation to adjust the K bits according to the comparison results. In some embodiments, K is a positive non-zero integer. In some embodiments, the number of all bits of the correction signal S1 is N, and K is less than N.

In some embodiments, the digital controller circuit 132 may be implemented by, but is not limited to, a digital signal processing circuit, one or more logic circuits, and/or a processing circuit executing a finite state machine.

DAC circuit 133 is coupled to DAC circuit 122 and digital controller circuit 132. In some embodiments, the DAC circuit 133 outputs the compensation signal SP according to the correction signal S1 to correct the DAC circuit 122. For example, if the DAC circuit 122 is a current-steering DAC implemented by a plurality of unit current sources, the compensation signal SP can be directly input to the DAC circuit 122 to modify the bias voltages of the corresponding unit current sources. In this way, the signal AO2 output by the DAC circuit 122 can be equivalently corrected.

Alternatively, as shown in fig. 1, in some embodiments, the DAC circuit 133 is directly coupled to the output of the DAC circuit 122. In this configuration, the DAC circuit 133 may turn ON the corresponding current source circuit according to the correction signal S1 to generate the corresponding current signal (i.e., the compensation signal SP) to the output terminals OP and ON of the DAC circuit 122. In this way, the compensation signal SP can be directly added to the signal AO2 to equivalently correct the offset of the DAC circuit 122.

Fig. 2 is a schematic diagram illustrating an arrangement of the current source circuits in the

DAC circuits

121, 122 and 133 in fig. 1 according to an arrangement of some embodiments.

In some embodiments, the

DAC circuits

121, 122, and 133 may be implemented by current-steering DAC circuits. In this example, the plurality of current source circuits 121A are controlled by the plurality of bits L1 to L3 of the LSB, the plurality of current source circuits 122A are controlled by the plurality of bits M1 to M3 of the MSB, and the plurality of current source circuits 133A are controlled by the plurality of bits B1 to BN of the correction signal SP. In these embodiments, there is a corresponding relationship between the plurality of current source circuits 121A in the DAC circuit 121 and the plurality of current source circuits 122A in the DAC circuit 122.

For example, if the LSB is coded in binary code and the MSB is coded in thermal code, the currents (hereinafter referred to as current ILSB) of the current source circuits 121A sequentially differ by a factor of 2. For example, as shown in fig. 2, the current ILSB of the current source circuits 121A (e.g., the current sources 121A corresponding to the bits L1 to L3) sequentially differs by a factor of 2. As shown in fig. 2, the DAC circuit 133 includes a plurality of current source circuits 133A, whose currents are sequentially different by a factor of 2 (e.g., 1/2I, 1/4I, 1/8I, 1/16I, etc.). In some embodiments, the resolution of the DAC circuit 133 is higher than the resolution of the DAC circuit 122.

Ideally, the sum of the plurality of currents ILSB should be equal to the current of the single current source circuit 122A (hereinafter referred to as current IMSB). That is, Σ ILSB is IMSB (hereinafter referred to as formula 1). However, due to process variations, the current IMSB will be shifted, such that equation 1 cannot be satisfied. In some embodiments, the DAC circuit 121 further includes an additional current source circuit 121B, whose current is I and controlled by the bit L4, in which case, ideally, Σ ILSB is IMSB.

Accordingly, when operating in the calibration mode, the digital controller circuit 132 may output the test signal DT having a specific bit value. During the initial test, the low-weight bits (e.g., bits L1-L4 of LSB) of the test signal DT are all 1, and one of the high-weight bits (e.g., bits M1-M3 of MSB) of the test signal DT is 1. Under this condition, all the current source circuits 121A are turned ON to output the full current ILSB to an output terminal (e.g., the output terminal ON) as the signal AO 1. A corresponding current source circuit 122A is turned on to output a single current IMSB to another output terminal (e.g., the output terminal OP) as the signal AO 2. By this arrangement, the detection circuit 131 can compare the signal AO1 and the signal AO2 to determine whether both conform to formula 1. If the signal does not satisfy formula 1, the detection circuit 131 can output a corresponding detection signal SD.

Furthermore, the digital controller circuit 132 may perform a calibration operation (e.g., binary search or successive approximation) to determine the bits B1 BN of the calibration signal S1 in response to the detection signal SD. At least one current source circuit 133A is turned on according to the plurality of bits B1-BN to output a corresponding current as the compensation signal SP. In some embodiments, the compensation signal SP may be summed directly with the signal AO2 to equivalently calibrate the DAC circuit 122 (shown in FIG. 1). In other words, equation 1 can be modified to Σ ILSB — IMSB + SP (hereinafter equation 2). Thus, by performing one or more operations in sequence, the digital controller circuit 132 can determine the offset to be corrected by the single current source circuit 133A and record the corresponding correction signal S1 into the memory (not shown).

After recording the compensation signal SP corresponding to one current source circuit 122A, the digital controller circuit 132 may update the corresponding one of the MSBs of the test signal DT to 0 and update the next corresponding one of the MSBs of the test signal DT to 1, and perform the above operation again. In this way, the digital controller circuit 132 records the calibration signals S1 corresponding to all the current source circuits 122A by means of a look-up table or the like. As such, when the current source circuit 122A is activated, the digital controller circuit 132 may output the corresponding correction signal S1 to control the DAC circuit 133 to output the compensation signal SP to correct the DAC circuit 122.

For ease of understanding, the signals AO 1-AO 2 and the compensation signal SP in FIG. 1 are presented in a simplified manner. In practical applications, the signal AO1 may be a sum of a plurality of current (or voltage) signals (e.g., the current ILSB) outputted by the DAC circuit 121, the signal AO2 may be a sum of a plurality of current (or voltage) signals (e.g., the current IMSB) outputted by the DAC circuit 122, and the compensation signal SP may be a sum of a plurality of current signals outputted by the DAC circuit 133. With different signal types, the detection circuit 131 can also adopt different circuit configurations to determine whether the above equation 2 holds. For example, when the signals are all current signals, the detecting circuit 131 can be implemented by a current comparator and a switching circuit. The switching circuit can be used to adjust the transmission paths of the current signals corresponding to the signals AO 1-AO 2, so that the current comparator can obtain enough information to determine whether the expression 2 is satisfied.

Fig. 3 is a flow chart of a calibration method 300 according to some embodiments. In some embodiments, the calibration method 300 may be performed by the DAC device 100 in fig. 1.

In operation S310, the digital controller circuit 132 performs a calibration operation in response to the detection signal SD to determine the bits B1 BN of the calibration signal S1.

Fig. 4 is a diagram illustrating operation S310 in fig. 3 according to some embodiments. In this example, the digital controller circuit 132 performs a gradual approximation method according to the detection signal SD to determine the bits B1 BN of the correction signal S1. In the process of performing the successive approximation method, the digital controller circuit 132 enters a one-bit conversion stage. The bit transition stage includes a plurality of transition periods P1 PN. Each transition period P1 PN is used to determine a corresponding bit. For example, bit BN is determined during the transition period PN.

For easy understanding, in this example, N is set to 4, but the present application is not limited thereto. During the transition period P1, the detection circuit 131 compares the signals AO1 (corresponding to Σ ILSB) and AO2 (corresponding to IMSB + SP) for the 1 st time, and determines that Σ ILSB is smaller than IMSB + SP. The detection circuit 131 generates a corresponding detection signal SD to indicate the comparison result. The digital controller circuit 132 determines that the bit B1 of the correction signal S1 is 0 in response to the detection signal SD. Then, during the transition period P2, the detecting circuit 131 compares the signals AO1 and AO2 for the 2 nd time, and determines that Σ ILSB is greater than IMSB + SP. The digital controller circuit 132 determines that the bit B2 of the correction signal S1 is 1 in response to the comparison result. Similarly, during transition period P3, bit B3 is determined to be 0, and during transition period P4, bit B4 is determined to be 1.

With continued reference to fig. 3, in operation S320, the digital controller circuit 132 performs a statistical operation to adjust the K-bit reciprocal of the correction signal S1 in response to the comparison results represented by the detection signal SD.

In operation S330, the DAC circuit 133 generates the compensation signal SP to correct the DAC circuit 122 in response to the correction signal S1.

As previously described, K is less than N. For easy understanding, the following paragraphs illustrate the case where K is 1, but the present application is not limited thereto. For the last 1 bit B4, the digital controller circuit 132 can control the detection circuit 131 to repeatedly compare the signal AO1 and the signal AO2 to generate the multiple detection signal SD. Based on the comparison results respectively represented by the detection signals SD, the digital controller circuit 132 may perform a statistical operation to adjust the last 1 bit B4. In some embodiments, the statistical operation may be a majority operation. Alternatively, in some embodiments, the statistical operation may be a weighting operation.

FIG. 5 is a block diagram illustrating a method for performing a majority operation according to some embodiments. As shown in fig. 5, in the transition period P4 of the decision bit B4, the detection circuit 131 compares the 5 sub-signals AO1 and AO2 to sequentially generate 5 detection signals SD. In response to the 5 detection signals SD, the digital controller circuit 132 determines the bits B4 to be 1, 0 in sequence according to the calibration operation. In this case, the digital controller circuit 132 determines the bit B4 to be 1 according to the majority operation due to the larger number of 1. Conversely, if the determined bit B4 is 0, 1, 0 in order. In this case, since the number of 0 is large, the bit B4 is determined to be 0.

Fig. 6 is a schematic diagram illustrating performing a weight operation according to some embodiments. As shown in fig. 6, in the transition period P4 of the decision bit B4, the detection circuit 131 compares the 5 sub-signals AO1 and AO2 to sequentially generate 5 detection signals SD.

If all of the 5 detection signals SD are 1, the digital controller circuit 132 encodes the bit B4 as 2. If there are 4 1 s and 10 s in the 5 detection signals SD, the digital controller circuit 132 encodes the bit B4 as 1. If there are 31 s and 20 s in the 5 detection signals SD, the digital controller circuit 132 encodes the bit B4 as 0.5. If there are 21 s and 30 s in the 5 detection signals SD, the digital controller circuit 132 encodes the bit B4 as 0.25. If there are 1 and 4 0 in the 5 detection signals SD, the digital controller circuit 132 encodes the bit B4 as 0. If there are 5 0's in the 5 detection signals SD, the digital controller circuit 132 encodes the bit B4 as-1.

In this example, different codes correspond to different levels. In some embodiments, the DAC circuit 133 comprises more current source circuits for generating different levels corresponding to different codes, for example, the DAC circuit 133 further comprises a first current source circuit with a current of (1/16) I, when the bit B4 is coded as 2, two current source circuits (the original current source circuit and the first current source circuit) with a current of (1/16) I will be turned on simultaneously, and the current source circuit 122A corresponding to the MSB is connected to the same output terminal; when bit B4 encodes a-1, the first current source circuit will be on, but the current source circuit 122A corresponding to the MSB is connected to a different output; in another example, the DAC circuit 133 further includes a current source circuit having a current of (1/32) I, and when the bit B4 is encoded to 0.5, the current source circuit having a current of (1/32) I will be turned on and the current source circuit 122A corresponding to the MSB is connected to the same output terminal.

Compared to fig. 5, the bit B4 can be encoded into a multi-level (multi-level) digital code according to the multiple comparison results. In this manner, the DAC circuit 133 may generate a more accurate compensation signal SP to correct the DAC circuit 122.

In some related art techniques, to improve the accuracy of the correction, the N bits (e.g., B1-BN) of the correction signal are set to be determined by averaging the sets of digital codes generated by the multiple bit transition stages. For example, if the correction signal has 4 bits, in these techniques, 1024 bit conversion stages are required to obtain 1024 sets of digital codes (e.g., B1-B4), and then the 1024 sets of digital codes are averaged to determine the 4 bits of the correction signal. Thus, the entire calibration process takes at least 1024 × 4 switching cycles.

In contrast to the above-described technique, the digital controller circuit 132 only repeats the comparison when determining the last K bits of the correction signal. Thus, the time consumed by the correction process can be reduced. In addition, since the analog signal (i.e., the input of the detection circuit 131) corresponding to the last K bits is relatively small, the comparison result of the detection circuit 131 is more susceptible to noise and errors. By adjusting the last K bits according to the statistical operation of the multiple comparison results, the error probability of the detection circuit 131 can be effectively reduced, thereby improving the accuracy of the correction. In some embodiments, the higher the number of comparison operations performed by the detection circuit 131 during the transition period for determining the last K bits, the higher the accuracy of the calibration. In some embodiments, the number of comparison operations performed by the detection circuit 131 may be preset according to actual requirements (calibration time, accuracy, etc.).

In some embodiments, the value of K may be preset. In other words, when the transition period for determining K bits is entered, the digital controller circuit 132 starts to perform operation S320.

Alternatively, in other embodiments, the digital controller circuit 132 may determine whether the operation S320 needs to be performed according to the transition time of the detection signal SD (i.e., the time for switching from logic 1 to logic 0, or the time for switching from logic 0 to logic 1). As mentioned above, the analog signal (i.e. the input of the detection circuit 131) corresponding to the last K bits is relatively small, and the detection circuit 131 may require a long operation time to generate the detection signal SD. Equivalently, the transition time of the detection signal SD may be longer when determining the last K bits. In some embodiments, as shown in fig. 1, the digital controller circuit 132 can compare the transition time of the detection signal SD with a predetermined time value TH. During the determination of one of the bits B1-BN, if the transition time of the detection signal SD is longer than the predetermined time value TH, the digital controller circuit 132 may determine that a plurality of comparisons are required to perform a statistical operation to adjust the corresponding bit in the correction signal S1. In some embodiments, the predetermined time value TH may be set according to a transition time of the detection signal SD to the current ILSB (e.g., the current I), and may be adjusted according to practical applications.

The above embodiments are provided for illustrative purposes, and various modifications and alterations can be made without departing from the spirit and scope of the present application, and the scope of the present application is defined by the appended claims.

Description of the symbols

100: digital-to-analog converter device

120: digital-to-analog converter circuitry

DT: test signal

SIN: input signal

AO1, AO 2: signal

MSB: most significant bit

RO1, RO 2: resistance (RC)

132: digital controller circuit

SD: detecting signal

S1: correcting signal

B1-BN: bit

TH: predetermined time value

133A: current source circuit

I: specific current

S310, S320, S330: operation of

L1-L4: bit 110: multiplexer circuit system

130: correction circuit system

DIN: data signal

CAL, CAL': mode control signal

121-122: digital-to-analog converter circuit

133: digital-to-analog converter circuit

LSB: least significant bit

And (3) SOUT: analog output

OP, ON: output end

131: detection circuit

SP: compensating signal

SW1, SW 2: switch with a switch body

121A, 122A: current source circuit

ILSB, IMSB: electric current

300: correction method

P1-P4: during the transition

M1-M3: bit

Claims

1. A digital to analog converter apparatus, comprising:

a digital-to-analog converter circuit system for generating a first signal according to a plurality of least significant bits of an input signal and generating a second signal according to a plurality of most significant bits of the input signal; and

a calibration circuit system for comparing the first signal and the second signal to generate a calibration signal to calibrate the DAC circuit system according to the calibration signal,

the correction circuit system is further configured to repeatedly compare the first signal and the second signal to generate a plurality of comparison results when determining at least one of the plurality of bits, and perform a statistical operation to adjust the at least one bit according to the plurality of comparison results, wherein the number of the at least one bit is less than the number of the plurality of bits.

2. The digital-to-analog converter device of claim 1, wherein the at least one bit is a last bit of the plurality of bits.

3. The digital-to-analog converter device of claim 1, wherein the at least one bit comprises a last K bits of the plurality of bits, K being a positive non-zero integer.

4. The digital-to-analog converter device of claim 1, wherein the correction circuitry comprises:

a detection circuit for comparing the first signal with the second signal to generate a detection signal indicating the comparison results;

a digital controller circuit configured to perform a calibration operation according to the detection signal to generate the calibration signal, wherein when the at least one bit is determined, the digital controller circuit is further configured to perform the statistical operation according to the detection signal to adjust the at least one bit; and a digital-to-analog converter circuit for generating a compensation signal according to the plurality of bits of the correction signal to correct the digital-to-analog converter circuit system.

5. The DAC device of claim 4, wherein the statistical operation is a majority operation, and the digital controller circuit performs the majority operation to adjust the at least one bit according to the comparison results indicated by the detection signal.

6. The DAC device of claim 4, wherein the statistical operation is a weighting operation, and the digital controller circuit performs the weighting operation to adjust the at least one bit according to the comparison results indicated by the detection signal.

7. The digital-to-analog converter device of claim 6, wherein the at least one bit is encoded as a digital code having multiple levels.

8. The DAC device of claim 4, wherein the digital controller circuit is further configured to compare a transition time of the detection signal with a predetermined time value to determine whether to perform the statistical operation.

9. The digital-to-analog converter arrangement of claim 1, wherein the digital-to-analog converter circuitry comprises:

a first digital-to-analog converter circuit for generating the first signal according to the least significant bits; and

a second digital-to-analog converter circuit for generating the second signal according to the most significant bits,

wherein each of the first digital-to-analog converter circuit and the second digital-to-analog converter circuit is implemented by a current-steering digital-to-analog converter circuit.

10. A calibration method for a digital-to-analog converter circuit system, the calibration method comprising:

generating a first signal according to a plurality of least significant bits of an input signal and generating a second signal according to a plurality of most significant bits of the input signal by the digital-to-analog converter circuit system;

comparing the first signal with the second signal to generate a correction signal, so as to correct the digital-to-analog converter circuit system according to the correction signal; and

when at least one bit of the plurality of bits of the correction signal is determined, the first signal and the second signal are repeatedly compared to generate a plurality of comparison results, and a statistical operation is performed according to the plurality of comparison results to adjust the at least one bit, wherein the number of the at least one bit is less than the number of the plurality of bits.