CN110379390A - A display panel, its driving method and display device - Google Patents

Abstract

The invention discloses a display panel, a driving method thereof and a display device, and relates to the technical field of display. In the embodiment of the present invention, each gate line group sequentially inputs a gate-on signal, each gate line in the gate line group sequentially inputs a gate-on signal, and the data line may input a data signal of the same polarity to each sub-pixel electrically connected to the data line and electrically connected to each gate line in the same gate line group, where the sub-pixel has the same color. Therefore, the sub-pixels which are electrically connected with the same data line and are electrically connected with the grid lines in the same grid line group and have the same color are enabled to sequentially input the data signals with the same polarity, so that the polarity switching times of the data signals are reduced to the maximum extent, the power consumption of the display panel is reduced, the power consumption of the display device is reduced, and the service life of the display device is prolonged.

Description

A display panel, its driving method and display device

technical field

The invention relates to the field of display technology, in particular to a display panel, a driving method thereof and a display device.

Background technique

A liquid crystal display is a non-self-luminous device, which requires a backlight module, and uses the backlight provided by the backlight module to realize the display function.

In order to increase the screen-to-body ratio of the display, the display panel can be designed as a double-gate structure, as shown in FIG. 1 , a schematic structural diagram of the display panel, wherein each data line 10 can be electrically connected to two adjacent columns of sub-pixels on the left and right, and, Through the control of each shift register, each gate line is sequentially input with a gate turn-on signal. In addition, referring to the timing diagram shown in Figure 2, the diagram shows the timing of the data signal input from the data line marked as S1 to the correspondingly connected sub-pixels P when the red screen is displayed. When the gate turn-on signal is input sequentially, the data signal transmitted on the data line S1 needs to be switched continuously, so that the number of switching times of the data signal is large, resulting in increased power consumption of the display panel.

Then, how to reduce the power consumption of the display panel with the double gate structure is a technical problem to be solved urgently in the embodiments of the present invention.

Contents of the invention

Embodiments of the present invention provide a display panel, a driving method thereof and a display device for reducing power consumption of a display panel with a double gate structure.

In a first aspect, an embodiment of the present invention provides a method for driving a display panel, where the display panel includes:

Pixels arranged in an array, the pixels include at least three sub-pixels with different colors, each column of sub-pixels is composed of sub-pixels with the same color, and any two adjacent sub-pixels in the row direction and column direction are input The polarity of the data signal is reversed;

A plurality of data lines arranged in the row direction and extending in the column direction, two columns of sub-pixels are arranged between any two adjacent data lines, and each of the data lines is electrically connected to multiple columns of sub-pixels;

A plurality of gate lines arranged along the column direction and extending along the row direction, two gate lines are arranged between any two adjacent rows of sub-pixels, the side of the first row of sub-pixels away from the last row of sub-pixels, and one gate line is provided on the side of the last row of sub-pixels away from the first row of sub-pixels; all the gate lines are divided into multiple gate line groups, and the gate line groups include multiple grid lines line, at least one row of sub-pixels is arranged between the sub-pixels electrically connected to any two adjacent gate lines in the group of gate lines;

The driving method includes:

Each of the gate line groups is sequentially input with a gate open signal, each of the gate lines in the gate line group is sequentially input with a gate open signal, and the data line is electrically connected to itself and connected to the same gate line group. Each of the sub-pixels with the same color electrically connected to each of the gate lines receives a data signal of the same polarity.

In a second aspect, an embodiment of the present invention provides a display device, including a display panel;

The display panel is driven by the above-mentioned driving method provided by the embodiment of the present invention.

In a third aspect, an embodiment of the present invention provides a display panel, including:

Pixels arranged in an array, the pixels include at least three sub-pixels with different colors, each column of sub-pixels is composed of sub-pixels with the same color, and any two adjacent sub-pixels in the row direction and column direction are input The polarity of the data signal is reversed;

A plurality of data lines arranged in the row direction and extending in the column direction, two columns of sub-pixels are arranged between any two adjacent data lines, and each of the data lines is electrically connected to multiple columns of sub-pixels;

a plurality of shift register groups, each of which includes a plurality of cascaded shift registers;

A clock signal line group electrically connected to the shift register group, the clock signal line is used to provide a clock signal for the correspondingly electrically connected shift register;

A plurality of gate lines arranged along the column direction and extending along the row direction, two gate lines are arranged between any two adjacent rows of sub-pixels, the side of the first row of sub-pixels away from the last row of sub-pixels, and one gate line is provided on the side of the last row of sub-pixels away from the first row of sub-pixels; all the gate lines are divided into multiple gate line groups, and the gate line groups include multiple grid lines line, at least one row of sub-pixels is arranged between the sub-pixels electrically connected to any two adjacent gate lines in the group of gate lines;

Wherein, each of the gate lines is electrically connected to one of the shift registers, and each of the gate lines in the gate line group corresponds to the shift registers at the same level in different shift register groups electrical connection;

Each of the gate line groups is sequentially input with a gate open signal, and each of the gate lines in the gate line group is sequentially input with a gate open signal, so that the gate line electrically connected to the same data line and connected to the same gate Each of the sub-pixels electrically connected to each of the gate lines in the line group has the same color and inputs data signals of the same polarity.

The beneficial effects of the present invention are as follows:

The embodiments of the present invention provide a display panel, its driving method, and a display device. By dividing all the gate lines into multiple gate line groups, the gate line group includes a plurality of gate lines, and any two adjacent gate line groups At least one row of sub-pixels is arranged between the sub-pixels electrically connected by the gate lines. During the driving process of the display panel, gate-on signals are sequentially input to each gate-line group, and each gate-line group in the gate-line group is sequentially input to the gate When the signal is turned on, the data line can input a data signal of the same polarity to each sub-pixel with the same color that is electrically connected to itself and to each gate line in the same gate line group. In this way, the sub-pixels with the same color that are electrically connected to the same data line and to the gate lines in the same gate line group are sequentially input with data signals of the same polarity, thereby minimizing the polarity of the data signals. The number of switching times, thereby reducing the power consumption of the display panel, reducing the power consumption of the display device, and prolonging the use time of the display device.

Description of drawings

FIG. 1 is a schematic structural diagram of a display panel in the prior art;

Figure 2 is a timing diagram corresponding to Figure 1;

FIG. 3 is a schematic structural diagram of a first display panel provided in an embodiment of the present invention;

Fig. 4 is a sequence diagram corresponding to Fig. 3;

FIG. 5 is a schematic structural diagram of a second display panel provided in an embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a third display panel provided in an embodiment of the present invention;

Fig. 7 is a sequence diagram corresponding to Fig. 5 and Fig. 6;

FIG. 8 is a schematic diagram of a cascade relationship between shift registers provided in an embodiment of the present invention;

FIG. 9 is a schematic structural diagram of a display device provided in an embodiment of the present invention.

Among them, 10, D1, D2, D3, D4-data line, 20, G1, G2, G3, G4, G5, G6, G7, G8, G9, G10, G11, G12, G13, G14, G15, G16- grid Line, P0-pixel, P-sub-pixel, 40-touch signal line, A1-display area, A2-non-display area, Z1, Z2-sub-area, X-display panel.

Detailed ways

Specific implementations of a display panel, a driving method thereof, and a display device provided by embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the described embodiments are only some of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The inventor found in research that, taking the structure of the display panel shown in Figure 1 as an example, the display panel includes sub-pixels, gate lines, and data lines arranged in an array, wherein any two adjacent rows of sub-pixels are arranged There are two gate lines, one gate line is set on the side of the first row of sub-pixels away from the last row of sub-pixels, and the side of the last row of sub-pixels away from the first row of sub-pixels, and two adjacent data lines are set The columns of sub-pixels are electrically connected to the two columns of sub-pixels respectively.

Referring to FIG. 1, the display panel further includes: a shift register corresponding to each gate line, a first clock signal line CK and a second clock signal line CKB electrically connected to each shift register, and a first clock signal line connected to the first clock signal line. The initial signal line electrically connected to the stage shift register, wherein, each shift register is cascaded, the first clock signal line CK can provide the first clock signal for each shift register, and the second clock signal line CKB can provide each shift register The shift register provides the second clock signal, and the start signal line can provide the start signal for the first-stage shift register.

The timing diagram corresponding to the structure shown in Figure 1 is shown in Figure 2. Figure 2 shows the time for each gate to input the gate-on signal, after the start signal is input, and the first clock signal line CK outputs When the first clock signal is used, the first-stage shift register inputs a gate open signal to the correspondingly connected gate line, and at the same time inputs the gate open signal to the signal input end of the second-stage shift register as a second-stage shift register start signal.

When the second clock signal line provides the second clock signal, the second-stage shift register inputs the gate open signal to the correspondingly connected gate line, and at the same time, on the one hand, the second-stage shift register outputs the gate open signal to The reset signal terminal of the first-stage shift register enables the first-stage shift register to reset and stop outputting the gate open signal to the correspondingly connected gate line, and on the other hand, the second-stage shift register outputs the gate open signal The signal input terminal to the third-stage shift register serves as the start signal of the third-stage shift register.

Similarly, the working process of the third-stage shift register to the penultimate stage shift register is similar to the above, and the repetition will not be repeated.

Only for the last stage shift register, it is only necessary to input the gate open signal to the correspondingly connected gate line, and output the gate open signal to the reset signal terminal of the upper stage shift register, so that the upper stage shift register The bit register is reset to stop outputting the gate-on signal to the correspondingly connected gate line.

That is to say, as the first clock signal periodically outputs the first clock signal, and the second clock signal periodically outputs the second clock signal, the shift registers of each stage successively output gate open signals to correspondingly connected gate lines , so that each grid line is scanned sequentially.

Correspondingly, for the data lines, taking the data line marked as S1 in FIG. When scanned sequentially, the polarity of the data signal needs to be switched continuously. As shown in the timing sequence of the data line S1 in Figure 2, the position corresponding to R in the figure indicates the data signal input to the red sub-pixel R, and the position corresponding to G indicates the data signal input to the green sub-pixel G, where in Figure 2 Given is the timing when a red picture is displayed, because the red picture is displayed, only the data signal is input to the red sub-pixel R, and no data signal is input to the sub-pixels of other colors.

Referring to FIG. 2, the data signal transmitted on the data line S1 needs to be continuously switched between high-level signal, low-level signal, and zero potential to ensure that only the data signal is input to the red sub-pixel R, and It is ensured that the polarities of the data signals input by the two red sub-pixels R adjacent to each other are opposite in polarity. In this way, the number of switching times of the data signal is increased, resulting in a large power consumption of the display panel.

In order to solve this problem, an embodiment of the present invention provides a display panel for reducing power consumption of a display panel with a double gate structure.

Specifically, an embodiment of the present invention provides a driving method of a display panel, wherein, before introducing the driving method, the structure of the display panel is firstly introduced, as shown in FIG. 3 , FIG. 5 and FIG. 6 , wherein FIG. 3 is A schematic structural diagram of the first type of display panel, FIG. 5 is a schematic structural diagram of the second type of display panel, and FIG. 6 is a schematic structural diagram of the third type of display panel.

Referring to Fig. 3, Fig. 5 and Fig. 6, the display panel may include:

Pixel P0 arranged in an array, pixel P0 includes at least three sub-pixels P with different colors, each column of sub-pixels is composed of sub-pixels P with the same color, and any two adjacent sub-pixels P in the row direction and column direction are input The polarity of the data signal is reversed;

A plurality of data lines 10 arranged in the row direction and extending in the column direction, two columns of sub-pixels are arranged between any two adjacent data lines 10, and each data line 10 is electrically connected to multiple columns of sub-pixels; for example, as shown in FIG. 3 As shown, each data line 10 is electrically connected to two columns of sub-pixels, and for another example, as shown in FIGS. 5 and 6 , each data line 10 is electrically connected to four columns of sub-pixels.

A plurality of gate lines arranged in the column direction and extending in the row direction (such as G1 to G8 in Figure 3, and 20 or G1 to G16 in Figure 5 and Figure 6), between any two adjacent rows of sub-pixels There are two gate lines, one gate line is provided on the side of the first row of sub-pixels away from the last row of sub-pixels, and the side of the last row of sub-pixels away from the first row of sub-pixels; all the gate lines are divided into multiple A grid line group (the grid lines electrically connected to the sub-pixels with the same filling pattern are a grid line group, and the mark of the grid line group is not given in the figure), the grid line group includes multiple grid lines, and any adjacent grid line group At least one row of sub-pixels is arranged between the sub-pixels electrically connected by two gate lines;

For example, as shown in FIG. 3, the gate line group may include two gate lines, wherein the gate lines in FIG. The two columns of sub-pixels electrically connected by the data line of D1 are taken as an example. The gate lines electrically connected to the sub-pixels filled with sparse black dots are marked as G1 and G5, so the gate line G1 and the gate line G5 can be regarded as a gate line group; The grid lines electrically connected to the sub-pixels with a grid pattern are marked as G3 and G7, so the grid lines G3 and G7 can be regarded as a grid line group; the grid lines electrically connected to the sub-pixels filled with horizontal lines are marked as G4 and G7. G8, so the gate line G4 and the gate line G8 can be regarded as a gate line group; the gate lines electrically connected to the sub-pixels filled with vertical lines are marked as G2 and G6, so the gate line G2 and the gate line G6 can be regarded as a gate line Group.

Among them, the first row of sub-pixels and the last row of sub-pixels can be understood as:

Taking the structure shown in FIG. 3 as an example, the first row of subpixels can be understood as the row of subpixels farthest from the driving IC, and the last row of subpixels can be understood as the row of subpixels closest to the driving IC.

Of course, the driver IC is not limited to setting the position of the lower frame of the display panel in Figure 3, but also the position of the upper frame of the display panel (not shown). At this time, the first row of sub-images can be understood as distance driving The sub-pixel row closest to the IC, and the last row of sub-pixels can be understood as the sub-pixel row farthest from the driving IC. However, regardless of whether the driver IC is disposed on the upper frame or the lower frame, the sub-pixels in the first row and the sub-pixels in the last row are respectively sub-pixel rows arranged on two opposite edges of the display area along the column direction.

For another example, as shown in FIG. 5, the gate line group may include four gate lines, wherein the gate lines in FIG. Taking the two columns of sub-pixels electrically connected to the data line of D2 as an example, the gate lines electrically connected to the sub-pixels filled with sparse black dots are marked as G1, G5, G9 and G13, so the gate lines G1, G5, G13 can be The line G9 and the gate line G13 are used as a gate line group; the grid lines that are electrically connected to the sub-pixels filled with the grid pattern are marked as G3, G7, G11 and G15, so the gate line G3, the gate line G7, the gate line G11 and the The gate line G15 serves as a gate line group; the gate lines electrically connected to the sub-pixels filled with horizontal lines are marked as G4, G8, G12 and G16, so the gate line G4, the gate line G8, the gate line G12 and the gate line G16 can be used as A grid line group; the grid lines electrically connected to the sub-pixels filled with vertical lines are marked as G2, G6, G10, and G14, so the grid lines G2, G6, G10, and G14 can be regarded as a grid line group .

Of course, the above is just an example to illustrate how many grid lines a grid line group can include, and which grid lines are included in a grid line group, but the specific implementation is not limited to the above-mentioned Figure 3 and Figure 5, and other division methods are also possible. As long as the driving method to be introduced below can be realized, it is not limited here.

At this point, referring to the timing diagrams shown in FIGS. 4 and 7 , wherein FIG. 4 is a timing diagram corresponding to FIG. 3 , and FIG. 7 is a timing diagram corresponding to FIGS. 5 and 6 , the driving method may include:

Each gate line group inputs the gate opening signal sequentially, and each gate line in the gate line group sequentially inputs the gate opening signal, and the data lines have the same color as those electrically connected to themselves and to each gate line in the same gate line group. The data signals of the same polarity are input to each sub-pixel.

In the embodiment of the present invention, by improving the driving method, each gate line group is sequentially input with a gate open signal, and each gate line in the gate line group is sequentially input with a gate open signal, so that when each gate line is scanned , the grid lines are not sequentially input with the gate open signal from top to bottom or from bottom to top as in the prior art, but according to the division of the gate line groups, each gate line is sequentially input with the gate open signal, thus The raster line scanning mode in the prior art can be broken.

Moreover, after breaking the grid line scanning method in the prior art, the data line can input data of the same polarity to each sub-pixel with the same color that is electrically connected to itself and to each grid line in the same grid line group. The signal, especially when displaying a monochrome picture, makes the data signal input by the data line to the sub-pixel of the same color electrically connected to the gate line in each gate line group do not need to be switched, and the data signal can be kept unchanged. Moreover, the more gate lines are included in the gate line group, the longer the data signal remains unchanged, so that the switching times of the data signal can be effectively reduced, thereby reducing the power consumption of the display panel.

Specifically, as shown in Table 1 below, Table 1 shows the data signals transmitted on the three data lines marked as D2, D3 and D4 in Figure 5, and G1-G16 represent the top-to-bottom lines in Figure 5 16 grid lines, wherein, if G1, G5, G9 and G13 are considered as the first grid line group, G3, G7, G11 and G15 are regarded as the second grid line group, and G2, G6, G10 and G14 is regarded as the third gate line group, and G4, G8, G12 and G16 are regarded as the fourth gate line group, then these four gate line groups input the gate opening signal in turn, and the four gate line groups in each gate line group The gate lines are sequentially input with a gate turn-on signal.

As shown in Table 1, if the three data lines need to input data signals to the correspondingly connected red sub-pixel R when displaying a red picture, it can be seen that in each gate line group, the data signals transmitted on each data line are Data signals of the same polarity. At the same time, when the two continuously driven gate line groups are scanned, the data signals transmitted on the data lines are all of the same polarity (as shown by the bold B+ in Table 1), In this way, the switching times of the data signal can be greatly reduced, thereby greatly reducing the power consumption of the display panel, further reducing the power consumption of the display device, and prolonging the use time of the display device.

Table 1

In specific implementation, in the embodiment of the present invention, the number of sub-pixel columns electrically connected to the data line can be set as:

Referring to FIG. 3, the data line 10 is electrically connected to two columns of sub-pixels, and the gate line group may include two gate lines at this time;

Or, referring to FIG. 5 and FIG. 6 , the data lines 10 are electrically connected to four columns of sub-pixels, and at this time the gate line group may include four gate lines.

Wherein, the division of the gate line groups has been introduced with examples in the above content, and details may be referred to the above content, and repeated descriptions will not be repeated.

It should be noted that the number of grid lines included in the grid line group can be set according to actual needs.

For example, if the area requirement for the non-display area is small, more wires can be set in the non-display area, and the more gate lines the gate line group includes, the more wiring between the shift registers in the non-display area. The more the non-display area is, the more the number of gate lines included in the gate line group can be set to make full use of the non-display area and greatly reduce the power consumption of the display.

For another example, if the requirements for the area of the non-display area are relatively high, and the requirements for the structural complexity of the display panel are relatively high, the space in the non-display area may be small, and it may not be possible to provide sufficient space for setting more wiring. , at this time, the number of gate lines included in the gate line group can be set to be small, so as to reduce the wiring, thereby reducing the occupied area of the non-display area, and at the same time, it is beneficial to simplify the wiring setting, so as to simplify the complexity of the display panel structure, so as to facilitate Fabrication of display panels.

In this way, not only can the gate turn-on signal be sequentially input to each gate line in the gate line group, but also the data line can be connected to each sub-pixel with the same color and electrically connected to each gate line in the same gate line group. When data signals of the same polarity are input, the switching times of the data signals are reduced, and the power consumption of the display panel is reduced; at the same time, the electrical connection between the data lines and the sub-pixel columns and the division of the gate line groups can also be adjusted according to actual needs. setting, thereby improving the flexibility of display panel design to meet the needs of various application scenarios.

During specific implementation, in the embodiment of the present invention, the first phase difference between the gate-on signals input from every two adjacent gate lines in the same gate line group is the same.

For example, taking the timing diagram shown in FIG. 7 as an example, T0 in the diagram may represent the first phase difference, and G1 to G16 marked in the diagram represent the time when each gate line inputs the gate-on signal, and, according to the above description, it can be known that , the gate line G1 , the gate line G5 , the gate line G9 and the gate line G13 can be regarded as a gate line group. Wherein, the time difference between the rising edge of the gate opening signal input by the gate line G1 and the rising edge of the gate opening signal input by the gate line G5 is the first phase difference T0, and the rising edge of the gate opening signal input by the gate line G5 and the gate line The time difference between the rising edges of the G9 input gate-on signal is also the first phase difference T0.

In this way, it is possible to ensure that each gate line group is sequentially input with a gate open signal, and at the same time, it is also ensured that each gate line is regularly input with a gate open signal, so as to effectively control the charging time of each sub-pixel, thereby realizing the display The driving process of the panel is effectively controlled, so that the display panel can work normally and effectively, and disorder is avoided.

Optionally, in this embodiment of the present invention, the first phase difference may be 3 microseconds to 10 microseconds.

Wherein, the setting size of the first phase difference is related to the pulse width of the clock signal (introduced in the following content), and can be set according to actual needs, as long as each gate line group can be guaranteed to input the gate opening signal sequentially, and the gate line Each gate line in the group is sequentially input with a gate turn-on signal, so as to reduce the switching times of the data signal and reduce the power consumption of the display panel.

Optionally, in this embodiment of the present invention, the first phase difference may be 5 microseconds.

In this way, it is not only beneficial to control the charging time of each sub-pixel, but also enables each sub-pixel to have sufficient charging time in each frame scanning time, which is beneficial to improving the display effect of the display panel.

Specifically, in the embodiment of the present invention, for different gate line groups, in two consecutively driven gate line groups: the gate open signal input by the last driven gate line in the previous gate line group is different from that of the next gate line group. There is a second phase difference between the gate turn-on signals input by the first driven gate line in the line group, and the first phase difference is the same as the second phase difference.

For example, taking the timing diagram shown in FIG. 3 as an example, the G1 to G8 marked in the figure represent the time when each gate line inputs the gate-on signal, and, according to the above description, the gate line G1 and the gate line G5 can be regarded as is a gate line group, and the gate line G3 and the gate line G7 can be regarded as a gate line group. Wherein, in FIG. 3 , the gate line group comprising gate line G1 and gate line G5 and the gate line group comprising gate line G3 and gate line G7 are two continuously driven gate line groups, and gate line G5 is the gate line group in which it is located. The last gate line to be driven, the gate line G3 is the first gate line to be driven in the gate line group, between the rising edge of the gate opening signal input by gate line G1 and the rising edge of the gate open signal input by gate line G5 The time difference is the first phase difference, the time difference between the rising edge of the grid line G5 input gate open signal and the gate line G3 input gate open signal is the second phase difference, the second phase difference and the first phase The differences are all T0, that is, the second phase difference is the same as the first phase difference.

In this way, the driving process of each gate line can be kept consistent, which not only simplifies the complexity of driving the display panel, further reduces the power consumption of the display panel, but also improves the uniformity of the display panel, thereby improving the display effect.

During specific implementation, in order to enable each gate line group to input the gate open signal sequentially, and each gate line in the gate line group to input the gate open signal sequentially, it is necessary to configure the shift register for outputting the gate open signal to the gate line work process control. Wherein, the shift register is usually electrically connected with the clock signal line, and the clock signal provided by the clock signal line can control the output signal of the shift register. Therefore, if the working process of the shift register is to be controlled, it is also necessary to The timing of the clock signal is set.

The driving method provided by the embodiment of the present invention will be described below in combination with the setting of the shift register and the working timing of the clock signal.

Specifically, in the embodiment of the present invention, as shown in FIG. 3 , FIG. 5 and FIG. 6 , the display panel includes: a display area A1 and a non-display area A2 surrounding the display area A1, and the pixels are located in the display area A1;

The non-display area A2 is provided with: a plurality of shift register groups (identifications of the shift register groups are given in the figure), and clock signal line groups electrically connected to each shift register group, and each shift register group includes A plurality of cascaded shift registers, the shift registers are electrically connected to one end of the gate lines; the clock signal line group includes first clock signal lines (such as CK1 to CK8) and second clock signal lines (such as CKB1 to CKB8).

For example, referring to Fig. 3, 8 shift registers are shown in the figure, and each shift register is electrically connected to a gate line, wherein:

The shift registers labeled Y1 and Y5 can be regarded as a group of shift registers, and the group of shift registers is electrically connected to a group of clock signal lines including CK1 and CKB1, and the shift register Y1 and the shift register Y5 between cascades.

The shift registers labeled Y2 and Y6 can be regarded as a group of shift registers, and the group of shift registers is electrically connected to a group of clock signal lines including CK2 and CKB2, and the shift register Y2 and the shift register Y6 between cascades.

The shift registers labeled Y3 and Y7 can be regarded as a group of shift registers, and the group of shift registers is electrically connected to a group of clock signal lines including CK3 and CKB3, and the shift register Y3 and the shift register Y7 between cascades.

The shift registers labeled Y4 and Y8 can be regarded as a group of shift registers, and the group of shift registers is electrically connected to a group of clock signal lines including CK4 and CKB4, and the shift register Y4 and the shift register Y8 between cascades.

That is to say, 4 shift register groups and 4 clock signal line groups are shown in FIG. The second clock signal line (such as CKB1, CKB2, CKB3, CKB4).

For another example, referring to Fig. 5, 16 shift registers are shown in the figure, and each shift register is electrically connected to a gate line, wherein, for the 8 shift registers located on the right side of the figure:

The shift registers labeled Y1 and Y2 can be regarded as a group of shift registers, and the group of shift registers is electrically connected to a group of clock signal lines including CK1 and CKB1, and the shift register Y1 and the shift register Y5 between cascades.

The shift registers labeled Y5 and Y6 can be regarded as a group of shift registers, and the group of shift registers is electrically connected to a group of clock signal lines including CK2 and CKB2, and the shift register Y5 and the shift register Y6 between cascades.

The shift registers labeled Y9 and Y10 can be regarded as a group of shift registers, and the group of shift registers is electrically connected to a group of clock signal lines including CK3 and CKB3, and the shift register Y9 and the shift register Y10 between cascades.

The shift registers labeled Y13 and Y14 can be regarded as a group of shift registers, and the group of shift registers is electrically connected to a group of clock signal lines including CK4 and CKB4, and the shift register Y13 and the shift register Y14 between cascades.

For the 8 shift registers on the left side of the figure:

The shift registers labeled Y3 and Y4 can be regarded as a group of shift registers, and the group of shift registers is electrically connected to a group of clock signal lines including CK5 and CKB5, and the shift register Y3 and the shift register Y4 between cascades.

The shift registers labeled Y7 and Y8 can be regarded as a group of shift registers, and the group of shift registers is electrically connected to a group of clock signal lines including CK6 and CKB6, and the shift register Y7 and the shift register Y8 between cascades.

The shift registers labeled Y11 and Y12 can be regarded as a group of shift registers, and the group of shift registers is electrically connected to a group of clock signal lines including CK7 and CKB7, and the shift register Y11 and the shift register Y12 between cascades.

The shift registers labeled Y15 and Y16 can be regarded as a group of shift registers, and the group of shift registers is electrically connected to a group of clock signal lines including CK8 and CKB8, and the shift register Y15 and the shift register Y16 between cascades.

That is to say, 8 shift register groups and 8 clock signal line groups are shown in FIG. , CK6, CK7, CK8) and the second clock signal lines (such as CKB1, CKB2, CKB3, CKB4, CKB5, CKB6, CKB7, CKB8).

To illustrate, in the embodiment of the present invention, combined with the schematic structural diagram of the connection relationship of the shift registers shown in FIG. 8, the cascading between two shift registers can be understood as:

Referring to Fig. 8, if the upper-stage shift register is represented by Y1, and the lower-stage shift register is represented by Y2, the signal output terminal OUT of the upper-stage shift register Y1 is the signal input of the next-stage shift register Y2 Terminal IN inputs the gate open signal to serve as the start signal of the next-stage shift register Y2, and the signal output terminal OUT of the next-stage shift register Y2 inputs the reset signal terminal RESET of the upper-stage shift register Y1 to open the gate The signal is used as the reset signal of the upper stage shift register Y1.

Moreover, in order to ensure that the cascaded shift registers can work normally and orderly, taking the example shown in Figure 8, each shift register includes a first signal input terminal K1 and a second signal input terminal K2, and the upper stage The first signal input terminal K1 of the shift register Y1 is electrically connected to the first clock signal line CK1, the second signal input terminal K2 is electrically connected to the second clock signal line CKB1, and the first signal input terminal of the next stage shift register Y2 K1 is electrically connected to the second clock signal line CKB1, and the second signal input terminal K2 is electrically connected to the first clock signal line CK1.

It should be noted that the difference between Fig. 5 and Fig. 6 is that the cascading relationship of two adjacent shift registers in the same shift register group is adjusted, such as shift register Y5 and shift register Y5 in Fig. 5 and Fig. 6 Cascade relationship between bit register Y6, cascade relationship between shift register Y13 and shift register Y14, cascade relationship between shift register Y7 and shift register Y8, shift register Y15 and shift register Cascade relationship between Y16.

Moreover, the connection relationship between the subpixels in some subpixel rows and the gate lines on opposite sides is also adjusted. For example, take the green subpixel G filled with sparse black dots in the subpixels in the third row as an example. In FIG. 5, The green subpixel G is electrically connected to the gate line on the side close to the second row of subpixels. In FIG. 6 , the green subpixel G is electrically connected to the gate line on the side away from the second row of subpixels. The connection relationship between other adjusted sub-pixels and gate lines will not be described in detail here, as long as the gate-on signal can be sequentially input to each gate line group, and each gate line in the same gate line group can be sequentially input with a gate-on signal. When, the sub-pixels electrically connected to the same data line and the gate lines in the same gate line group have the same color and input data signals of the same polarity, so as to reduce the switching times of the data signal and reduce the power consumption of the display panel. Can.

In this way, it can be ensured that the cascaded shift registers sequentially input gate open signals to the corresponding electrically connected gate lines, while ensuring that the cascaded shift registers can work normally and orderly, it is also beneficial to realize the gate line The gate-on signal is sequentially input to the group, and each gate line in the gate-line group is sequentially input with the gate-on signal.

Optionally, referring to Fig. 4 and Fig. 7, the driving method may also include:

There is a first phase difference between the first clock signals provided by the first clock signal lines electrically connected to the shift registers corresponding to every two adjacent gate lines in the same gate line group;

There is a first phase difference between the second clock signals provided by the second clock signal lines electrically connected to the shift registers corresponding to every two adjacent gate lines in the same gate line group.

In this way, it is beneficial to realize that the shift registers corresponding to every two adjacent gate lines in the same gate line group sequentially output gate open signals to the corresponding gate lines, so that when the data line is electrically connected to itself and is connected to the same gate line group When the sub-pixels with the same color electrically connected to each gate line in the grid input data signals of the same polarity, the switching times of the data signals can be reduced to the greatest extent, and the power consumption of the display panel can be effectively reduced.

Optionally, referring to Fig. 4 and Fig. 7, the driving method may also include:

In the two gate line groups driven continuously: the first clock signal provided by the first clock signal line electrically connected to the shift register corresponding to the last gate line driven in the last gate line group is the same as the last clock signal in the next gate line group. There is a first phase difference between the first clock signal provided by the first clock signal line electrically connected to the shift register corresponding to the first driven gate line;

In the two gate line groups driven continuously: the second clock signal provided by the second clock signal line electrically connected to the shift register corresponding to the gate line driven last in the previous gate line group is the same as the second clock signal provided by the second clock signal line in the next gate line group. There is a first phase difference between the second clock signals provided by the second clock signal lines electrically connected to the shift registers electrically connected to the first driven gate lines.

In this way, it is beneficial to realize the gate open signal input by the last driven gate line in the previous gate line group and the gate open signal input by the first driven gate line in the next gate line group among the two continuously driven gate line groups. The phase difference between them is the first phase difference, which is conducive to keeping the driving process of each gate line consistent, which not only simplifies the complexity of driving the display panel, further reduces the power consumption of the display panel, but also improves the uniformity of the display panel. performance, thereby improving the display effect.

Optionally, when the gate line group includes M gate lines, in the embodiment of the present invention, as shown in FIG. 4 and FIG. 7 , the driving method may further include:

For two consecutive gate line groups in the odd-numbered or even-numbered driven gate line groups: the first clock provided by the first clock signal line electrically connected to the shift register corresponding to the last driven gate line in the previous gate line group There is a third phase difference between the first clock signal provided by the first clock signal line electrically connected to the shift register corresponding to the first driven gate line in the next gate line group;

In the two consecutive gate line groups in the odd-number driven or even-number driven gate line groups: the second clock signal line provided by the second clock signal line electrically connected to the shift register corresponding to the last driven gate line in the previous gate line group There is a third phase difference between the second clock signal provided by the second clock signal line electrically connected to the shift register corresponding to the first driven gate line in the next gate line group;

Wherein, the third phase difference is M times of the first phase difference.

In this way, the polarities of the data signals input by the sub-pixels electrically connected to the gate lines in the two continuously driven gate line groups can be avoided from being the same, thereby avoiding problems such as image sticking, thereby improving the display effect.

Optionally, in this embodiment of the present invention, as shown in FIG. 3 , FIG. 5 and FIG. 6 , the set number of shift register groups may be 2M.

For example, in FIG. 3 , each gate line group includes 2 gate lines, that is, M is 2, and the number of shift register groups is 4, which is 2 times of 2. For another example, in FIG. 5 and FIG. 6 , each gate line group includes 4 gate lines, that is, M is 4, and the number of shift register groups is 8, which is twice of 4.

In this way, the scanning process of the gate lines in each gate line group can be effectively controlled by setting the shift register group, thereby reducing the switching times of the data signal and reducing the power consumption of the display panel.

Optionally, in this embodiment of the present invention, the non-display area A2 includes two sub-areas (such as Z1 and Z2), and the two sub-areas are respectively located in the non-display area A2 pointed to by the two ends of the gate line;

Each shift register group is set in the same sub-area;

Alternatively, each shift register group is equally divided into two sub-regions.

For example, as shown in FIG. 3, all shift registers are arranged in the same sub-region Z2.

In this way, more space can be left for another sub-region (such as Z1 ), so that other structures can be arranged in the sub-region Z1 to complete the display function of the display panel.

For another example, as shown in FIG. 5 , four of the shift register groups are arranged in the sub-area Z1 , and the remaining four shift register groups are arranged in the sub-area Z2 .

In this way, it is possible to avoid the short-circuit problem caused by the large number of shift registers set in one sub-area, thereby ensuring that the shift registers can work normally and orderly, avoiding mutual interference, and ensuring signal integrity. Normal transmission, improving the reliability of the display panel.

Certainly, in a specific implementation process, selection and setting may be made according to factors such as actual needs and application scenarios, so as to improve the flexibility of the design of the display panel.

Optionally, in order to enable the shift register to work normally, in the embodiment of the present invention, a first start signal line STV1 and a second start signal line STV2 are also provided in the sub-area, as shown in Figure 3, Figure 5 and As shown in Figure 6, wherein, the signal input end of the first stage shift register in each shift register group is electrically connected with the first start signal line or the second start signal line, for receiving the start signal, so that Shift registers work fine.

Specifically, regardless of whether it is the first start signal provided by the first start signal line or the second start signal provided by the second start signal line, as long as it can ensure that the shift register can work normally, and then ensure that each gate line group The grid lines are sequentially input with the gate open signal, and the gate line groups are sequentially input with the open signal. Therefore, in the embodiment of the present invention, the pulse width and output time of the first start signal and the second start signal are not specifically limited. It can be set according to actual needs, so as to improve the flexibility of design, so as to meet the needs of various application scenarios.

It should be noted that, when setting the connection traces between the shift registers, the clock signal lines, the start signal lines, and the connection traces between the shift registers and the gate lines, the clock signal lines, and the start signal lines When, taking the structure in the sub-region Z1 shown in Fig. 5 as an example, in the sub-region Z1, a plurality of shift registers (such as Y1, Y2, Y5, Y6, Y9, Y10, Y13, Y14), A plurality of first clock signal lines (such as CK1, CK2, CK3, CK4), a plurality of second clock signal lines (such as CKB1, CKB2, CKB3, CKB4), and a first clock signal line (such as STV1), and a variety of To connect the wiring, there may be overlapping between the lines that need insulation settings, so in order to avoid short circuits between the lines that need insulation settings, you can set the overlapping lines that need insulation settings and overlap in different layers.

For example, the extension directions of the first clock signal line, the second clock signal line and the first start signal line are all parallel to the column direction, and the shift register is connected with the first clock signal line, the second clock signal line, and the first start signal line. The extension direction of the first connecting wiring (as shown in the dotted circle 1) is parallel to the row direction. At this time, when the extension direction of the data line is parallel to the column direction and the extension direction of the gate line is parallel to the row direction , so that the first clock signal line, the second clock signal line and the first start signal line are all made of the same material and set on the same layer as the data line, and the shift register is connected with the first clock signal line, the second clock signal line, the first start signal line The first connection wiring between the signal lines is made of the same material as the gate line and arranged on the same layer, so as to simplify the manufacturing process and reduce the manufacturing difficulty.

At the same time, in order to enable the shift register to be electrically connected to the corresponding first clock signal line, the second clock signal line and the first start signal line through the first connection line, it can be set as the first connection line that needs to be electrically connected It is electrically connected with the first clock signal line, the second clock signal line and the first start signal line through via holes.

For another example, there may be overlap between the second connecting wires cascaded between the shift registers and the third connecting wires between the shift registers and the gate lines, as shown in the dotted circle 2, although the second The connecting traces overlap with the third connecting traces but need to be insulated to avoid affecting signal transmission, so the second connecting traces and the third connecting traces can be arranged in different layers. The line needs to be electrically connected with the gate line, and most of the line segments in the third connection line extend along the row direction, so the third connection line can be set to be made of the same material and on the same layer as the gate line, so that the third connection line The wire can be in direct contact with the gate line and electrically connected to improve the reliability of the electrical connection; for the second connecting wire, it can be made of the same material and set on the same layer as the data line, or it can be set on the same material and layer as the pixel electrode, or it can be placed on the same layer as the pixel electrode. The other film layers are made of the same material and arranged on the same layer as the other electrode structures, which is not limited here, as long as the second connecting trace is insulated from the third connecting trace.

That is to say, for two kinds of connecting traces that need to be insulated and have overlaps, it is enough to set the two connecting traces in different layers, but which layer each connecting trace is placed on can be determined according to the actual situation. and need to be set, which is not limited here.

The driving process of the display panel will be described below by taking the structure shown in FIG. 5 and the timing diagram shown in FIG. 7 as an example.

The case where the data line marked as D4 in FIG. 5 transmits a data signal to each sub-pixel electrically connected and displays a green screen is taken as an example for illustration.

Shown in conjunction with Fig. 5 and Fig. 7, the first start signal line STV1 at first inputs the first start signal in the shift register Y1, shift register Y5, shift register Y9, shift register Y13 that are electrically connected with it, in the second When the clock signal line CKB1 outputs an effective second clock signal, the shift register Y1 outputs a gate turn-on signal to the correspondingly connected gate line G1, and at this time, the sub-pixels electrically connected to the data line D4 and the gate line G1 are sparse The green sub-pixel G filled with black dots currently needs to display a green image, so the data line D4 outputs a positive polarity data signal to the green sub-pixel G.

After T0 time after the rising edge of the second clock signal output by the second clock signal line CKB1, when the second clock signal line CKB2 outputs a valid second clock signal, the shift register Y5 outputs to the correspondingly connected gate line G5 Gate open signal, at this time, the sub-pixels electrically connected to the data line D4 and the gate line G5 are green sub-pixels G filled with sparse black dots, because the current need to display a green picture, so the data line D4 also sends the green sub-pixel G to the green sub-pixel G. Pixel G outputs a data signal of positive polarity.

After T0 time after the rising edge of the second clock signal output by the second clock signal line CKB2, when the second clock signal line CKB3 outputs an effective second clock signal, the shift register Y9 outputs to the correspondingly connected gate line G9 Gate open signal, at this time, the sub-pixels electrically connected to the data line D4 and the gate line G9 are green sub-pixels G filled with sparse black dots, because the current needs to display a green picture, so the data line D4 is still connected to the green sub-pixels. Pixel G outputs a data signal of positive polarity.

After T0 time after the rising edge of the second clock signal output by the second clock signal line CKB3, when the second clock signal line CKB4 outputs a valid second clock signal, the shift register Y13 outputs to the correspondingly connected gate line G13 Gate open signal, at this time, the sub-pixel electrically connected to the data line D4 and the gate line G13 is a green sub-pixel G filled with sparse black dots, because the current need to display a green picture, so the data line D4 keeps to the green sub-pixel G. Pixel G outputs a data signal of positive polarity.

So far, if G1, G5, G9, and G13 are regarded as the first gate line group, when the gate line group is sequentially input with the gate open signal, the data signal transmitted by the data line D4 always maintains a positive polarity data signal, that is, the data The data signal transmitted by line D4 does not need to be switched.

After the first start signal line STV1 outputs the first start signal for a period of time (this time can be 2 times T0), the second start signal line STV2 sends to the shift register Y3, the shift register Y7, the shift register electrically connected to it. The second start signal is input into the register Y11 and the shift register Y15.

After the T0 time after the rising edge of the second clock signal output by the second clock signal line CKB4, when the second clock signal line CKB5 outputs an effective second clock signal, the shift register Y3 sends a signal to the correspondingly connected gate line G3 Output the gate open signal. At this time, the sub-pixel electrically connected to the data line D4 and the gate line G3 is the blue sub-pixel B filled with a grid pattern. Because a green screen needs to be displayed at present, the data line D4 has no data signal output .

Similarly, after the T0 time after the rising edge of the second clock signal output by the second clock signal line CKB5, and after the T0 time after the rising edge of the second clock signal output by the second clock signal line CKB6, the After T0 time after the rising edge of the second clock signal output by the second clock signal line CKB7, the blue sub-pixels B filled with the grid pattern electrically connected to the data line D4 in FIG. screen, so the data line D4 has no data signal output. That is to say, when G3, G7, G11, and G15 are regarded as the second gate line group, when the gate line group is sequentially input with the gate-on signal, the data line D4 has no data signal output, and thus there is no The case of data signal switching.

After the time T0 after the rising edge of the second clock signal output by the second clock signal line CKB8, when the first clock signal line CK1 outputs a valid first clock signal, the shift register Y2 sends a signal to the correspondingly connected gate line G2 Output the gate open signal. At this time, the sub-pixel electrically connected to the data line D4 and the gate line G2 is the blue sub-pixel B filled with vertical lines. Because a green screen needs to be displayed at present, the data line D4 has no data signal output.

Similarly, after the T0 time after the rising edge of the first clock signal output by the first clock signal line CK1, after the T0 time after the rising edge of the first clock signal output by the first clock signal line CK2, the After T0 time after the rising edge of the first clock signal output by the first clock signal line CK3, the blue sub-pixels B filled with vertical lines electrically connected to the data line D4 in FIG. , so the data line D4 has no data signal output. That is to say, when G2, G6, G10, and G14 are regarded as the third gate line group, when the gate line group is sequentially input with the gate-on signal, the data line D4 has no data signal output, and thus there is no The case of data signal switching.

After the T0 time after the rising edge of the first clock signal output by the first clock signal line CK4, when the first clock signal line CK5 outputs an effective first clock signal, the shift register Y4 sends a signal to the correspondingly connected gate line G4 Output the gate open signal. At this time, the sub-pixels electrically connected to the data line D4 and the gate line G4 are red sub-pixels R filled with horizontal lines. Since a green screen needs to be displayed at present, the data line D4 has no data signal output.

Similarly, after the T0 time after the rising edge of the first clock signal output by the first clock signal line CK5, after the T0 time after the rising edge of the first clock signal output by the first clock signal line CK6, the After T0 time after the rising edge of the first clock signal output by the first clock signal line CK7, the red sub-pixels R filled with horizontal lines electrically connected to the data line D4 in FIG. Therefore, the data line D4 has no data signal output. That is to say, when G4, G8, G12, and G16 are regarded as the fourth gate line group, when the gate line group is sequentially input with the gate-on signal, the data line D4 has no data signal output, and thus there is no The case of data signal switching.

Therefore, when it is necessary to display a red picture at present, for the data line D4, the transmitted data signal only needs to be switched once in the above driving process, and does not need to be continuously switched. Therefore, through the embodiment of the present invention The driving method minimizes the switching times of the data signal, thereby effectively reducing the power consumption of the display panel, further reducing the power consumption of the display device, and prolonging the use time of the display device.

Optionally, in order to realize the touch function, in the embodiment of the present invention, a touch signal line 40 is also provided in the display area A1, as shown in FIG. 3 and FIG. 5 , and the touch signal line 40 is located in two columns of sub-pixels The gap between them is located at a different gap from the data line 10 .

Of course, in FIG. 3 , the touch signal line 40 and the data line 10 can be located in the same film layer, or can be arranged in different layers, which can be set according to actual needs, so as to improve the flexibility of design. Moreover, in the structure shown in FIG. 5 , the touch signal line 40 needs to be arranged in a different layer from the data line 10 to avoid short circuit with other lines, thereby improving the reliability of the display panel.

Based on the same inventive concept, an embodiment of the present invention provides a display panel, as shown in FIG. 3 , FIG. 5 and FIG. 6 , which may include:

Pixels arranged in an array, the pixels include at least three sub-pixels with different colors, each column of sub-pixels is composed of sub-pixels with the same color, and any two adjacent sub-pixels in the row direction and column direction are input The polarity of the data signal is reversed;

A plurality of data lines arranged in the row direction and extending in the column direction, two columns of sub-pixels are arranged between any two adjacent data lines, and each of the data lines is electrically connected to multiple columns of sub-pixels;

a plurality of shift register groups, each of which includes a plurality of cascaded shift registers;

A clock signal line group electrically connected to the shift register group, the clock signal line is used to provide a clock signal for the correspondingly electrically connected shift register;

A plurality of gate lines arranged along the column direction and extending along the row direction, two gate lines are arranged between any two adjacent rows of sub-pixels, the side of the first row of sub-pixels away from the last row of sub-pixels, and one gate line is provided on the side of the last row of sub-pixels away from the first row of sub-pixels; all the gate lines are divided into multiple gate line groups, and the gate line groups include multiple grid lines line, at least one row of sub-pixels is arranged between the sub-pixels electrically connected to any two adjacent gate lines in the group of gate lines;

Wherein, each of the gate lines is electrically connected to one of the shift registers, and each of the gate lines in the gate line group corresponds to the shift registers at the same level in different shift register groups electrical connection;

Each of the gate line groups is sequentially input with a gate open signal, and each of the gate lines in the gate line group is sequentially input with a gate open signal, so that the gate line electrically connected to the same data line and connected to the same gate Each of the sub-pixels electrically connected to each of the gate lines in the line group has the same color and inputs data signals of the same polarity.

In this way, the sub-pixels with the same color that are electrically connected to the same data line and to the gate lines in the same gate line group are sequentially input with data signals of the same polarity, thereby minimizing the polarity of the data signals. The number of switching times, thereby reducing the power consumption of the display panel, reducing the power consumption of the display device, and prolonging the use time of the display device.

Optionally, in the embodiment of the present invention, the set number of the gate line groups may be an integer multiple of 4. For example, the number of grid line groups is 4, 8, 12 or 16, etc., which is not limited here.

In this way, it is beneficial to reduce the number of polarity switching of the data signal, thereby reducing the power consumption of the display panel.

In specific implementation, for the embodiments of the display panel, reference may be made to the embodiments of the display panel introduced above, and repeated descriptions will not be repeated.

Based on the same inventive concept, an embodiment of the present invention provides a display device. The structural schematic diagram of the display device shown in FIG. 9 may include a display panel X;

Wherein, the display panel can be driven by using the above-mentioned driving method provided by the embodiment of the present invention. Alternatively, the display panel may be the same as the above-mentioned display panel provided by the embodiment of the present invention.

In a specific implementation, the display device can be any product or component with a display function such as a mobile phone (as shown in FIG. 9 ), a tablet computer, a television set, a monitor, a notebook computer, a digital photo frame, a navigator, and the like. For the implementation of the display device, reference may be made to the above-mentioned embodiments of the display panel, and repeated descriptions will not be repeated.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims (13)

1. A method for driving a display panel, wherein the display panel comprises: Pixels arranged in an array, the pixels include at least three sub-pixels with different colors, each column of sub-pixels is composed of sub-pixels with the same color, and any two adjacent sub-pixels in the row direction and column direction are input The polarity of the data signal is reversed; A plurality of data lines arranged in the row direction and extending in the column direction, two columns of sub-pixels are arranged between any two adjacent data lines, and each of the data lines is electrically connected to multiple columns of sub-pixels; A plurality of gate lines arranged along the column direction and extending along the row direction, two gate lines are arranged between any two adjacent rows of sub-pixels, the side of the first row of sub-pixels away from the last row of sub-pixels, and one gate line is provided on the side of the last row of sub-pixels away from the first row of sub-pixels; all the gate lines are divided into multiple gate line groups, and the gate line groups include multiple grid lines line, at least one row of sub-pixels is arranged between the sub-pixels electrically connected to any two adjacent gate lines in the group of gate lines; The driving method includes: Each of the gate line groups is sequentially input with a gate open signal, each of the gate lines in the gate line group is sequentially input with a gate open signal, and the data line is electrically connected to itself and connected to the same gate line group. Each of the sub-pixels with the same color electrically connected to each of the gate lines receives a data signal of the same polarity. 2 . The driving method according to claim 1 , wherein the first phase difference between the gate-on signals input to every two adjacent gate lines in the same gate line group is the same. 3 . 3. The driving method according to claim 2, characterized in that, among the two continuously driven groups of gate lines: the last input gate-on signal of the last-driven gate line in the previous group of gate lines is the same as There is a second phase difference between the gate turn-on signals input by the first gate line driven in the next gate line group, and the first phase difference is the same as the second phase difference. 4. The driving method according to claim 2, wherein the display panel comprises: a display area and a non-display area surrounding the display area, and the pixels are located in the display area; The non-display area is provided with: a plurality of shift register groups, and clock signal line groups electrically connected to each of the shift register groups, and each of the shift register groups includes a plurality of cascaded shift A register, the shift register is electrically connected to one end of the gate line; the clock signal line group includes a first clock signal line and a second clock signal line; The driving method also includes: There is the first phase difference between the first clock signals provided by the first clock signal lines electrically connected to the shift registers corresponding to every two adjacent gate lines in the same gate line group; There is the first phase difference between the second clock signals provided by the second clock signal lines electrically connected to the shift registers corresponding to every two adjacent gate lines in the same gate line group. 5. The driving method according to claim 4, further comprising: Among the two gate line groups driven continuously: the first clock signal provided by the first clock signal line electrically connected to the shift register corresponding to the gate line driven last in the previous gate line group, The first phase difference exists between the first clock signal provided by the first clock signal line electrically connected to the shift register corresponding to the gate line driven first in the next gate line group; Among the two continuously driven gate line groups: the second clock signal provided by the second clock signal line electrically connected to the shift register corresponding to the gate line driven last in the previous gate line group, There is the first phase difference between the second clock signal provided by the second clock signal line electrically connected to the shift register corresponding to the gate line driven first in the next gate line group. 6. The driving method according to claim 4, wherein the gate line group comprises M gate lines; The driving method also includes: Among the two consecutive gate line groups in the odd-numbered or even-numbered drive groups: the last-driven gate line in the previous gate line group is electrically connected to the shift register corresponding to the set The first clock signal provided by the first clock signal line, the first clock provided by the first clock signal line provided by the first clock signal line electrically connected to the shift register corresponding to the gate line driven first in the next gate line group There is a third phase difference between the signals; Among the two consecutive gate line groups in the odd-numbered or even-numbered drive groups: the last-driven gate line in the previous gate line group is electrically connected to the shift register corresponding to the set The second clock signal provided by the second clock signal line, the second clock provided by the second clock signal line provided by the second clock signal line electrically connected to the shift register corresponding to the first driven gate line in the next gate line group said third phase difference exists between the signals; Wherein, the third phase difference is M times of the first phase difference. 7. The driving method according to claim 6, characterized in that, the set number of the shift register groups is 2M. 8. The driving method according to claim 4, wherein the non-display area comprises two sub-areas, and the two sub-areas are respectively located in the non-display area pointed to by the two ends of the gate line; Each of the shift register groups is set in the same sub-area; Or, each of the shift register groups is equally distributed in the two sub-regions. 9. The driving method according to any one of claims 2-8, wherein the first phase difference is 3 microseconds-10 microseconds. 10. The driving method according to any one of claims 1-7, wherein the data lines are electrically connected to two columns of sub-pixels, and the gate line group includes two gate lines; Alternatively, the data lines are electrically connected to four columns of sub-pixels, and the gate line group includes four gate lines. 11. A display device, comprising a display panel; The display panel is driven by the driving method according to any one of claims 1-10. 12. A display panel, characterized in that it comprises: Pixels arranged in an array, the pixels include at least three sub-pixels with different colors, each column of sub-pixels is composed of sub-pixels with the same color, and any two adjacent sub-pixels in the row direction and column direction are input The polarity of the data signal is reversed; A plurality of data lines arranged in the row direction and extending in the column direction, two columns of sub-pixels are arranged between any two adjacent data lines, and each of the data lines is electrically connected to multiple columns of sub-pixels; a plurality of shift register groups, each of which includes a plurality of cascaded shift registers; A clock signal line group electrically connected to the shift register group, the clock signal line is used to provide a clock signal for the correspondingly electrically connected shift register; A plurality of gate lines arranged along the column direction and extending along the row direction, two gate lines are arranged between any two adjacent rows of sub-pixels, the side of the first row of sub-pixels away from the last row of sub-pixels, and one gate line is provided on the side of the last row of sub-pixels away from the first row of sub-pixels; all the gate lines are divided into multiple gate line groups, and the gate line groups include multiple grid lines line, at least one row of sub-pixels is arranged between the sub-pixels electrically connected to any two adjacent gate lines in the group of gate lines; Wherein, each of the gate lines is electrically connected to one of the shift registers, and each of the gate lines in the gate line group corresponds to the shift registers at the same level in different shift register groups electrical connection; Each of the gate line groups is sequentially input with a gate open signal, and each of the gate lines in the gate line group is sequentially input with a gate open signal, so that the gate line electrically connected to the same data line and connected to the same gate Each of the sub-pixels electrically connected to each of the gate lines in the line group has the same color and inputs data signals of the same polarity. 13. The display panel according to claim 12, wherein the number of the grid line groups is an integer multiple of 4.